JPH11144467A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology by which a memory device can be precharged sufficiently and, further, a current consumption can be reduced. SOLUTION: A plurality of precharge transistors m1 -m3 which precharge the data lines of a memory device are divided and selectively turned on/off so as to obtain a Gm suitable for an operation speed to reduce the current consumption of the memory device. The memory device has a plurality of switches which are connected in parallel to each other and by which one of a plurality of word lines W and one of a plurality of data lines D1 and D2 are respectively selected and driven to precharge the respective data lines D1 and D2 and has a control circuit which controls the plurality of switches which are connected in parallel to each other and by which the data lines D1 and D2 are precharged and the control circuit has a memory table which selects the precharge switch in accordance with the interrelation between the operation environment temperature of a memory cell and the operation frequency of the memory cell and a timing circuit which sets a time for precharge in accordance with the operation frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for precharging a floating capacitance of a data line.

[0002]

2. Description of the Related Art In a static RAM, an arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively, and each data line is connected to each other. A transistor for precharging is provided for each data line. The storage cells are arranged in a matrix of rows and columns to form a storage array.

In this storage array, a plurality of word lines and a plurality of data lines are respectively provided in a row direction and a column direction.

When a word line in any one row is selected, a large number of memory cells on the selected word line are connected to data lines.

At this time, when a data line in any one column is selected, a memory cell connected to the intersection of the selected data line and the selected word line is selected.

[0006] Then, reading or writing of storage information to the selected storage cell is performed via the selected data line. The reading of the stored information is performed by detecting the potential difference between the two data lines using a differential amplifier.

For this reason, two data lines are charged before reading, and precharging is performed as an operation of adjusting potentials.
In precharge, a precharge transistor is operated before a memory cell is selected, and charges the floating capacitance of the data line.

Since the reading operation is performed by detecting the potential difference by the differential amplifier for detecting the potential difference between the two data lines, the potential difference between the two data lines is generated with a small current from the memory cell. Therefore, the memory cell size is not reduced and the influence of the increase in the floating capacitance of the data line accompanying the increase in the memory capacity is not affected without lowering the operation speed.

However, in order to precharge before reading, a current for charging the stray capacitance of each data line flows through the precharge transistor. Therefore, the total amount of the charging current is proportional to the number of data lines. .

For example, if 64 data lines are arranged and a charging current of 0.15 mA flows per pair of data lines, a total of 0.15 mA × 64 = 9.
A load current of 6 mA flows when selected.

In order to charge a data line, a precharge transistor is required for each data line.
Having four data lines requires 64 precharge transistors. The current required to operate the precharge transistor is, for example, 0.
Assuming that a current of 15 mA flows, a total of 0.1 mA
A current of 5 mA × 64 = 9.6 mA flows to operate the precharge transistor.

Here, when increasing the operating speed, the precharge time is shortened and the Gm of the precharge transistor is increased.

When Gm of the precharge transistor is increased, the gate capacitance of the precharge transistor increases. Further, when Gm of the precharge transistor increases, the gate capacitance of the precharge transistor increases, and the current required for charging the gate capacitance becomes larger than that for charging the data line. There is a problem that a large amount of current is consumed by the circuit.

Conventionally, in order to reduce the charging current, a method of selectively controlling precharge for each data line has been adopted.
The charge of the data line and the charge of the gate capacitance of the precharge transistor were reduced.

However, when connected as a memory of a microcomputer, a circuit configuration in which the address is determined before the precharge cannot be taken, and a circuit configuration in which the address is determined after the completion of the precharge is not used. And the address is not fixed.

Therefore, there is a problem that it is not possible to select the precharge for each data line because it is not known which data line should be precharged during the precharge period.

If the address before the precharge,
If the data line to be precharged is determined, an address that has not been determined will be used, and the wrong data line will be precharged. Problems that do not occur.

For this reason, the precharge cannot be selectively controlled for each data line. An example for solving such a problem is disclosed in Japanese Patent Application Laid-Open No. 61-9892. In this publication, an arbitrary storage cell among a large number of storage cells is selected by selectively driving a plurality of word lines and a plurality of data lines, and each data line is precharged. Storage device in which an impedance element for each data line is provided, and the equivalent impedance of each impedance element is variably controlled for each data line, and only the impedance element provided for the selected data line is used. It discloses that the impedance is relatively reduced.

This control is particularly suitable for a static RAM, and is connected to each data line from a power supply via an nMOS transistor for precharging, and a current required for each data line flows through a gate terminal of the nMOS transistor. As described above, a pMOS transistor is connected in series between a power supply and a ground potential so that a control variable voltage can be supplied, and the gate terminal of the nMOS transistor is connected to the connection point to operate as an impedance element. ing.

However, as described in this publication, there is a case where an undetermined address is used, and a wrong data line is precharged.
There remains a problem that the data line to be read is not completely precharged.

[Object of the Invention] An object of the present invention is to provide a technique for sufficiently precharging a memory device and reducing current consumption.

[0022]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention selectively drives a plurality of word lines and a plurality of data lines, respectively, so that any one of a plurality of storage cells can be selected. A cell is selected and a storage device having a plurality of precharge transistors for precharging each of the data lines in parallel, wherein the time for charging the stray capacitance of the data lines is reduced by the plurality of precharge transistors. A control circuit for variably controlling the Gm of the precharge transistor by switching is provided, and a selection circuit for selecting a minimum Gm precharge transistor whose charging is completed within a predetermined time is provided. Further, the selection is performed by selectively controlling the Gm according to the temperature and the manufacturing conditions of the semiconductor.

Further, according to the present invention, an arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively. A storage device having a plurality of precharge switches for precharging each in parallel, comprising a control circuit for selectively controlling a plurality of precharge switches connected in parallel for precharging the data lines, wherein the control circuit includes: A memory table for selecting the precharge switch based on a correlation between an operation environment temperature of the storage cell and an operation frequency of the storage cell; and a timing circuit for setting the precharge time from the operation frequency. It is characterized by.

Further, according to the present invention, an arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively. A storage device having a plurality of precharge switches for precharging each in parallel, comprising a control circuit for selectively controlling a plurality of precharge switches connected in parallel for precharging the data lines, wherein the control circuit includes: A memory table for selecting the precharge switch based on a correlation between a manufacturing condition of the storage cell and an operating frequency of the storage cell, and a timing circuit for setting the precharge time from the operating frequency. Features.

Further, by selectively driving a plurality of word lines and a plurality of data lines, an arbitrary one of a large number of storage cells is selected, and each of the data lines is pre-selected. A storage device having a plurality of precharge switches for charging in parallel, comprising: a control circuit for selectively controlling the plurality of precharge switches connected in parallel for precharging the data lines, wherein the control circuit includes the storage device. A memory table for selecting the precharge switch based on a correlation between a cell manufacturing condition and an operating environment temperature of the storage cell; and a timing circuit for setting the precharge time from the operating environment temperature. Features.

According to the present invention, a precharging transistor (switch) for precharging a data line of a storage device is provided with a transistor so that Gm (overall transconductance) suitable for an operation speed can be obtained. Is divided and the selection control is performed, thereby reducing the current consumption of the storage device.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Hereinafter, a representative embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a storage device according to the present invention.

The storage device shown in FIG. 1 is a MOS static RAM configured as a semiconductor storage device, and operates according to a static system.

The static RAM shown in FIG. 1 has a storage array 1 in which a large number of storage cells M11 to Mmn are arranged in a matrix of rows and columns.

The storage array 1 includes a plurality of word lines W
And two or more pairs of data lines D1 and D2 are X
The wires are wired in the direction (row direction) and the Y direction (column direction).

There are provided address buffers 11 and 21, an X decoder 12, and a Y decoder 22. By these, the address signal Ai is divided into two alternative selection signals X1 to X
m, Y1 to Yn.

One of the selection signals is an X selection signal X1 to X1.
Xm is provided to each word line W via the X driver 13. Thereby, only one of the word lines W is selected and activated.

The other selection signal is given to the Y selection switch row 23 as Y selection signals Y1 to Yn. Then, via this Y selection switch 23, one pair of data lines D1 and D2 is selected and connected to the read sense circuit 31. In addition, a write / read control circuit 32 and the like are provided.

The write / read control circuit 32 has an externally applied write control signal (write enable).
Operated by WE and chip select signal CS.

When the write enable WE and the chip select signal CS are both activated, when the storage device enters the write mode, the write data Di is written to the storage cell selected by the address signal Ai. When the write enable WE is inactive and the chip select signal CS becomes active, the storage device enters the read mode.

In the read mode, the contents stored in the memory cell selected by the address signal Ai are output from the read sense circuit 31 as read data Do.

The data lines D1 and D2 are connected to the precharge transistors m before the read operation.
Is to be pre-charged.

The T1 period in FIG. 2 corresponds to the precharge period, and when the word line W is not selected, that is, the transistor Q1 for turning on / off the flip-flop of the memory unit is turned on.
This is performed in the state of FF.

The precharge transistor m shown in FIG. 1 includes a plurality of p-channel MOS field effect transistors m1 to m.
n, and gm select transistors g1 to gn that control the gates thereof.
By setting the gates of 1 to mn to GND, predetermined transistors m1 to mn are operated.

The transistors m1 to mn are p-channel transistors.
Thereby, the potentials of the data lines D1 and D2 are pulled toward the potential side of the power supply Vcc.

In this precharge operation, during the read operation, the read sense amplifier is connected to the floating capacitance C1 of the data line.
In order not to be affected by C2, data lines D1, D2
Are set to the same potential.

When the precharge operation is completed and the word line W is selected and activated, the transistor Q1 is turned on along the selected word line. As a result, the storage cells Mxy on the selected word line W are connected to the data lines D1 and D2, respectively.
Connected to.

When the data lines D1 and D2 are connected to the storage cell Mxy, the potentials of the data lines D1 and D2 change complementarily according to the storage contents of the storage cell Mxy. At this time,
The sense amplifiers 31 composed of operation amplifiers are D1, D
2 is detected, and the stored content of Mxy is read. The read operation timing corresponds to the period T2 in FIG.

The outline of the operation of the MOS static RAM according to the present embodiment has been described above. The precharge operation, which is a feature of the present invention, will be described in more detail.

Conventionally, the precharge transistor m is constituted by one, and the value gm of the precharge transistor m is designed at the time of designing, and is fixed at a constant value after manufacturing the LSI.

However, in this embodiment, the gm of the precharge transistor m is selectively controlled by the precharge transistor selection circuit 50.

Precharge transistor selection circuit 50
Output preselection timing signals 54 from the precharge timing generation circuit, and output the two signals to the gates g1 to g3.
, One of the precharge transistors m1 to m3 operates to precharge the data lines D1 and D2.

The precharge transistors m1 to mn
Can be selected by selecting a large Gm at the time of high-speed operation and selecting a small Gm at the time of low-speed operation by selecting a Gm suitable for the required speed.

FIG. 2 is a timing chart for the high-speed operation and the low-speed operation. In FIG. 2, prior to the data reading in the period T2, the precharge time in the period T1 is short in the high-speed operation and is long in the low-speed operation.

For the adjustment of Gm, a small Gm can be selected by selecting only m1, and a Gm three times the above can be obtained by selecting three of m1, m2, and m3.

The precharge timing generation circuit 55
Until the precharge is completed by the selected Gm transistor, the time for outputting 0 in the circuit that outputs 0 is determined by the floating capacitances C1, C2 and Gm of the data line.

For example, in a system using this memory as the memory of the microcomputer, when the microcomputer operates at high speed,
By shortening the precharge time for selecting a large Gm, the speed of the memory can be increased. Conversely, during low-speed operation, a small gm can be selected to reduce current consumption.

FIG. 3 is a conceptual diagram showing an example of the contents of the precharge transistor selection circuit 50 and the precharge timing generation circuit 55 in particular. The precharge transistor selection circuit 50 operates at an operating temperature and an operating frequency (operating speed).
Gm for the g selection signals 51-53 from the relationship with Fmax
Gm selection table 56 as a memory for setting
and a decoder for converting m to g selection signals 51 to 53. The g selection signals 51 to 53 are OR circuits g1 to g3.
Supplied to Further, the precharge timing generation circuit 55 sets a precharge time according to a set temperature from the precharge transistor selection circuit 50 in accordance with the chip select signal, and supplies a precharge time signal to the OR circuits g1 to g3. And the temperature and operating frequency Fma
According to x, the bit line to be precharged is precharged with a current value according to Gm.

Further, as shown in FIG.
In order to obtain the required memory speed, Gm with respect to temperature is preprogrammed in the memory table in the precharge transistor selection circuit 50 so that the required memory speed can be obtained, and the optimum Gm for the required memory speed is selected. As a result, current consumption can be further reduced.

For example, to obtain Fmax4 at the temperature of 2, the result of operating two precharge transistors is obtained from the Gm selection table 56, and the decoder circuit 5
5, the g1 selection signal 51 and the g2 selection signal 52 are selected, and the precharge transistors m1 and m2 operate.

[Second Embodiment] As a second embodiment, as shown in FIG. 4, the conditions at the time of manufacturing, for example, the mutual conductance of each precharge MOS transistor are different depending on the manufacturing conditions. The Gm capability difference due to the variation condition or the Gm for the manufacturing condition so that the required memory speed can be obtained is programmed in the table 56 in advance, and the Gm optimal for the required memory operating frequency is selected. By doing so, the current consumption can be further reduced.

FIG. 4 is a conceptual diagram showing an example of the contents of the precharge transistor selection circuit 50 and the precharge timing generation circuit 55. The precharge transistor selection circuit 50 Gm indicating how many transistors are to be precharged is set from the relationship between the conditions at the time of manufacturing the cell and the operating frequency Fmax. Next, the signals are transmitted to the g selection signals 51 to 53 via a decoder for converting the value of Gm into the g selection signals 51 to 53, and the OR circuits g1 to g
3 is supplied. Further, the precharge timing generation circuit 55 sets the precharge time according to the conditions at the time of manufacture from the precharge transistor selection circuit 50 in response to the chip select signal, and also sets the OR circuits g1 to g
3 is supplied with a precharge time signal, and the operating frequency Fma
According to x and one of the manufacturing conditions of the memory cell, for example, a diffusion condition, a precharged bit line is precharged with a current value according to Gm.

As described above, by selecting the minimum precharge transistors m1 to mn, the gate capacitance of m1 to mn is reduced, and the current required for charging the gate capacitance of these transistors and operating the transistor can be reduced. . The degree of reduction of this current is, for example, Gm is small, and if the gate capacitance of m1 whose operation speed is slow is half of m2, the consumption current is I = fCV (C is the parasitic capacitance of the memory cell bit line, and V is the power supply voltage Vcc. ).

Further, as described in the section of the problem, the current required for precharging occupies a large part of the whole, so that the current consumption can be greatly reduced.

Here, Gm is controlled by 1) a method of simply selecting a device capable of obtaining a desired operation speed, 2) a method of programming by a microcomputer or the like, and selecting by a temperature, a manufacturing condition, and a power supply voltage; 3). Attempting to read the memory, the written data and the read data become equal, which makes it possible to feed back the optimum Gm for the normal operation of the memory.

In the above embodiment, an example is shown in which the memory table 56 in the precharge transistor selection circuit 50 two-dimensionally shows the relationship between the ambient temperature and the operating frequency, and the relationship between the manufacturing conditions and the operating frequency. It is of course possible to turn on a predetermined number of MOS transistors with Gm determined three-dimensionally using a memory table to perform precharge.

In the above embodiment, the precharge of the static RAM has been described.
In the case of an onous dynamic RAM, the present invention can be applied to precharge at the time of bank switching, and the same effect can be obtained.

Further, in a large-capacity DRAM, precharging is performed for bank switching. Also in this case, Gm is switched according to the operating temperature, DRAM manufacturing conditions, and the like, and precharging is performed with an appropriate current value. Although the number of precharges in the SRAM is not as large as that of the data line, the power consumption can be reduced.

Further, in the above description, the case where the present precharge is applied to the MOS static RAM technology has been described. However, the present invention is not limited to this. For example, a FRAM to be developed in the future, such as a ROM or a dynamic RAM, is used. Of course, it can also be applied to other memory cells and the like.

[0065]

As described above, the Gm of the precharge transistor depends on the operation speed, especially when reading data.
, The gate capacity of the precharge transistors connected by the number of data lines can be reduced, and the current consumption can be reduced.

The method of variably controlling Gm is: 1) a method of selecting a table in advance according to the operation speed; 2) a method of programming by a microcomputer or the like and selecting by temperature, manufacturing conditions and power supply voltage; 3) a memory Gm suitable for the operation speed can be selected by a method of performing readout and feeding back the optimum gm that makes the written data equal to the read data, and the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention.

FIG. 2 is a timing chart showing the timing of the storage device according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a main part of the storage device shown in FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the main part of the storage device shown in FIG. 1;

FIG. 5 is a circuit block diagram for precharge according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 storage cell array Ai address signal 11, 21 address buffer 12 X decoder 13 X driver 22 Y decoder 23 Y selection switch array X1 to Xm word line selection signal Y1 to Yn data line selection signal M11 to Mmn storage cell W word line D1 to D2 Data line 31 Read sense amplifier 32 Write / read control m1, m2, m3 Precharge transistors g1, g2, g3 OR gate 50 Precharge transistor selection circuit 51 g1 selection signal 52 g2 selection signal 53 g3 selection signal 54 Precharge timing signal 55 precharge timing generation circuit 56 Gm selection table

Claims (7)

[Claims] An arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively, and each of the data lines is precharged. A storage device having a plurality of pre-charge transistors in parallel, the control circuit variably controlling the Gm of the pre-charge transistors by switching the plurality of pre-charge transistors to charge the floating capacitance of the data line. And a selection circuit for selecting a minimum Gm precharge transistor whose charging is completed within a predetermined time. 2. The storage device according to claim 1, wherein said selection is performed by selectively controlling said Gm according to temperature and semiconductor manufacturing conditions. 3. An arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively, and each of the data lines is precharged. A storage device having a plurality of precharge switches for performing parallel control, the control circuit selectively controlling a plurality of precharge switches connected in parallel for precharging the data lines, wherein the control circuit includes A memory table for selecting the precharge switch based on a correlation between an operating environment temperature and an operating frequency of the storage cell; and a timing circuit for setting the precharge time from the operating frequency. Storage device. 4. An arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively, and each of the data lines is precharged. A storage device having a plurality of precharge switches for performing parallel control, the control circuit selectively controlling a plurality of precharge switches connected in parallel for precharging the data lines, wherein the control circuit includes A memory comprising: a memory table for selecting the precharge switch based on a correlation between manufacturing conditions and an operation frequency of the storage cell; and a timing circuit for setting a time for the precharge from the operation frequency. apparatus. 5. An arbitrary memory cell among a large number of memory cells is selected by selectively driving a plurality of word lines and a plurality of data lines, respectively, and each of the data lines is precharged. A storage device having a plurality of precharge switches for performing parallel control, the control circuit selectively controlling the plurality of precharge switches connected in parallel to precharge the data lines, wherein the control circuit includes the storage cell. A memory table for selecting the precharge switch based on a correlation between the manufacturing conditions and the operating environment temperature of the storage cell, and a timing circuit for setting the precharge time from the operating environment temperature. Storage device. 6. The storage device according to claim 3, wherein the storage cell is an SRAM or a DRAM.
A storage device, which is a RAM. 7. The storage device according to claim 4, wherein said precharge switch is a MOS transistor.
A transistor, wherein the control circuit includes the plurality of MOs.
A storage device, wherein Gm of the precharge switch is made variable by turning on / off an S transistor.