JPH11142474A - Auxiliary device for testing flat plate-like inspected body and its manufacture - Google Patents

Auxiliary device for testing flat plate-like inspected body and its manufacture

Info

Publication number
JPH11142474A
JPH11142474A JP9325183A JP32518397A JPH11142474A JP H11142474 A JPH11142474 A JP H11142474A JP 9325183 A JP9325183 A JP 9325183A JP 32518397 A JP32518397 A JP 32518397A JP H11142474 A JPH11142474 A JP H11142474A
Authority
JP
Japan
Prior art keywords
substrate
auxiliary device
shape
lugs
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9325183A
Other languages
Japanese (ja)
Inventor
Yoshie Hasegawa
義栄 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micronics Japan Co Ltd
Original Assignee
Micronics Japan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micronics Japan Co Ltd filed Critical Micronics Japan Co Ltd
Priority to JP9325183A priority Critical patent/JPH11142474A/en
Publication of JPH11142474A publication Critical patent/JPH11142474A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an auxiliary device not changing the height size and apex shape of bump electrodes by forming multiple conductive lugs at intervals on one face of an insulating substrate, and forming recesses having the same cross sectional area from the top faces to the prescribed depth on the top faces of the lugs parallel with the substrate. SOLUTION: An IC chip 12 is provided with multiple bump electrodes 16 on a flat plate-like device main body 14, and the bump electrodes 16 are formed into a semispherical shape by soldering on electrodes 18. An auxiliary device 10 is provided with conductive through holes 22 formed on an insulating substrate 20, first lugs 24 and second lugs 26. The lugs 24, 26 closing the through holes 22 are integrated by connecting members 28 made of the same material and are electrically connected. Each lug 24 has a hemispherical shape with a top face 30 parallel with the substrate 20, each lug 26 has a hemispherical shape and each member 28 has a cylindrical shape. Each top face 30 has a recess 32, and the recess 32 has a cross sectional area and a cross sectional shape to the prescribed depth position. The lugs 24 and the electrodes 16 are pressed to each other during a test.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路のような
平板状被検査体の通電試験に用いる補助装置に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to an auxiliary device used for a current test of a flat test object such as an integrated circuit.

【0002】[0002]

【従来の技術】フィリップチップのような集積回路チッ
プ(ICチップ)は、一般に、多数の電極(端子)を一
方の面に有しており、また配線基板のような回路基板に
重ねられて電極を回路基板の電極(すなわち、パッド電
極)に接続される。ICチップの各電極は、半田により
形成された半球状突起(すなわち、バンプ電極)であ
り、回路基板のパッド電極に当接された状態で加熱され
ることにより、パッド電極に電気的に接続される。
2. Description of the Related Art In general, an integrated circuit chip (IC chip) such as a flip chip has a large number of electrodes (terminals) on one surface, and the electrodes are stacked on a circuit board such as a wiring board. Is connected to an electrode of the circuit board (that is, a pad electrode). Each electrode of the IC chip is a hemispherical protrusion (that is, a bump electrode) formed by solder, and is electrically connected to the pad electrode by being heated while being in contact with the pad electrode of the circuit board. You.

【0003】この種のICチップは、その良否の検査の
ために、回路基板に配置される前に通電試験をされる。
この種のICチップの通電試験は、一般に、ニードルタ
イプのプローブカードの代わりに、複数の突起を基板に
形成した補助装置を用いて行われる。
[0003] An IC chip of this type is subjected to a conduction test before being placed on a circuit board in order to inspect its quality.
In general, this type of IC chip energization test is performed using an auxiliary device having a plurality of protrusions formed on a substrate, instead of a needle type probe card.

【0004】この種の補助装置の1つとして、多数の突
起を、それらの先端が集積回路チップのバンプ電極と同
様にランダムに又はマトリクス状となるように、基板に
高密度に配置したものがある(特開平8−327659
号公報)。
[0004] One type of auxiliary device is one in which a large number of protrusions are densely arranged on a substrate such that their tips are randomly or in a matrix like the bump electrodes of an integrated circuit chip. (Japanese Unexamined Patent Application Publication No. Hei 8-327659)
No.).

【0005】この補助装置において、各突起はICチッ
プの側に開放する凹所を有し、各突起の凹所は基板側ほ
ど小さくなる断面積を有する。通電試験時、各突起は、
ICチップのバンプ電極に押圧される。これにより、半
田製の各バンプ電極の頂部は突起の凹所に食い込む。
In this auxiliary device, each projection has a recess opening toward the IC chip, and the recess of each projection has a cross-sectional area that becomes smaller toward the substrate. During the energization test, each protrusion
It is pressed by the bump electrode of the IC chip. As a result, the top of each bump electrode made of solder bites into the recess of the projection.

【0006】上記の補助装置では、各突起の凹所の断面
積が基板側ほど小さくなるから、バンプ電極の基部(デ
バイス本体の側の部位)がデバイス本体の側に押し潰さ
れるように変形するとともに、バンプ電極の頂部がその
軸線側(凹所の中心側)に押し潰されるように変形され
る。バンプ電極のそのような変形のうち、基部の変形
は、基部を膨出させるが、バンプ電極の高さ寸法及び頂
部の形状に影響を与えない。
In the above auxiliary device, since the cross-sectional area of the recess of each projection becomes smaller toward the substrate, the base of the bump electrode (the part on the device body side) is deformed so as to be crushed by the device body side. At the same time, the bump electrode is deformed such that the top portion is crushed toward the axis (the center of the recess). Of such deformations of the bump electrode, deformation of the base causes the base to bulge, but does not affect the height dimension and the top shape of the bump electrode.

【0007】しかし、バンプ電極の頂部がその軸線側に
押し潰されると、バンプ電極の頂部が押し伸ばされるか
ら、バンプ電極の高さ寸法が不規則に大きくなるととも
に、バンプ電極の頂部の形状が不規則に変形する。この
ようにバンプ電極の高さ寸法又は頂部の形状が不規則に
変化したICチップは、これを回路基板に実装すると、
回路基板のパッド電極に接触しないバンプ電極が存在
し、その結果回路基板に正しく接続されない。
However, when the top of the bump electrode is crushed toward its axis, the top of the bump electrode is pushed and stretched, so that the height of the bump electrode becomes irregularly large and the shape of the top of the bump electrode is changed. Deform irregularly. As described above, when the height of the bump electrode or the shape of the top portion is irregularly changed, when the IC chip is mounted on the circuit board,
There are bump electrodes that do not contact the pad electrodes of the circuit board, resulting in improper connection to the circuit board.

【0008】[0008]

【発明が解決しようとする課題】それゆえに、バンプ電
極の高さ寸法及び頂部の形状を変化させない補助装置と
することは重要である。
Therefore, it is important to provide an auxiliary device which does not change the height and the shape of the top of the bump electrode.

【0009】[0009]

【解決手段、作用および効果】本発明の補助装置は、電
気絶縁性の基板と、該基板の一方の面に間隔をおいて形
成された導電性の複数の突起とを含む。各突起は、基板
とほぼ平行の頂面を有するとともに、この頂面に開放す
る凹所を有する。各凹所は、頂面から所定の深さまでほ
ぼ同じ断面積を有する。
An auxiliary device according to the present invention includes an electrically insulating substrate and a plurality of conductive projections formed on one surface of the substrate at intervals. Each projection has a top surface that is substantially parallel to the substrate and has a recess that opens into the top surface. Each recess has approximately the same cross-sectional area from the top surface to a predetermined depth.

【0010】各突起をICチップのバンプ電極に押圧す
ると、バンプ電極の頂部は、突起の凹所に受け入れられ
る。しかし、各突起の凹所がその頂面から所定の深さま
でほぼ同じ断面積を有すると、バンプ電極の基部をデバ
イス本体の側に押し潰す力はバンプ電極に作用するが、
頂部をその軸線の側に押し潰す力はバンプ電極に作用し
ない。このため、本発明の補助装置は、バンプ電極の高
さ寸法及び頂部の形状を変化させない。
When each projection is pressed against the bump electrode of the IC chip, the top of the bump electrode is received in the recess of the projection. However, when the recess of each projection has substantially the same cross-sectional area from the top surface to a predetermined depth, the force of crushing the base of the bump electrode toward the device body acts on the bump electrode,
The force that crushes the top toward its axis does not act on the bump electrode. For this reason, the auxiliary device of the present invention does not change the height dimension and the top shape of the bump electrode.

【0011】基板を厚さ方向へ貫通する導電性の複数の
スルーホールを基板に形成し、各スルーホールを少なく
とも一端において突起により閉塞してもよい。また、各
スルーホールを少なくとも他端において閉塞する半球状
の第2の突起を基板の他方の面に形成してもよい。
A plurality of conductive through holes penetrating the substrate in the thickness direction may be formed in the substrate, and each through hole may be closed at least at one end by a projection. Further, a hemispherical second projection for closing each through hole at least at the other end may be formed on the other surface of the substrate.

【0012】好ましい実施例において、凹所は一定断面
積の間の部分において同じ断面形状を有する。また、各
突起は、平板状の形を有していてもよいが、好ましい実
施例においては、頂部が基板とほぼ平行に除去された截
頭半球状の形を有する。
[0012] In a preferred embodiment, the recess has the same cross-sectional shape at portions between constant cross-sectional areas. Also, each protrusion may have a plate-like shape, but in a preferred embodiment has a truncated hemispherical shape with the top removed substantially parallel to the substrate.

【0013】上記のような補助装置は、導電性の複数の
突起を電気絶縁性の基板の一方の面に間隔をおいて形成
し、各突起の頂部を基板とほぼ平行に除去し、各突起の
頂面に開放しかつ前記頂面から所定の深さ位置までほぼ
同じ断面積を有する凹所を各突起に形成することにより
製作することができる。
In the auxiliary device as described above, a plurality of conductive protrusions are formed at intervals on one surface of an electrically insulating substrate, and the top of each protrusion is removed substantially in parallel with the substrate. Can be manufactured by forming a recess in each projection that is open to the top surface and has substantially the same cross-sectional area from the top surface to a predetermined depth position.

【0014】また、突起を形成する前に、基板を厚さ方
向へ貫通する導電性の複数のスルーホールを基板に形成
し、その後スルーホールを少なくとも一端において閉塞
するように各突起を形成することができる。さらに、各
スルーホールを少なくとも他端において閉塞する半球状
の第2の突起を基板の他方の面に形成することができ
る。凹所はドリル加工により横断面積及び横断面形状が
同じ円形に形成することができる。
Further, before forming the projections, a plurality of conductive through holes penetrating the substrate in the thickness direction are formed in the substrate, and then each projection is formed so as to close the through holes at at least one end. Can be. Furthermore, a hemispherical second projection that closes each through hole at least at the other end can be formed on the other surface of the substrate. The recess can be formed into a circular shape having the same cross-sectional area and cross-sectional shape by drilling.

【0015】[0015]

【発明の実施の形態】図1から図3を参照するに、補助
装置10は、ICチップ12の通電試験に用いられる。
ICチップ12は、平板状のデバイス本体14にランダ
ムに又はマトリクス状に設けられた複数のバンプ電極1
6を有する。各バンプ電極16は、デバイス本体14の
一方の面に設けられた電極18に半田により半球状に形
成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 to 3, an auxiliary device 10 is used for an energization test of an IC chip 12. FIG.
The IC chip 12 includes a plurality of bump electrodes 1 provided randomly or in a matrix on a flat device body 14.
6. Each bump electrode 16 is formed in a hemispherical shape by soldering on an electrode 18 provided on one surface of the device body 14.

【0016】補助装置10は、電気絶縁性の基板20
と、該基板にランダムに又はマトリクス状に形成された
導電性の複数のスルーホール22と、各スルーホール2
2をその一端において閉塞する第1の突起24と、各ス
ルーホール22をその他端において閉塞する第2の突起
26とを備える。
The auxiliary device 10 comprises an electrically insulating substrate 20
A plurality of conductive through holes 22 formed randomly or in a matrix on the substrate;
2 is provided with a first projection 24 closing one end thereof, and a second projection 26 closing each through hole 22 at the other end.

【0017】基板20は、ポリイミドのような合成樹脂
材料により形成されており、また、可撓性又は剛性を有
する。スルーホール22は、導電性材料によりICチッ
プ12のバンプ電極16の配置パターンに対応するパタ
ーンに形成されている。第1及び第2の突起24及び2
6は、ニッケルのような導電性材料から形成されてい
る。
The substrate 20 is formed of a synthetic resin material such as polyimide, and has flexibility or rigidity. The through holes 22 are formed in a pattern corresponding to the arrangement pattern of the bump electrodes 16 of the IC chip 12 by using a conductive material. First and second projections 24 and 2
6 is formed from a conductive material such as nickel.

【0018】同じスルーホール22を閉塞する第1及び
第2の突起24及び26は、対応するスルーホール22
内に設けられた同じ材料からなる接続部材28により一
体化されており、従ってスルーホール22及び接続部材
28により電気的に接続されている。接続部材28は設
けなくてもよい。
The first and second projections 24 and 26 closing the same through-hole 22 are provided with corresponding through-holes 22.
It is integrated by a connecting member 28 made of the same material provided therein, and is therefore electrically connected by the through hole 22 and the connecting member 28. The connecting member 28 may not be provided.

【0019】各第1の突起24は基板20とほぼ平行の
頂面30を有する截頭半球状の形状を有し、各第2の突
起26は半球状の形状を有し、各接続部材28は円柱状
の形状を有する。各第1の突起24は、頂面30に開放
する凹所32を有する。
Each first protrusion 24 has a truncated hemispherical shape having a top surface 30 substantially parallel to the substrate 20, each second protrusion 26 has a hemispherical shape, and each connecting member 28 Has a columnar shape. Each first projection 24 has a recess 32 that opens into the top surface 30.

【0020】各凹所32は、頂面30から所定の深さ位
置までの間ほぼ同じ横断面積及び横断面形状を有する。
このような凹所32は、頂面30の側からのドリル加工
により形成することができる。図示の例では、各凹所3
2は、円形の横断面形状を有するが、多角形の横断面形
状を有していてもよい。なお、横断面とは、突起24の
軸線34に対して直角の面をいう。
Each recess 32 has substantially the same cross-sectional area and cross-sectional shape from the top surface 30 to a predetermined depth position.
Such a recess 32 can be formed by drilling from the side of the top surface 30. In the example shown, each recess 3
2 has a circular cross-sectional shape, but may have a polygonal cross-sectional shape. Note that the cross section refers to a plane perpendicular to the axis 34 of the projection 24.

【0021】通電試験時、補助装置10及びICチップ
12は、それらの一方が他方の上側となるように配置さ
れた状態で、相寄る方向へ相対的に変位されることによ
り、各突起24とバンプ電極16とを押圧される。この
とき、半田製の各バンプ電極16は、その基部がデバイ
ス本体14の側に押し潰され、その頂部が突起24の凹
所32に食い込むように、変形される。
At the time of the power-on test, the auxiliary device 10 and the IC chip 12 are relatively displaced in the mutually approaching direction in a state where one of them is disposed above the other, so that The bump electrode 16 is pressed. At this time, each bump electrode 16 made of solder is deformed such that its base is crushed toward the device body 14 and its top bites into the recess 32 of the projection 24.

【0022】これにより、バンプ電極16の基部がデバ
イス本体14の側に押し潰されるように変形するととも
に、バンプ電極16の基部と頂部との境界付近に段部が
形成される。これらの変形は、バンプ電極16の基部を
膨出させるが、バンプ電極16の高さ寸法及び頂部の形
状に影響を与えることはない。
As a result, the base of the bump electrode 16 is deformed so as to be crushed toward the device body 14, and a step is formed near the boundary between the base and the top of the bump electrode 16. These deformations cause the base of the bump electrode 16 to bulge, but do not affect the height dimension and the shape of the top of the bump electrode 16.

【0023】各凹所32の横断面積及び横断面形状が所
定の深さ位置までほぼ同じであると、バンプ電極16の
頂部が凹所32内に食い込んでも、バンプ電極16の頂
部を軸線34の側に押し潰すように変形させる力はバン
プ電極16に作用しない。このため、補助装置10は、
バンプ電極16と突起24とが押圧されても、バンプ電
極16の高さ寸法及び頂部の形状を変化させない。これ
は、横断面積が多少異なっていても、同じである。
If the cross-sectional area and cross-sectional shape of each recess 32 are substantially the same up to a predetermined depth position, even if the top of the bump electrode 16 bites into the recess 32, the top of the bump electrode 16 is The force for squeezing to the side does not act on the bump electrode 16. For this reason, the auxiliary device 10
Even if the bump electrode 16 and the projection 24 are pressed, the height dimension and the shape of the top of the bump electrode 16 are not changed. This is true even if the cross-sectional area is slightly different.

【0024】補助装置10は、たとえば、先ず、剛性樹
脂製の基板20に複数のスルーホール22を検査すべき
ICチップ12のバンプ電極16と同じパターンに形成
し、次いで、第1及び第2の突起24及び26並びに部
材28を気相生長法のような適宜な手法で各スルーホー
ル22に形成し、次いで各第1の突起24の頂部を基板
20とほぼ平行に切除して頂面30を形成し、その後各
突起24に頂面30の側からドリル加工を施して凹所3
2を形成することにより、製作することができる。従っ
て、補助装置を容易に製作することができる。
The auxiliary device 10, for example, first forms a plurality of through holes 22 in a rigid resin substrate 20 in the same pattern as the bump electrodes 16 of the IC chip 12 to be inspected. The protrusions 24 and 26 and the member 28 are formed in each through hole 22 by an appropriate method such as a vapor phase growth method, and then the top of each first protrusion 24 is cut out substantially parallel to the substrate 20 to form the top surface 30. After that, each projection 24 is drilled from the side of the top surface 30 to form the recess 3.
2 can be manufactured. Therefore, the auxiliary device can be easily manufactured.

【0025】上記の補助装置10は、複数の突起24を
有するから、突起タイプのプローブカードとして用いる
ことができる。このため、本発明の補助装置は、回路基
板に直接実装されるICチップの通電試験用補助装置の
みならず、他の集積回路、液晶表示パネル等、他の平板
状被検査対の通電試験用補助装置にも適用することがで
きる。
Since the auxiliary device 10 has a plurality of projections 24, it can be used as a projection type probe card. For this reason, the auxiliary device of the present invention is not only an auxiliary device for conducting a current test of an IC chip directly mounted on a circuit board, but also for conducting a current test of another flat inspected pair such as another integrated circuit or a liquid crystal display panel. It can also be applied to auxiliary devices.

【0026】本発明は、上記実施例に限定されない。た
とえば、各第1の突起24の形状を截頭半球状とする代
わりに、板状としてもよい。また、スルーホール22及
び第2の突起26を設けなくてもよい。さらに、基板2
0に複数の配線部を形成し、各配線部に第1の突起24
を形成してもよい。
The present invention is not limited to the above embodiment. For example, the shape of each first projection 24 may be plate-shaped instead of being truncated hemisphere. Further, the through hole 22 and the second protrusion 26 may not be provided. Further, the substrate 2
0, a plurality of wiring portions are formed, and each of the wiring portions has a first protrusion 24.
May be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の補助装置と試験すべきICチップとの
一実施例を示す断面図である。
FIG. 1 is a sectional view showing one embodiment of an auxiliary device of the present invention and an IC chip to be tested.

【図2】第1の突起の近傍及びバンプ電極の近傍の拡大
断面図である。
FIG. 2 is an enlarged cross-sectional view near a first protrusion and near a bump electrode.

【図3】第1の突起の平面図である。FIG. 3 is a plan view of a first protrusion.

【符号の説明】[Explanation of symbols]

10 補助装置 12 ICチップ 16 バンプ電極 20 基板 22 スルーホール 24 第1の突起 26 第2の突起 30 突起の頂面 32 突起の凹所 DESCRIPTION OF SYMBOLS 10 Auxiliary device 12 IC chip 16 Bump electrode 20 Substrate 22 Through-hole 24 First projection 26 Second projection 30 Top surface of projection 32 Depression of projection

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 電気絶縁性の基板と、該基板の一方の面
に間隔をおいて形成された導電性の複数の突起とを含
み、各突起は、前記基板とほぼ平行の頂面を有するとと
もに、前記頂面に開放する凹所を有し、各凹所は前記頂
面から所定の深さ位置までほぼ同じ断面積を有する、平
板状被検査体試験用補助装置。
1. An electronic device comprising: an electrically insulating substrate; and a plurality of conductive protrusions formed on one surface of the substrate at intervals, each protrusion having a top surface substantially parallel to the substrate. In addition, an auxiliary device for testing a flat object to be inspected has concave portions opened to the top surface, and each concave portion has substantially the same cross-sectional area from the top surface to a predetermined depth position.
【請求項2】 さらに、前記基板を厚さ方向へ貫通する
導電性の複数のスルーホールを含み、各スルーホールは
少なくとも一端において前記突起により閉塞されてい
る、請求項1に記載の補助装置。
2. The auxiliary device according to claim 1, further comprising a plurality of conductive through holes penetrating the substrate in a thickness direction, wherein each of the through holes is closed at least at one end by the protrusion.
【請求項3】 さらに、前記基板の他方の面に形成され
て各スルーホールをを少なくとも他端において閉塞する
半球状の第2の突起を含む、請求項2に記載の補助装
置。
3. The auxiliary device according to claim 2, further comprising a hemispherical second protrusion formed on the other surface of the substrate and closing each through hole at at least the other end.
【請求項4】 導電性の複数の突起を電気絶縁性の基板
の一方の面に間隔をおいて形成し、各突起の頂部を前記
基板とほぼ平行に除去し、各突起の頂面に開放しかつ前
記頂面から所定の深さ位置までほぼ同じ断面積を有する
凹所を各突起に形成することを含む、平板状被検査体試
験用補助装置の製造方法。
4. A plurality of conductive protrusions are formed at intervals on one surface of an electrically insulating substrate, the tops of the protrusions are removed substantially parallel to the substrate, and open to the top surfaces of the protrusions. And forming a recess having substantially the same cross-sectional area in each projection from the top surface to a predetermined depth position.
【請求項5】 さらに、前記突起を形成する前に、前記
基板を厚さ方向へ貫通する導電性の複数のスルーホール
を前記基板に形成することを含み、前記突起は前記スル
ーホールを少なくとも一端において閉塞するように形成
される、請求項4に記載の製造方法
5. The method according to claim 1, further comprising: forming a plurality of conductive through-holes through the substrate in a thickness direction of the substrate before forming the protrusion, wherein the protrusion has at least one end formed with the through-hole. The manufacturing method according to claim 4, which is formed so as to be closed in the step (c).
【請求項6】 さらに、各スルーホールを少なくとも他
端において閉塞する半球状の第2の突起を前記基板の他
方の面に形成することを含む、請求項5に記載の製造方
法。
6. The manufacturing method according to claim 5, further comprising forming, on the other surface of the substrate, a hemispherical second projection that closes each through hole at least at the other end.
JP9325183A 1997-11-12 1997-11-12 Auxiliary device for testing flat plate-like inspected body and its manufacture Pending JPH11142474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9325183A JPH11142474A (en) 1997-11-12 1997-11-12 Auxiliary device for testing flat plate-like inspected body and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9325183A JPH11142474A (en) 1997-11-12 1997-11-12 Auxiliary device for testing flat plate-like inspected body and its manufacture

Publications (1)

Publication Number Publication Date
JPH11142474A true JPH11142474A (en) 1999-05-28

Family

ID=18173942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9325183A Pending JPH11142474A (en) 1997-11-12 1997-11-12 Auxiliary device for testing flat plate-like inspected body and its manufacture

Country Status (1)

Country Link
JP (1) JPH11142474A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020025024A (en) * 2000-09-27 2002-04-03 나까무라 쇼오 Printed circuit board and method of manufac turing the same
KR101974931B1 (en) * 2018-05-03 2019-05-03 주식회사 티에프이 Test socket module for semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020025024A (en) * 2000-09-27 2002-04-03 나까무라 쇼오 Printed circuit board and method of manufac turing the same
KR101974931B1 (en) * 2018-05-03 2019-05-03 주식회사 티에프이 Test socket module for semiconductor package

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