JPH11135483A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11135483A JPH11135483A JP29823097A JP29823097A JPH11135483A JP H11135483 A JPH11135483 A JP H11135483A JP 29823097 A JP29823097 A JP 29823097A JP 29823097 A JP29823097 A JP 29823097A JP H11135483 A JPH11135483 A JP H11135483A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- power supply
- reaction chamber
- force
- provided outside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プラズマを用いた
半導体装置の製造装置に関するものである。The present invention relates to an apparatus for manufacturing a semiconductor device using plasma.
【０００２】[0002]
【従来の技術】半導体装置の微細化、高集積化が進んで
おり、ドライエッチングでは、半導体基板の温度制御が
加工精度に大きく影響する。従来は、この半導体基板を
支持する方法として平板の上への設置や、半導体基板の
周辺部を機械的におさえる方法（クランプ方式）が用い
られてきた。2. Description of the Related Art As semiconductor devices are becoming finer and more highly integrated, temperature control of a semiconductor substrate greatly affects processing accuracy in dry etching. Conventionally, as a method of supporting the semiconductor substrate, a method of mounting the semiconductor substrate on a flat plate and a method of mechanically holding a peripheral portion of the semiconductor substrate (clamp method) have been used.
【０００３】近年、より確実に半導体基板を支持、固定
する方法として、半導体基板を支持する板と半導体基板
間に電界を作用させることによって静電力を生じさせ、
半導体基板を吸着させる静電チャック（ESC）方式が用
いられるようになってきた。静電チャックは、その装置
部に片側の電極のみが設置され、半導体基板が対向電極
となる単極型と、半導体基板支持装置部に両極の電極を
設置している双極型に分けられる。以下、単極型静電チ
ャック方式を用いた半導体装置の製造装置の一例につい
て説明する。図７はドライエッチング装置の場合の従来
の半導体装置の製造装置の略図である。１は上部電極、
２は下部電極、３は表面絶縁層、４は半導体基板、５は
反応室、６は高周波電源、７は直流電源、８はブロッキ
ングコンデンサ、９はHeガス配管である。ドライエッチ
ング装置では、接地した上部電極１と下部電極２との間
に高周波電源６によって高周波電力を印加してプラズマ
を発生させ、下部電極部に設置された半導体基板４に所
望の加工を施す。ドライエッチング装置の場合の半導体
基板支持装置は、下部電極２と表面絶縁層３で構成され
る。さらに、下部電極２を直流電源７によって一定の直
流電圧を印加することで、静電吸着力を発生させ、半導
体基板４を固定している。また、ガス配管９を通して、
半導体基板４と半導体基板支持装置の間にHeガスを導入
することにより、半導体基板４の温度制御性を高めてい
る。In recent years, as a method of more securely supporting and fixing a semiconductor substrate, an electrostatic force is generated by applying an electric field between a plate supporting the semiconductor substrate and the semiconductor substrate.
An electrostatic chuck (ESC) method for adsorbing a semiconductor substrate has been used. Electrostatic chucks are classified into a monopolar type in which only one electrode is provided in a device portion thereof and a semiconductor substrate as a counter electrode, and a bipolar type in which bipolar electrodes are provided in a semiconductor substrate supporting device portion. Hereinafter, an example of an apparatus for manufacturing a semiconductor device using a single-pole electrostatic chuck method will be described. FIG. 7 is a schematic view of a conventional semiconductor device manufacturing apparatus in the case of a dry etching apparatus. 1 is the upper electrode,
Reference numeral 2 denotes a lower electrode, 3 denotes a surface insulating layer, 4 denotes a semiconductor substrate, 5 denotes a reaction chamber, 6 denotes a high-frequency power supply, 7 denotes a DC power supply, 8 denotes a blocking capacitor, and 9 denotes a He gas pipe. In the dry etching apparatus, high-frequency power is applied between the grounded upper electrode 1 and lower electrode 2 by a high-frequency power supply 6 to generate plasma, and a desired processing is performed on the semiconductor substrate 4 provided on the lower electrode portion. In the case of a dry etching apparatus, the semiconductor substrate supporting apparatus includes a lower electrode 2 and a surface insulating layer 3. Further, a constant DC voltage is applied to the lower electrode 2 by a DC power supply 7 to generate an electrostatic attraction force, thereby fixing the semiconductor substrate 4. Also, through the gas pipe 9,
By introducing He gas between the semiconductor substrate 4 and the semiconductor substrate supporting device, the temperature controllability of the semiconductor substrate 4 is improved.
【０００４】また、半導体装置の製造工程のうち、反応
性イオンエッチングを行う工程では、能動的に電界を作
用させなくても、自己バイアス（セルフバイアス）によ
って電界が発生し、半導体基板がその支持台に吸着す
る。In the process of manufacturing a semiconductor device, in the step of performing reactive ion etching, an electric field is generated by a self-bias (self-bias) without actively applying an electric field, and the semiconductor substrate is supported by the self-bias. Adsorb to the table.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置の製造装置では、静電吸着力を得るため
の直流電源７の出力設定値が一定であるため、工程処理
中に発生する電界の影響で吸着力が変動しやすく、処理
中に発生する電界が直流電源７による電界を相殺する場
合は、吸着力が低下し、半導体基板が跳ね上がったり、
充分な温度制御が不可能になる。また、処理中に発生す
る電界が直流電源７による電界と同方向の場合は、処理
が終了しても大きな残留吸着力が残り、半導体基板を搬
送するのに時間を要したり、残留吸着力以上の力を加え
て半導体基板をはがすことによって半導体基板が跳ね上
がり、半導体装置の製造装置に故障を生じさせるという
問題があった。However, in the above-described conventional semiconductor device manufacturing apparatus, since the output set value of the DC power supply 7 for obtaining the electrostatic attraction force is constant, the electric field generated during the process processing is reduced. If the electric force generated during processing offsets the electric field generated by the DC power supply 7 due to the influence of the adsorption force, the adsorption force decreases, the semiconductor substrate jumps,
Sufficient temperature control becomes impossible. If the electric field generated during the processing is in the same direction as the electric field generated by the DC power supply 7, a large residual adsorption force remains even after the processing is completed, and it takes time to transport the semiconductor substrate, When the semiconductor substrate is peeled off by applying the above-mentioned force, the semiconductor substrate jumps up, causing a problem that a failure occurs in a semiconductor device manufacturing apparatus.
【０００６】また、半導体基板の裏面の状態が一定では
ないため、多数の半導体基板を処理する際に、その裏面
の状態によっても、上記記載の異常が発生し、安定して
半導体装置を製造することができないという問題があっ
た。特に、プラズマ放電開始、終了時や、プラズマエッ
チングでオーバーエッチングステップに入る時などは、
プラズマによる電界が変動しやすく、工程処理中に異常
が発生するという問題があった。Further, since the state of the back surface of the semiconductor substrate is not constant, the abnormalities described above occur depending on the state of the back surface when processing a large number of semiconductor substrates, and a semiconductor device can be manufactured stably. There was a problem that it was not possible. In particular, at the start and end of plasma discharge, and when entering the over-etching step by plasma etching,
There has been a problem that the electric field due to the plasma tends to fluctuate, and abnormalities occur during the process.
【０００７】この発明の目的は、プラズマを用いた半導
体装置の製造装置において、静電力によって半導体基板
を固定する際、所望の処理中は安定した吸着力を発生さ
せ、処理終了後は、速やかに半導体基板を搬送する機能
を有した半導体装置の製造装置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing apparatus using plasma, in which when a semiconductor substrate is fixed by electrostatic force, a stable adsorption force is generated during a desired process, and immediately after the process is completed. An object of the present invention is to provide an apparatus for manufacturing a semiconductor device having a function of transporting a semiconductor substrate.
【０００８】[0008]
【課題を解決するための手段】この目的を達成するため
に、請求項１記載の半導体装置の製造装置は、反応室内
に設けた半導体基板を支持する台と、反応室外に設けた
交流電源、前記支持台に接続した直流電源、および直流
電源制御装置を備え、かつ反応室内に直流電圧測定装置
を備えることで、この測定装置の直流電圧測定値を前記
反応室外に設けた直流電源制御装置にフィードバックす
る特徴を有している。In order to achieve the above object, a semiconductor device manufacturing apparatus according to claim 1 comprises a base for supporting a semiconductor substrate provided in a reaction chamber, an AC power supply provided outside the reaction chamber, A DC power supply connected to the support, and a DC power supply control device, and by providing a DC voltage measurement device in the reaction chamber, the DC voltage measurement value of this measurement device to the DC power supply control device provided outside the reaction chamber It has the feature of feedback.
【０００９】請求項２記載の半導体装置の製造装置は、
反応室内に設けた半導体基板を支持する台と、反応室外
に設けた交流電源、前記支持台に接続した直流電源、お
よび直流電源制御装置を備え、かつ交流電圧測定装置を
備えることで、この測定装置の交流電圧測定値を前記反
応室外に設けた直流電源制御装置にフィードバックする
特徴を有している。According to a second aspect of the present invention, there is provided an apparatus for manufacturing a semiconductor device.
A base for supporting a semiconductor substrate provided in the reaction chamber, an AC power supply provided outside the reaction chamber, a DC power supply connected to the support base, and a DC power supply control device, and by providing an AC voltage measurement device, It is characterized in that the measured value of the AC voltage of the device is fed back to a DC power supply control device provided outside the reaction chamber.
【００１０】請求項３記載の半導体装置の製造装置は、
反応室内に設けた半導体基板を支持する台と、反応室外
に設けた交流電源、前記支持台に接続した直流電源、お
よび直流電源制御装置を備え、かつ直流電流測定装置を
備えることで、この測定装置の直流電流測定値を前記反
応室外に設けた直流電源制御装置にフィードバックする
特徴を有している。According to a third aspect of the present invention, there is provided an apparatus for manufacturing a semiconductor device.
A base for supporting the semiconductor substrate provided in the reaction chamber, an AC power supply provided outside the reaction chamber, a DC power supply connected to the support base, and a DC power supply control device, and by providing a DC current measurement device, It is characterized in that the measured value of the direct current of the device is fed back to a direct current power supply control device provided outside the reaction chamber.
【００１１】直流電源を用いて静電吸着力によって半導
体基板を支持台に固定する場合、その吸着力は、半導体
基板とその支持台間の電位差に依存する。この電位差
は、直流電源によって支持台に印加される電位と、プラ
ズマ放電によって生じる自己バイアスによる電位との和
となる。ここで、自己バイアスによる電位は処理条件や
処理中の雰囲気で変動する。また、半導体基板とその支
持台間の電位差は、半導体基板の裏面の状態や、半導体
基板と支持台との接触方法によっても変化する。[0011] When a semiconductor substrate is fixed to a support by electrostatic attraction using a DC power supply, the attraction depends on the potential difference between the semiconductor substrate and the support. This potential difference is the sum of the potential applied to the support base by the DC power supply and the potential due to self-bias generated by the plasma discharge. Here, the potential due to the self-bias varies depending on the processing conditions and the atmosphere during the processing. In addition, the potential difference between the semiconductor substrate and the supporting base changes depending on the state of the back surface of the semiconductor substrate and the method of contact between the semiconductor substrate and the supporting base.
【００１２】本発明の構成によれば、直接測定すること
が困難な半導体基板とその支持台間の電位差に代わり、
この電位差と相関がある値を測定し、その値をフィード
バックし、処理中に必要な吸着力が得られる電位差を確
保できるように直流電源の出力を制御することができる
ため、所望の処理中に安定した吸着力を得ることができ
る。また、処理終了後は、この電位差が０になるように
直流電源の出力を制御することによって、残留吸着力な
く、速やかに半導体基板を搬送することができる。According to the structure of the present invention, instead of the potential difference between the semiconductor substrate which is difficult to measure directly and the support thereof,
A value correlated with this potential difference is measured, the value is fed back, and the output of the DC power supply can be controlled so as to secure a potential difference at which a necessary attraction force is obtained during the process. Stable adsorption power can be obtained. Further, after the processing is completed, the output of the DC power supply is controlled so that the potential difference becomes 0, whereby the semiconductor substrate can be transferred quickly without residual suction power.
【００１３】[0013]
【発明の実施の形態】以下、この発明の実施の形態につ
いて、図面を参照しながら説明する。なお、以下の説明
では、半導体装置の製造装置としてドライエッチング装
置を用いる。Embodiments of the present invention will be described below with reference to the drawings. In the following description, a dry etching apparatus is used as a semiconductor device manufacturing apparatus.
【００１４】図１は、本発明の一実施の形態におけるド
ライエッチング装置の略図である。１は上部電極、２は
下部電極、３は表面絶縁層、４は半導体基板、５は反応
室、６は高周波電源、７は直流電源、８はブロッキング
コンデンサ、９はガス配管、１０は制御装置、１１は信
号線、１２は電圧測定用端子、１３は直流電圧計であ
る。FIG. 1 is a schematic diagram of a dry etching apparatus according to an embodiment of the present invention. 1 is an upper electrode, 2 is a lower electrode, 3 is a surface insulating layer, 4 is a semiconductor substrate, 5 is a reaction chamber, 6 is a high-frequency power supply, 7 is a DC power supply, 8 is a blocking capacitor, 9 is a gas pipe, and 10 is a control device. , 11 are signal lines, 12 is a voltage measuring terminal, and 13 is a DC voltmeter.
【００１５】半導体基板４を図１のように半導体基板支
持装置上に設置する。その後、所望のドライエッチング
処理を行うために、エッチングガスを反応室５内に導入
し所定の圧力、流量に調節し、高周波電源６によって高
周波電力を印加し、プラズマ放電させる。本実施の形態
では、圧力：5Pa、高周波電力：1000W、導入ガス：CHF3
=50cc、CF4=10ccの条件で、シリコン酸化膜をエッチン
グする。この状態で、半導体基板４上および、電圧測定
用端子１２にプラズマシースが形成され、自己バイアス
が生じる。静電吸着力が発生した後、ガス配管９から冷
却ガスを半導体基板支持装置と半導体基板４の間に導入
する。本実施の形態では、Heガスを2KPaの圧力で導入す
る。吸着力は、プラズマ放電によって発生する自己バイ
アスおよび直流電源７による電界からのクーロン力と、
半導体基板４の裏面を冷却するためのガス圧力の和で決
定される。直流電源７の出力値および、裏面冷却用ガス
圧力は処理条件として一定の値に設定されるが、自己バ
イアスによるクーロン力はプラズマの状態によって変動
する。The semiconductor substrate 4 is set on a semiconductor substrate supporting device as shown in FIG. Thereafter, in order to perform a desired dry etching treatment, an etching gas is introduced into the reaction chamber 5 and adjusted to a predetermined pressure and flow rate, high-frequency power is applied by a high-frequency power supply 6, and plasma discharge is performed. In this embodiment, the pressure is 5 Pa, the high frequency power is 1000 W, and the introduced gas is CHF 3
The silicon oxide film is etched under the conditions of = 50 cc and CF 4 = 10 cc. In this state, a plasma sheath is formed on the semiconductor substrate 4 and the voltage measurement terminal 12, and a self-bias is generated. After the electrostatic attraction force is generated, a cooling gas is introduced from the gas pipe 9 between the semiconductor substrate support device and the semiconductor substrate 4. In the present embodiment, He gas is introduced at a pressure of 2 KPa. The attraction force is based on the self-bias generated by the plasma discharge and the Coulomb force from the electric field generated by the DC power supply 7,
It is determined by the sum of the gas pressures for cooling the back surface of the semiconductor substrate 4. The output value of the DC power supply 7 and the pressure of the backside cooling gas are set to constant values as processing conditions, but the Coulomb force due to self-bias varies depending on the state of the plasma.
【００１６】図２は、各裏面冷却ガス圧力値で測定され
たVdcに対するウェハ吸着力が０になる直流電源７の出
力値をプロットしたものである。図２から、冷却ガス圧
力を設定すれば、測定されたVdcに対する吸着力が０と
なる直流電源７の出力値がわかる。そこで、測定された
Vdcに対して、吸着力が０とならないように常に直流電
源７の出力値を制御する。このように直流電源７を制御
することによって、安定かつ十分な吸着力が得られる。
また、必要以上に直流電源７によって電圧を印加すると
過剰な残留吸着力が残ったり、チャージアップ現象によ
るゲート酸化膜破壊を発生することがあるが、必要最低
限の直流電源７の出力値に制御することが可能であるこ
とから、これらの問題も防げるという利点もある。FIG. 2 is a plot of the output value of the DC power supply 7 at which the wafer suction force becomes zero with respect to Vdc measured at each backside cooling gas pressure value. From FIG. 2, if the cooling gas pressure is set, the output value of the DC power supply 7 at which the measured adsorption power to Vdc becomes 0 can be found. So it was measured
The output value of the DC power supply 7 is always controlled so that the attraction force does not become 0 with respect to Vdc. By controlling the DC power supply 7 in this manner, a stable and sufficient suction force can be obtained.
If a voltage is applied by the DC power supply 7 more than necessary, an excessive residual adsorption force may remain or a gate oxide film may be broken due to a charge-up phenomenon. This has the advantage that these problems can also be prevented.
【００１７】また同様に図２から、冷却ガス圧力０KPa
のときのVdcと吸着力が０となる直流電源７の出力値が
わかる。そこで、処理終了直前に、吸着力が０となるよ
うに直流電源７を制御することで、処理終了時に残留吸
着力を無くすことができる。FIG. 2 also shows that the cooling gas pressure is 0 KPa
In this case, Vdc and the output value of the DC power supply 7 at which the attraction force becomes 0 can be found. Therefore, by controlling the DC power supply 7 such that the suction force becomes 0 immediately before the end of the process, the residual suction force can be eliminated at the end of the process.
【００１８】図３は、本発明の第２の実施の形態におけ
るドライエッチング装置の略図である。１は上部電極、
２は下部電極、３は表面絶縁層、４は半導体基板、５は
反応室、６は高周波電源、７は直流電源、８はブロッキ
ングコンデンサ、９はガス配管、１０は制御装置、１１
は信号線、１４は交流電圧ピーク値測定装置である。FIG. 3 is a schematic view of a dry etching apparatus according to a second embodiment of the present invention. 1 is the upper electrode,
2 is a lower electrode, 3 is a surface insulating layer, 4 is a semiconductor substrate, 5 is a reaction chamber, 6 is a high frequency power supply, 7 is a DC power supply, 8 is a blocking capacitor, 9 is a gas pipe, 10 is a control device, 11
Is a signal line, and 14 is an AC voltage peak value measuring device.
【００１９】半導体基板４を図３のように半導体基板支
持装置上に設置する。その後、所望のドライエッチング
処理を行うために、エッチングガスを反応室５内に導入
し所定の圧力、流量に調節し、高周波電源６によって高
周波電力を印加し、プラズマ放電させる。次に、圧力：
5Pa、高周波電力：1000W、導入ガス：CHF3=50cc、CF4=1
0ccの条件で、シリコン酸化膜をエッチングする。静電
吸着力が発生した後、ガス配管９から冷却ガスを半導体
基板支持装置と半導体基板４の間に導入する。本実施の
形態では、Heガスを2KPaの圧力で導入する。The semiconductor substrate 4 is set on a semiconductor substrate supporting device as shown in FIG. Thereafter, in order to perform a desired dry etching treatment, an etching gas is introduced into the reaction chamber 5 and adjusted to a predetermined pressure and flow rate, high-frequency power is applied by a high-frequency power supply 6, and plasma discharge is performed. Then the pressure:
5Pa, high frequency power: 1000W, introduced gas: CHF 3 = 50cc, CF 4 = 1
The silicon oxide film is etched under the condition of 0 cc. After the electrostatic attraction force is generated, a cooling gas is introduced from the gas pipe 9 between the semiconductor substrate support device and the semiconductor substrate 4. In the present embodiment, He gas is introduced at a pressure of 2 KPa.
【００２０】図４は、各裏面冷却ガス圧力値で測定され
たVppに対するウェハ吸着力が０になる直流電源７の出
力値をプロットしたものである。図４から、冷却ガス圧
力を設定すれば、測定されたVppに対する吸着力が０と
なる直流電源７の出力値がわかる。そこで、測定された
Vppに対して、吸着力が０とならないように常に直流電
源７の出力値を制御する。このように直流電源７を制御
することによって、安定かつ十分な吸着力が得られる。
また、必要以上に直流電源７によって電圧を印加すると
過剰な残留吸着力が残ったり、チャージアップ現象によ
るゲート酸化膜破壊を発生することがあるが、本実施の
形態によると、必要最低限の直流電源７の出力値に制御
することが可能であることから、これらの問題も防げる
という利点もある。FIG. 4 is a plot of the output value of the DC power supply 7 at which the wafer attraction force becomes zero with respect to Vpp measured at each backside cooling gas pressure value. From FIG. 4, if the cooling gas pressure is set, the output value of the DC power supply 7 at which the measured adsorption power to Vpp becomes 0 can be found. So it was measured
The output value of the DC power supply 7 is always controlled so that the attraction force does not become 0 with respect to Vpp. By controlling the DC power supply 7 in this manner, a stable and sufficient suction force can be obtained.
Also, if a voltage is applied by the DC power supply 7 more than necessary, an excessive residual attraction force may remain or a gate oxide film may be broken due to a charge-up phenomenon. Since the output value of the power supply 7 can be controlled, there is an advantage that these problems can be prevented.
【００２１】また同様に図４から、冷却ガス圧力０KPa
のときのVppと吸着力が０となる直流電源７の出力値が
わかる。そこで、処理終了直前に、吸着力が０となるよ
うに直流電源７を制御することで、処理終了時に残留吸
着力を無くすことができる。Similarly, FIG. 4 shows that the cooling gas pressure is 0 KPa
In this case, the output value of the DC power supply 7 at which Vpp and the attraction force become 0 can be found. Therefore, by controlling the DC power supply 7 such that the suction force becomes 0 immediately before the end of the process, the residual suction force can be eliminated at the end of the process.
【００２２】また、反応室５内に測定用の端子をいれる
必要が無いという利点がある。図５は、本発明の第３の
実施の形態におけるドライエッチング装置の略図であ
る。１は上部電極、２は下部電極、３は表面絶縁層、４
は半導体基板、５は反応室、６は高周波電源、７は直流
電源、８はブロッキングコンデンサ、９はガス配管、１
０は制御装置、１１は信号線、１５は直流電流計であ
る。Another advantage is that there is no need to insert a measurement terminal into the reaction chamber 5. FIG. 5 is a schematic diagram of a dry etching apparatus according to the third embodiment of the present invention. 1 is an upper electrode, 2 is a lower electrode, 3 is a surface insulating layer, 4
Is a semiconductor substrate, 5 is a reaction chamber, 6 is a high frequency power supply, 7 is a DC power supply, 8 is a blocking capacitor, 9 is a gas pipe, 1
0 is a control device, 11 is a signal line, and 15 is a DC ammeter.
【００２３】半導体基板４を図５のように半導体基板支
持装置上に設置する。その後、所望のドライエッチング
処理を行うために、エッチングガスを反応室５内に導入
し所定の圧力、流量に調節し、高周波電源６によって高
周波電力を印加し、プラズマ放電させる。本実施の形態
では、圧力：5Pa、高周波電力：1000W、導入ガス：CHF3
=50cc、CF4=10ccの条件で、シリコン酸化膜をエッチン
グする。静電吸着力が発生した後、ガス配管９から冷却
ガスを半導体基板支持装置と半導体基板４の間に導入す
る。本実施の形態では、Heガスを2KPaの圧力で導入す
る。図６は、本実施の形態における各裏面冷却ガス圧力
値で測定されたIdcに対するウェハ吸着力が０になる直
流電源７の出力値をプロットしたものである。図６か
ら、冷却ガス圧力を設定すれば、測定されたIdcに対す
る吸着力が０となる直流電源７の出力値がわかる。そこ
で、測定されたIdcに対して、吸着力が０とならないよ
うに、常に直流電源７の出力値を制御する。このように
直流電源７を制御することによって、安定かつ十分な吸
着力が得られる。また、必要以上に直流電源７によって
電圧を印加すると過剰な残留吸着力が残ったり、チャー
ジアップ現象によるゲート酸化膜破壊を発生することが
あるが、本実施の形態によると、必要最低限の直流電源
７の出力値に制御することが可能であることから、これ
らの問題も防げるという利点もある。The semiconductor substrate 4 is set on a semiconductor substrate supporting device as shown in FIG. Thereafter, in order to perform a desired dry etching treatment, an etching gas is introduced into the reaction chamber 5 and adjusted to a predetermined pressure and flow rate, high-frequency power is applied by a high-frequency power supply 6, and plasma discharge is performed. In this embodiment, the pressure is 5 Pa, the high frequency power is 1000 W, and the introduced gas is CHF 3
The silicon oxide film is etched under the conditions of = 50 cc and CF 4 = 10 cc. After the electrostatic attraction force is generated, a cooling gas is introduced from the gas pipe 9 between the semiconductor substrate support device and the semiconductor substrate 4. In the present embodiment, He gas is introduced at a pressure of 2 KPa. FIG. 6 is a graph in which the output value of the DC power supply 7 at which the wafer attraction force is 0 with respect to Idc measured at each back surface cooling gas pressure value in the present embodiment. From FIG. 6, if the cooling gas pressure is set, the output value of the DC power supply 7 at which the measured adsorption power to Idc becomes 0 can be found. Therefore, the output value of the DC power supply 7 is always controlled so that the suction force does not become 0 with respect to the measured Idc. By controlling the DC power supply 7 in this manner, a stable and sufficient suction force can be obtained. If a voltage is applied by the DC power supply 7 more than necessary, an excessive residual attraction force may remain or a gate oxide film may be destroyed due to a charge-up phenomenon. Since the output value of the power supply 7 can be controlled, there is an advantage that these problems can be prevented.
【００２４】また同様に図６から、冷却ガス圧力０KPa
のときのIdcと吸着力が０となる直流電源７の出力値が
わかる。そこで、処理終了直前に、吸着力が０となるよ
うに直流電源７を制御することで、処理終了時に残留吸
着力を無くすことができる。FIG. 6 also shows that the cooling gas pressure is 0 KPa
In this case, the output value of the DC power supply 7 at which the Idc and the attraction force become 0 is known. Therefore, by controlling the DC power supply 7 such that the suction force becomes 0 immediately before the end of the process, the residual suction force can be eliminated at the end of the process.
【００２５】また、半導体基板支持方式として、単極型
静電チャック方式の半導体基板支持装置を用いるが、双
極型静電チャック方式の半導体基板支持装置にも、同様
な効果が得られることは言うまでもない。Although a semiconductor substrate supporting device of a monopolar electrostatic chuck type is used as a semiconductor substrate supporting system, it goes without saying that a similar effect can be obtained with a semiconductor substrate supporting device of a bipolar electrostatic chuck type. No.
【００２６】[0026]
【発明の効果】この発明によれば、反応室内に設けた半
導体基板を支持する台と、反応室外に設けた交流電源、
前記支持台に接続した直流電源、および直流電源制御装
置を備え、かつ半導体基板と半導体基板を支持する台と
の間の電位差と相関のある電気特性を測定する装置を備
え、この測定装置の測定値を前記反応室外に設けた直流
電源制御装置にフィードバックする機構を備えることに
よって、所望の処理中は、半導体基板に安定かつ十分な
吸着力を発生し、処理終了後も少ない残留吸着力で速や
かに搬送することができる優れた半導体装置の製造装置
を実現するものである。According to the present invention, a base for supporting a semiconductor substrate provided in a reaction chamber, an AC power supply provided outside the reaction chamber,
A DC power supply connected to the support base, and a DC power supply control device, and a device for measuring an electrical characteristic that is correlated with a potential difference between the semiconductor substrate and the support for supporting the semiconductor substrate. By providing a mechanism for feeding back the value to a DC power supply control device provided outside the reaction chamber, a stable and sufficient adsorption force is generated on the semiconductor substrate during a desired process, and quickly with a small residual adsorption force even after the process is completed. The present invention realizes an excellent semiconductor device manufacturing apparatus that can be transported to a semiconductor device.
【図１】本発明の第１の実施の形態におけるドライエッ
チング装置に用いられた場合の半導体装置の製造装置の
略図FIG. 1 is a schematic diagram of a semiconductor device manufacturing apparatus when used in a dry etching apparatus according to a first embodiment of the present invention.
【図２】本発明の第１の実施の形態における各冷却ガス
圧力での、直流電圧測定値に対する吸着力が０となる直
流電源電圧のグラフFIG. 2 is a graph of a DC power supply voltage at which an adsorption force becomes 0 with respect to a DC voltage measurement value at each cooling gas pressure in the first embodiment of the present invention.
【図３】本発明の第２の実施の形態におけるドライエッ
チング装置に用いられた場合の半導体装置の製造装置の
略図FIG. 3 is a schematic diagram of a semiconductor device manufacturing apparatus when used in a dry etching apparatus according to a second embodiment of the present invention.
【図４】本発明の第２の実施の形態における各冷却ガス
圧力での、交流電圧測定値に対する吸着力が０となる直
流電源電圧のグラフFIG. 4 is a graph of a DC power supply voltage at which an attraction force becomes zero with respect to an AC voltage measurement value at each cooling gas pressure in the second embodiment of the present invention.
【図５】本発明の第３の実施の形態におけるドライエッ
チング装置に用いられた場合の半導体装置の製造装置の
略図FIG. 5 is a schematic view of a semiconductor device manufacturing apparatus when used in a dry etching apparatus according to a third embodiment of the present invention.
【図６】本発明の第３の実施の形態における各冷却ガス
圧力での、直流電流測定値に対する吸着力が０となる直
流電源電圧のグラフFIG. 6 is a graph of a DC power supply voltage at which an attraction force becomes zero with respect to a DC current measurement value at each cooling gas pressure in the third embodiment of the present invention.
【図７】従来技術におけるドライエッチング装置に用い
られた場合の半導体装置の製造装置の略図FIG. 7 is a schematic diagram of an apparatus for manufacturing a semiconductor device when used in a dry etching apparatus according to the related art.
１ 上部電極 ２ 下部電極 ３ 表面絶縁層 ４ 半導体基板 ５ 反応室 ６ 高周波電源 ７ 直流電源 ８ ブロッキングコンデンサ ９ ガス配管 １０ 制御装置 １１ 信号線 １２ 電圧測定用端子 １３ 直流電圧計 １４ 交流電圧ピーク値測定装置 １５ 直流電流計 DESCRIPTION OF SYMBOLS 1 Upper electrode 2 Lower electrode 3 Surface insulating layer 4 Semiconductor substrate 5 Reaction chamber 6 High frequency power supply 7 DC power supply 8 Blocking capacitor 9 Gas piping 10 Control device 11 Signal line 12 Voltage measurement terminal 13 DC voltmeter 14 AC voltage peak value measurement device 15 DC ammeter
Claims (3)
支持台と、反応室外に設けた交流電源と、前記支持台に
接続した直流電源と、直流電源制御装置と、反応室内に
直流電圧測定装置とを備え、直流電圧測定値を前記反応
室外に設けた直流電源制御装置にフィードバックするこ
とを特徴とする半導体装置の製造装置。1. A support table provided in a reaction chamber for supporting a semiconductor substrate, an AC power supply provided outside the reaction chamber, a DC power supply connected to the support table, a DC power supply control device, and a DC voltage measurement in the reaction chamber. And a device for feeding back the measured DC voltage value to a DC power supply control device provided outside the reaction chamber.
支持台と、反応室外に設けた交流電源と、前記支持台に
接続した直流電源と、直流電源制御装置と、交流電圧測
定装置とを備え、交流電圧測定値を前記反応室外に設け
た直流電源制御装置にフィードバックすることを特徴と
する半導体装置の製造装置。2. A support for supporting a semiconductor substrate provided in a reaction chamber, an AC power supply provided outside the reaction chamber, a DC power supply connected to the support, a DC power supply control device, and an AC voltage measurement device. An apparatus for producing a semiconductor device, wherein the measured value of the AC voltage is fed back to a DC power supply control device provided outside the reaction chamber.
支持台と、反応室外に設けた交流電源と、前記支持台に
接続した直流電源と、直流電源制御装置と、直流電流測
定装置とを備え、直流電流測定値を前記反応室外に設け
た直流電源制御装置にフィードバックすることを特徴と
する半導体装置の製造装置。3. A support for supporting a semiconductor substrate provided in a reaction chamber, an AC power supply provided outside the reaction chamber, a DC power supply connected to the support, a DC power supply control device, and a DC current measurement device. An apparatus for manufacturing a semiconductor device, wherein a measured value of a DC current is fed back to a DC power supply control device provided outside the reaction chamber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29823097A JP3792865B2 (en) | 1997-10-30 | 1997-10-30 | Semiconductor device manufacturing apparatus and dry etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29823097A JP3792865B2 (en) | 1997-10-30 | 1997-10-30 | Semiconductor device manufacturing apparatus and dry etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135483A true JPH11135483A (en) | 1999-05-21 |
| JP3792865B2 JP3792865B2 (en) | 2006-07-05 |
Family
ID=17856926
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29823097A Expired - Fee Related JP3792865B2 (en) | 1997-10-30 | 1997-10-30 | Semiconductor device manufacturing apparatus and dry etching method |
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| Country | Link |
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Cited By (5)
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|---|---|---|---|---|
| WO2003009363A1 (en) * | 2001-07-10 | 2003-01-30 | Tokyo Electron Limited | Plasma processor and plasma processing method |
| JP2007234869A (en) * | 2006-03-01 | 2007-09-13 | Hitachi High-Technologies Corp | Etching processing apparatus, monitoring method thereof, and self bias voltage measuring method |
| JP2014186994A (en) * | 2013-02-20 | 2014-10-02 | Tokyo Electron Ltd | Plasma processing device, and plasma processing method |
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-
1997
- 1997-10-30 JP JP29823097A patent/JP3792865B2/en not_active Expired - Fee Related
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| WO2003009363A1 (en) * | 2001-07-10 | 2003-01-30 | Tokyo Electron Limited | Plasma processor and plasma processing method |
| US8056503B2 (en) | 2001-07-10 | 2011-11-15 | Tokyo Electron Limited | Plasma procesor and plasma processing method |
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| JP2007234869A (en) * | 2006-03-01 | 2007-09-13 | Hitachi High-Technologies Corp | Etching processing apparatus, monitoring method thereof, and self bias voltage measuring method |
| JP4657949B2 (en) * | 2006-03-01 | 2011-03-23 | 株式会社日立ハイテクノロジーズ | Etching processing apparatus, self-bias voltage measuring method, and etching processing apparatus monitoring method |
| JP2014186994A (en) * | 2013-02-20 | 2014-10-02 | Tokyo Electron Ltd | Plasma processing device, and plasma processing method |
| JP2016032096A (en) * | 2014-07-25 | 2016-03-07 | 株式会社日立ハイテクノロジーズ | Plasma processing device |
| JP2019186334A (en) * | 2018-04-06 | 2019-10-24 | 東京エレクトロン株式会社 | Plasma processing machine and plasma processing method |
| US11875977B2 (en) | 2018-04-06 | 2024-01-16 | Tokyo Electron Limited | Plasma processing apparatus and plasma processing method |
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