JPH11127421A - Scan converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan converting circuit capable of further reducing a memory capacity necessary for converting the scan system of a video signal. SOLUTION: This circuit 10 is provided with a memory part 16 constituted of (2<n> +1) pieces of memory blocks (only M1-M5 are shown here) for independently writing or reading a video signal, and respectively storing video signals by 1/2<n> ((n) is an integer more than 2) fields. The circuit 10 is controlled so that each video signal is sequentially written in a memory block which is turned into an empty area at the time point when the video signal is inputted among the (2<n> +1) pieces of memory blocks of this memory part 16, and the scan system of the video signal is converted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan conversion circuit for converting a video signal scanning system from an interlaced system to a non-interlaced system or from a non-interlaced system to an interlaced system.

[0002]

2. Description of the Related Art The interlaced system is also called interlaced scanning, and one frame of the interlaced system is, as shown in FIG.
A first (odd) field composed of a plurality of scanning lines scanned every other and a second (even) field composed of a plurality of scanning lines scanned between each scanning line of the first field. You. On the other hand, the non-interlace method is also called progressive scanning, and one frame is
As shown in FIG. 6 (b), it is composed of a plurality of scanning lines that are continuously scanned sequentially.

Hereinafter, a conventional scan conversion circuit will be described. Here, FIGS. 7A and 7B show a case where an interlaced video signal is converted into a non-interlaced video signal and a case where a non-interlaced video signal is converted into an interlaced video signal, respectively. FIG. 5 is an operation conceptual diagram of the conventional scan conversion circuit of FIG. The solid line in the figure indicates writing to the memory area,
Dotted lines indicate reading from the memory area.

As shown in FIG. 1, when a conventional scan conversion circuit converts an interlaced video signal into a non-interlaced video signal, first, an odd field video signal is stored in a memory area A for one field. The video signals of the even fields are successively written to the memory area B for one field, and the video signals of the odd and even fields are alternately switched from the memory areas A and B one line at a time. Are sequentially read out.

On the other hand, when a non-interlaced video signal is converted to an interlaced video signal, the non-interlaced video signal is converted into memory areas A and B as interlaced odd and even field video signals. The video signals of the odd-numbered fields are sequentially read out from the memory area A, and then the video signals of the even-numbered fields are sequentially read out from the memory area B. Is read.

As described above, in the conventional scanning circuit, the scanning method of the video signal is converted. However, since the conversion of the scanning method of the video signal requires a memory capacity for two fields, the cost is high. There was a problem of becoming. On the other hand, Japanese Patent Application Laid-Open No. 7-95542 discloses a video signal conversion device capable of converting a video signal scanning method with a memory for (1 + α (1/3 ≦ α <1)) fields. ing.

[0007] The video signal conversion device disclosed in the publication discloses an addressing control for a memory,
The capacity of the memory is increased from two fields of the prior art to (1 + 1 /
3) The data can be reduced to the number of fields, and the data of the other field is sequentially written and read from the time when the data of one field is read until the next data is written to that part. Thus, a partial area of the memory is fixedly shared by both fields.

[0008] The operation of the video signal converter disclosed in the publication will be described below. Here, FIGS. 8A and 8B show the case where the video signal of the interlace system is converted into the video signal of the non-interlace system, respectively, and
FIG. 3 is an operation conceptual diagram of a video signal conversion device disclosed in the same publication when converting a non-interlaced video signal into an interlaced video signal. Similarly, a solid line in the figure indicates writing to the memory area, and a dotted line indicates reading from the memory area.

When converting an interlaced video signal into a non-interlaced video signal, first, odd-numbered field video signals are sequentially written to memory areas A1, A2, and A3 each corresponding to 1/3 field. Subsequently, the video signal of the first １ ／ field of the even field is sequentially written into the memory area B of １ ／ field, and at the same time, the first one of the odd and even fields is read from the memory areas A1 and B. The video signals for / 3 fields are alternately read out line by line.

After the writing of the video signal of the first 1/3 field of the even field into the memory area B is completed, the video signal of the first 1/3 field of the odd and even fields from the memory areas A1 and B is completed. At the time when half of the reading of the even field is completed,
The video signal for the field is the first one of the odd fields.
The video signal for / 3 fields is sequentially written to the empty area of the memory area A1 from which half has been read.

Then, the reading of the video signal for the first 1/3 field of the odd and even fields from the memory areas A1 and B is completed, and the second 1 of the even field is completed.
After the writing of the video signal for the フ ィ ー ル ド field into the memory area A1 is completed, the video signal for the last ３ field of the even field is sequentially written to the memory area B, and at the same time, the data is read from the memory areas A2 and A1. , The video signals of the second 1/3 field of the odd and even fields are alternately read out line by line.

After reading of the video signals of the second third of the odd and even fields from the memory areas A2 and A1, the memory areas A3 and B are read out.
Thus, video signals for the last 1/3 field of the odd and even fields are alternately read out line by line. In this manner, the interlaced video signal is converted to a non-interlaced video signal.

On the other hand, when converting a non-interlaced video signal into an interlaced video signal, first, the non-interlaced video signal is converted to the first one of the interlaced odd and even fields.
Memory areas A and B as video signals for / 3 fields
1 is alternately and sequentially written line by line, and subsequently, as a video signal for the second ３ field, is alternately and sequentially written line by line into the memory areas B3 and B2.

At the time when the writing of the video signal of the second third の field of the odd and even fields to the memory areas B3 and B2 is half completed, the first フ ィ ー ル ド field of the odd field is removed from the memory area A. Are sequentially read out.

Subsequently, the reading of the video signal of the first １ ／ field of the odd field from the memory area A is completed, and the reading of the video signal of the second 数 field of the odd and even fields into the memory areas B3 and B2 is completed. After the writing of the video signal is completed, the video signal of the second 1/3 field of the odd field is read out from the memory area B3, and at the same time, the video signal of the non-interlace system is changed to the odd and even interlace system. The video signal for the last フ ィ ー ル ド field of the field is alternately and sequentially written line by line in the memory areas A and B3.

The odd field 2 from the memory area B3
After the reading of the video signal for the first 1/3 field is completed, when the writing of the video signal for the last 1/3 field of the odd and even fields to the memory areas A and B3 is half completed, the memory area From A, the video signal of the last 1/3 field of the odd field is sequentially read, and subsequently, the video signal of the even field is sequentially read from the memory areas B1, B2, and B3. Thus, the non-interlaced video signal is converted into the interlaced video signal.

According to this video signal conversion device, the memory for a maximum of 2/3 fields can be reduced as compared with the conventional one, and the number of components such as a digital VTR can be reduced. The company says that it will be possible to reduce costs and power consumption. However, in this video signal conversion device, since the shared memory area is fixedly used, a memory capacity of (1 + ／) fields or more is required even if the reduction is theoretically possible. There is a problem that there is.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan conversion circuit capable of further reducing the memory capacity required for converting a video signal scan system in view of the above-mentioned problems in the prior art. Is to provide.

[0019]

In order to achieve the above object, the present invention provides a method for scanning an input video signal.
A scan conversion circuit for converting from an interlaced system to a non-interlaced system or from a non-interlaced system to an interlaced system, each of which can independently write or read the video signal.
/ 2 ⁿ (where n is an integer equal to or greater than 2) a memory unit having (2 ⁿ +1) memory blocks for storing the video signals for the field, and the memory unit according to the scanning method. A write data control unit that performs control for writing a video signal, and a read data control unit that performs control for reading the video signal written to the memory unit according to the scan method, wherein the write data The control unit controls the video signal to be sequentially written into a memory block which is an empty area when the video signal is input among the (2 ⁿ +1) memory blocks of the memory unit. A scan conversion circuit is provided.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a scan conversion circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a conceptual diagram of one embodiment of the scan conversion circuit of the present invention. The illustrated scan conversion circuit 10
Is to convert the scanning method of the video signal input as input data from the interlaced method to the non-interlaced method, or from the non-interlaced method to the interlaced method, and output as output data.
It has a write data control unit 12, a read data control unit 14, and a memory unit 16.

In the scan conversion circuit 10, first, the write data control section 12 performs control for writing a video signal input as input data to the memory section 16 in accordance with a scan method. On the other hand, the read data control unit 14 performs control for reading the video signal written in the memory unit 16 according to the scan method and outputting the read video signal as output data.

The memory section 16 temporarily stores the video signal in order to convert the scanning method of the video signal. In the illustrated example, the memory section 16 stores the video signal for each 1/4 field. Memory blocks M1,
M2, M3, M4, and M5. That is, the scan conversion circuit 10 in the illustrated example has a memory capacity for a total of (1 + 1/4) fields. Note that each memory block M
Each of 1 to M5 can independently write or read a video signal.

In the illustrated scan conversion circuit 10, the video signal of one field is divided into four parts,
Although five memory blocks M1 to M5 having a memory capacity of 1/4 field are provided as an example, the present invention is not limited to this. ^{It suffices to} divide by ⁿ (n is an integer of 2 or more) and provide (1 + 2 ⁿ ) memory blocks having a memory capacity of ^{n n} fields as the memory unit 16.

As described above, by dividing the video signal into 2 ⁿ and providing (1 + 2 ⁿ ) memory blocks as the memory section 16, the write data control section 12,
Further, the addressing control of the memory unit 16 by the read data control unit 14 can be facilitated. For example, a video signal is divided into four or eight,
In the case of division into sixteen, addressing control for each memory block can be performed by the upper two bits, three bits, and four bits of the address signal.

Here, it is preferable to increase the number of divisions in order to reduce the memory capacity of the memory unit 16, but it is preferable to reduce the number of divisions in order to facilitate addressing control for the memory unit 16. It is most preferable to divide into four. Therefore, it is preferable to appropriately determine the number of divisions in consideration of the memory capacity of the memory unit 16 and ease of addressing control. The minimum value of the memory capacity of the memory unit 16 in the present invention is the memory capacity for one field + 1 line.

The scan conversion circuit 10 of the present invention basically has the above configuration. Next, the operation of the scan conversion circuit 10 of the present invention will be described.

First, the operation of the scan conversion circuit 10 when converting an interlaced video signal into a non-interlaced video signal will be described with reference to the operation conceptual diagrams shown in FIGS. Here, FIG.
FIG. 3 is an operation conceptual diagram of one embodiment showing the operation of the scan conversion circuit of the present invention. FIG. 3 is a conceptual diagram of one embodiment showing the order of writing video signals to the memory unit of the scan conversion circuit of the present invention. FIG.

In FIG. 2, memory blocks M1, M
2, M3, M4, and M5 indicate the flow of time from the left side to the right in the figure, and indicate the use status of each memory block M1 to M5 of the memory unit 16 at each time in the up and down direction. Note that a halftone dot portion indicates a state in which the video signal of the odd field is written in the memory block, and a hatched portion indicates
The state where the video signal of the even field is written in the memory block is shown, and the blank portion indicates that the memory block is empty (unused state).

The write order is such that the write data control unit 12 operates in the memory block M 1 of the memory unit 16.
The order in which the video signals are written to the memory block M1 of the memory unit 16 is shown in FIG.
3 shows the order in which video signals are read from M5.
Note that the solid line in the figure indicates writing to the memory unit 16,
Dotted lines indicate reading from the memory unit 16.

In FIG. 3, the video signals of the odd fields (1, 3, 5,...) Of the interlaced system are divided into four, respectively, as f11, f12, f13, f14, and the even fields (2, 4, 6, 6). ,...) Are divided into four to be f21, f22, f23, and f24, respectively.
In the interlace method, the odd-numbered field video signal f
Input data is input in the order of 11, f12, f13, f14 and the video signals f21, f22, f23, f24 of the even field.

As shown in these figures, when converting an interlaced video signal into a non-interlaced video signal, first, video signals f11, f12, f13, and f14 of the odd fields of the first frame are respectively stored in a memory. Data is sequentially written to blocks M1, M2, M3, and M4. Writing and reading of the video signal to and from each of the memory blocks M1 to M5 are performed by the write data control unit 12 and the read data control unit 1.
4 is performed.

After the writing of the video signal f14 to the memory block M4 is completed, the video signal f21 of the even field of the first frame is sequentially written to the memory block M5, and at the same time, the video signal f21 is output from the memory blocks M1 and M5. f11 and f21 are alternately read out line by line. As described above, the video signals of the odd and even fields are alternately read out line by line, whereby the interlaced video signal is converted into a non-interlaced video signal.

After the writing of the video signal f21 to the memory block M5 is completed and the reading of the video signals f11 and f21 from the memory blocks M1 and M5 is half, the video signal f22 is changed to the video signal of the memory block M1. f11 is sequentially written into the empty area after half reading. Subsequently, after the reading of the video signals f11 and f21 from the memory blocks M1 and M5 is completed, the video signals f12 and f22 are sequentially read from the memory blocks M2 and M1 one by one in the same manner.

The reading of the video signals f11 and f21 from the memory blocks M1 and M5 is completed, and the video signals f11 and f21 are read.
After the writing to the memory block M1 of No. 22 is completed,
The memory block M5 in which the video signal f23 has become an empty area.
Are written sequentially. After the video signal f23 has been written into the memory block M5, the memory block M2
When the reading of the video signals f12 and f22 from M1 is half completed, the video signal f24 is output to the memory block M1.
Of the video signal f22 is sequentially written into the empty area after half the reading.

Subsequently, after the reading of the video signals f12 and f22 from the memory blocks M2 and M1, the video signals f13 and f2 are read from the memory blocks M3 and M5, respectively.
3 are alternately read line by line, and finally, video signals f14 and f24 are alternately read line by line from the memory blocks M4 and M1, respectively. In this manner, the video signal of the first frame of the interlace system is converted into a video signal of the non-interlace system.

Here, after the video signal f24 of the even field of the first frame is written into the memory block M1, the video signal f11 of the odd field of the second frame is continuously input as input data. At this time, since the video signal f24 of the even field of the first frame is written in the memory block M1, the video signal f11 of the second frame is written in the memory block M1 in the same manner as the video signal f11 of the first frame. It is not possible.

For this reason, in the scan conversion circuit 10, the memory block M1 to which each video signal is written
To M5 are not used in a fixed manner, but are sequentially rotated, and the video signals are sequentially written to the memory blocks M1 to M5 which are empty when the video signals are input. For example, the video signal f11 of the second frame
Is written not in the memory block M1 but in the memory block M2 which is in an empty area when the video signal f11 of the second frame is input as input data.

In the scan conversion circuit 10 in the illustrated example, as shown in FIG. 3, the write and read operations related to the conversion control of the first frame are defined as a pattern a.
If the operations related to the conversion control of the second frame and the third frame are patterns b and c, respectively, these patterns a and
By successively repeating a series of conversion controls consisting of b and c, an interlaced video signal can be continuously converted to a non-interlaced video signal.

In the above embodiment, the writing and reading operations are controlled so as to return to the original state by the three patterns a, b, and c. However, the present invention is not limited to this. Write and read control may be performed by one or more patterns.
It goes without saying that the smaller the number of patterns is, the easier the control in the write data control unit 12 and the read data control unit 14 is.

Next, the operation of the scan conversion circuit 10 when converting a non-interlaced video signal into an interlaced video signal will be described with reference to the operation conceptual diagrams shown in FIGS. Here, FIG.
FIG. 5 is an operation conceptual diagram of another embodiment showing the operation of the scan conversion circuit of the present invention. FIG. 5 is another embodiment showing the order of writing video signals to the memory section of the scan conversion circuit of the present invention. FIG.

FIGS. 4 and 5 correspond to FIGS. 2 and 3 respectively.
Since it is described in exactly the same format as in the case of, a detailed description thereof is omitted here. In the non-interlace system, the video signals f11, f12, f13, and f14 in the odd fields of the interlace system and the video signals f21, f22, f23, and f24 in the even fields are one.
Lines are alternately folded, and input data is input in the order of sequential scanning.

As shown in FIGS. 4 and 5, when a non-interlaced video signal is converted to an interlaced video signal, first, the video signal of the first frame of the non-interlaced video is converted to an odd and even interlaced video signal. As field video signals f11 and f21,
The lines are alternately and sequentially written to the memory blocks M4 and M1 line by line, and then sequentially and alternately line by line to the memory blocks M5 and M2 as video signals f12 and f22.

After the writing of the video signals f12 and f22 into the memory blocks M5 and M2 is completed, the video signals f11 are sequentially read from the memory block M4, and at the same time, the video signals of the first frame of the non-interlace system are interlaced. Empty areas after the video signal f11 of the memory block M4 has been read out as the video signals f13 and f23 of the odd and even fields of the system, and
The data is alternately written to the memory block M3 line by line.

Subsequently, after reading of the video signal f11 from the memory block M4 is completed,
4, when the writing of the video signals f13 and f23 to M3 is completed half, the video signal f1 is read from the memory block M5.
2 are sequentially read.

After the reading of the video signal f12 from the memory block M5 is completed and the writing of the video signals f13 and f23 to the memory blocks M4 and M3 are completed, the video signal f13 is sequentially read from the memory block M4. The free space after the video signal f13 of the memory block M5 and the memory block M4 is read out as the video signals f14 and f24 of the odd and even fields of the interlaced system in which the video signal of the first frame of the non-interlaced system is read. Are written alternately and sequentially one line at a time.

After the reading of the video signal f13 from the memory block M4 is completed, when the writing of the video signals f14 and f24 to the memory blocks M5 and M4 is half completed, the video signal f14 is sequentially read from the memory block M5. Then, the memory blocks M1, M2, M3,
Video signals f21, f22, f23 and f24 are sequentially read from M4. In this manner, the video signal of the first non-interlaced frame is converted to an interlaced video signal.

Here, when a non-interlaced video signal is converted into an interlaced video signal, the second frame is converted in exactly the same way as when an interlaced video signal is converted into a non-interlaced video signal. Cannot be written in the same memory block M1 as the video signal of the first frame. For this reason, the memory blocks M1 to M5 are sequentially rotated, and the respective video signals are sequentially written to the memory blocks that are empty when the video signals are input.

For example, in the scan conversion circuit 10 in the illustrated example, as shown in FIG. 5, the write and read operations related to the conversion control of the first frame are performed in a pattern a.
If the operations related to the conversion control of the second frame and the third frame are patterns b and c, respectively, a series of conversion controls of these patterns a, b, and c are sequentially and repeatedly performed to obtain a non-interlaced video. The signal can be continuously converted into an interlaced video signal.

The scan conversion circuit 10 of the present invention is basically as described above. As described above, the scan conversion circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and changes may be made without departing from the gist of the present invention. is there.

[0051]

As described above in detail, the scan conversion circuit of the present invention can independently write or read a video signal, and each of them can be 1/2 ⁿ (n is an integer of 2 or more).
A memory unit including (2 ⁿ +1) memory blocks for storing video signals for a field is provided. Of the (2 ⁿ +1) memory blocks in this memory unit, when a video signal is input, a vacant portion is provided. By controlling each video signal to be sequentially written into a memory block serving as an area, the scanning method of the video signal is converted.
According to the scan conversion circuit of the present invention, the memory capacity necessary for converting the scan mode of the video signal is (1 + 1 /
4) It can be reduced to the field or less, which has the effect of enabling further downsizing, lower cost, and lower power consumption.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of one embodiment of a scan conversion circuit of the present invention.

FIG. 2 is an operation conceptual diagram of one embodiment showing an operation of the scan conversion circuit of the present invention.

FIG. 3 is a conceptual diagram of one embodiment showing an order of writing a video signal to a memory unit of the scan conversion circuit of the present invention.

FIG. 4 is an operation conceptual diagram of another embodiment showing the operation of the scan conversion circuit of the present invention.

FIG. 5 is a conceptual diagram of another embodiment showing the order of writing video signals to the memory unit of the scan conversion circuit of the present invention.

FIGS. 6A and 6B are conceptual diagrams of an example of a scanning method. FIG.

FIGS. 7A and 7B are conceptual diagrams illustrating an example of an operation of a conventional scan conversion circuit. FIG.

FIGS. 8A and 8B are operation conceptual diagrams of another example showing the operation of a conventional scan conversion circuit; FIG.

[Explanation of symbols]

 Reference Signs List 10 scan conversion circuit 12 write data control unit 14 read data control unit 16 memory unit M1, M2, M3, M4, M5 memory block

Claims (1)

[Claims] 1. A scan conversion circuit for converting a scanning method of an input video signal from an interlaced method to a non-interlaced method or from a non-interlaced method to an interlaced method, each of which independently writes or writes the video signal. A memory unit having (2 ⁿ +1) memory blocks each capable of reading and storing 1/2 ⁿ (where n is an integer of 2 or more) fields of the video signal; A write data control unit that performs control for writing the video signal to the memory unit; and a read data control unit that performs control for reading the video signal written to the memory unit according to the scan method. with the door, the write data control unit, the memory unit (2 ⁿ + ) Number of the memory blocks, the at the time when the video signal is input, a scan conversion circuit and controls so as to sequentially write each said video signal to a memory block that is to be free space.