JPH11126810A - Measurement method of crystal defect - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately evaluate the depth directional distribution of a specific crystal defect density by a method, wherein a crystal defect layer in a substrate of a semiconductor device after removing the upper layer crystal defect layer so as to cause no irregularities due to the crystal defect, the lower layer crystal defect is measured. SOLUTION: Aluminum electrodes 8 are removed by immersing an inspected semiconductor device in a heated phosphoric acid. Next, a field oxide film 2, a silicon oxide film 3 and inter-layer films 7 are removed using the hydrofluoric acid. Successively, a wafer formed of P/N diode is led into a dry etching device to remove a p-type layer 5 through by etching step using CF 4 gas. Furthermore, C remaining on the surface of the p/n diode as well as a natural oxide film are removed, and then the whole surface is etched away using secco solution so as to observe the etch pit numbers formed on the surface of an n-type embedded layer 4. In such a constitution, the steps are repeated so as to measure distribution in the depth direction of the crystal density due to the embedded layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor evaluation method capable of accurately measuring a desired crystal defect layer when a plurality of crystal defect layers exist in the semiconductor.

[0002]

2. Description of the Related Art In recent years, attempts have been made to form a buried collector layer of a Bipolar or BiCMOS transistor by high energy ion implantation from conventional epitaxial growth for the purpose of cost reduction and TAT. In the high-energy ion implantation used for these technologies,
In order to operate the device at higher speed, it is necessary to lower the collector resistance, and a higher dose than the impurity dose (<5 × 10 ¹³ cm ⁻² ) conventionally used for well formation or the like is required. It is considered that it is desirable to use a dose of about 1 × 10 ¹⁴ cm ⁻² more practically from the viewpoint of the balance between the collector resistance and the withstand voltage since the collector withstand voltage is reduced when the height is increased.

As shown in FIG. 9, P (phosphorus) ions are applied to a p-type Si substrate 93 subjected to element isolation 90 at an acceleration voltage of 1 Me.
V, a dose of 1 × 10 ¹⁴ cm ⁻² was implanted, and then RTA (Rapid Thermal Anneal).
a buried layer 91 formed by performing a heat treatment according to an annealing method, and ion implantation of BF ₂ under the conditions of an acceleration voltage of 30 keV and a dose of 3 × 10 ¹⁵ cm ⁻² to form a p-type layer 92 by performing a heat treatment. The corresponding p / n of the base and collector regions of the transistor
When a diode is manufactured, a defect grows from the vicinity of the buried layer 91 toward the sample surface depending on the conditions of the heat treatment by the RTA method, and the leak current of the p / n diode increases.

The density distribution in the depth direction of the defect is calculated as p / n
Diode mixed solution of dichromic acid, hydrofluoric acid and water
(Seco solution) caused by chemical etching
When the inspection is performed by observing the
BF performed to form 2 _TwoDue to the effects of ion implantation
Therefore, a high density near the depth of 30 nm in the p-type layer 92 is obtained.
Due to the presence of defects, the silicon substrate surface
When etching is performed more than 30 nm deep, the sample surface
Irregularities are generated in the chip, and the chip grown from the vicinity of the buried layer 91 is formed.
The accuracy of the densitometry is reduced.

As a first method for solving this problem, the p-type layer is removed in advance using a mixture of nitric acid, hydrofluoric acid, and glacial acetic acid that does not generate etch pits, and then chemically etched using a Seco solution. Thus, a method of measuring the density of defects grown from the vicinity of the buried layer 91 has been adopted. In addition, as a second method, a method of slicing a sample using mechanical polishing, ion milling, or the like, and measuring the defect density by observing the sample with a transmission electron microscope (TEM) has been performed.

Further, as a third method, Japanese Patent Application Laid-Open No. Hei 7-130811 discloses a method of measuring the defect density of a sample having a plurality of defects by using an infrared tomograph and measuring the defect size in a nondestructive manner. A method for accurately measuring the defect density by correcting the effect of the difference in the observation region caused by the difference is disclosed.

[0007]

According to the first method, however, the high concentration p-type layer is etched (hereinafter referred to as pre-etching) using a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid. In addition, the surface is nitrided to cause roughness, and the subsequent etching accuracy by the Seco solution is significantly reduced.

Further, when there are a plurality of samples to be measured, since the etching rate of the pre-etched sample varies depending on the temperature of the solution and the degree of agitation, even if pre-etching is performed for the same time, the pre-etched region is There is a problem that fluctuation occurs. Further, in the second method, it is necessary to thin the sample to a thickness through which the electron beam can pass, and it is difficult to measure the defect density existing at the same depth over a large area of 100 μm ² or more.

Further, in the third method, since the beam diameter of the infrared laser beam is large, even if the laser beam can be moved at a very short pitch in a depth region to be evaluated by the present invention, JP-A-7-13081
1, the total number of defects _NG including the duplicate observation and the net number of defects _NN become almost the same, and the defect density cannot be calculated accurately.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, to remove the upper crystal defect layer without damaging the sample, and to subsequently remove the state of the crystal defect layer where crystal defects exist. And a method for measuring a crystal defect which can easily and accurately detect and evaluate the crystal defect.

[0011]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, when a crystal defect layer is present in a plurality of layers in a substrate of a semiconductor device, the crystal defect layer is detected and evaluated so that the upper crystal defect layer does not have unevenness due to the crystal defect. And a step of measuring a crystal defect of a lower layer after the step of removing the upper layer.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS That is, in the method of measuring crystal defects according to the present invention, for example, when a plurality of crystal defect layers are present in a semiconductor and different crystal When defects are present, the upper crystal defect layer is removed by performing dry etching or scanning a focused ion beam on the surface of the sample so as not to cause unevenness due to crystal defects, and then the crystal defect density of the lower layer is reduced. More specifically, even if there are different crystal defects in the upper layer of the region where the crystal defect density measurement is to be performed, dry etching or focused ion beam with low acceleration and By irradiating the sample at a low angle condition, it is possible to remove the defect in the upper layer without damaging the sample, so that there is a crystal defect after that. And perform chemical etching with a solution etch pit occurs, resulting crystal defect density in a desired region by observing the etch pits can be measured accurately.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a specific example of a method for measuring crystal defects according to the present invention will be described below in detail with reference to the drawings.
A first specific example of the present invention will be described with reference to the drawings. FIG.
FIG. 4 is a cross-sectional view of a sample on which depth direction defect density measurement is performed according to the first specific example of the present invention, and FIG. 2 illustrates a process of performing depth direction defect density measurement according to the first example of the present invention. FIG. 3A is a diagram showing five sampling positions from within the wafer surface obtained by the first embodiment of the present invention, and FIG. 3B is a diagram showing each of the sampling positions. FIG. 5 is a diagram showing a distribution of defect densities in a depth direction.

As shown in FIG. 1, a sample is formed by depositing a field oxide film 2, a silicon oxide film 3, and P (phosphorus) ions on a p-type silicon single crystal substrate 1 at an acceleration voltage of 1 MeV and a dose of 1 × 1.
After ion implantation under the condition of 0 ¹⁴ cm ^-2 , the n-type buried layer 4 and BF2 formed by performing a heat treatment at a temperature of 1050 ° C. and a temperature increase rate of 100 ° C./sec by RTA are accelerated to an acceleration voltage of 30 keV. Surface area 50 formed by heat treatment after ion implantation under the condition of dose 3 × 10 ¹⁵ cm ^-2
0 μm ² □ p-type layer 5 and P (phosphorus) at 70 keV, 5 ×
The n-type buried layer contact layer 6, the interlayer film 7, the p-type layer 5, and the n-type buried layer contact formed by heat treatment after ion implantation under the conditions of 10 ¹⁵ cm ⁻² and 250 keV and 3 × 10 ¹³ cm ^−2. A p / n diode composed of an aluminum electrode 8 on the layer 6
It is formed at three places.

The wafer on which the p / n diodes having the structure shown in FIG. 1 are formed is configured so that a predetermined processing operation is executed according to a flowchart shown in FIG. The aluminum electrode 8 is removed by immersing the semiconductor device under test in heated phosphoric acid (first step), and then the field oxide film 2 and the silicon oxide film 3 are removed.
Then, the interlayer film 7 is removed using hydrofluoric acid (second step).

Next, the wafer on which the p / n diodes are formed is introduced into a dry etching apparatus, and the etching rate is set to 50 nm / min. Etching is performed for 4 minutes using CF4 gas under the conditions described above to remove the p-type layer 5 (third step). Next, C remaining on the surface of the p / n diode is removed using Branson cleaning (fourth step), and a natural oxide film on the surface is removed using a dilute hydrofluoric acid solution (fifth step). Etching is performed for 10 seconds using the liquid (sixth step), the number of etch pits formed on the surface of the n-type buried layer 4 is measured (seventh step), and the process returns to the fifth step and returns to the same step. Is removed with a dilute hydrofluoric acid solution to remove the natural oxide film on the surface, and then etched with a Seco solution for 10 seconds to form an n-type buried layer 4 directly under the p-type layer 5 at the edge and the center of the wafer at five places. The number of etch pits caused by the resulting defect is measured.

Further, by removing the natural oxide film on the surface by using the dilute hydrofluoric acid solution, the following steps are repeated to obtain a defect density caused by the n-type buried layer 4 at five places in the wafer surface as shown in FIG. Was able to be measured as shown in FIG. Next, a second specific example of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view of a sample on which defect density measurement was performed according to the second embodiment of the present invention.
FIG. 5 is a diagram showing a result of measuring a leak current output from the aluminum electrode 29 at five places in the wafer by applying a voltage of −5 V to the aluminum electrode 28 of the sample of FIG. 4 and a measurement position in the wafer. FIG. 6 is a flowchart illustrating a process of measuring a defect density according to the second embodiment of the present invention, and FIG. 7 is a diagram illustrating a boron depth direction concentration distribution in a sample obtained by secondary ion mass spectrometry (hereinafter, SIMS) measurement. FIG. 8 is a diagram showing the measurement results of the defect densities at five places in the wafer surface and the measurement positions in the wafer obtained by the second embodiment of the present invention.

As shown in FIG. 4, a sample is formed by depositing a field oxide film 22, a silicon oxide film 23, and P (phosphorus) ions on a p-type silicon single crystal substrate 21 at an acceleration voltage of 1 MeV and a dose of 1
After ion implantation under the condition of x10 ¹⁴ cm ^-2 , the n-type buried layer 24, B formed by performing a heat treatment by RTA at a temperature of 1100 ° C. at a rate of 200 ° C./sec.
F2 is ion-implanted under the conditions of an acceleration voltage of 30 keV and a dose of 3 × 10 ¹⁵ cm ⁻² , and then heat treatment is performed to form a p-type layer 25 having a surface area of 500 μm ² □ and P (phosphorus) of 70 ke.
V, 5 × 10 ¹⁵ cm ⁻² and 250 keV, 3 × 10 ¹³ c
m buried layer of n-type formed by heat treatment after ion-implanted under the conditions ^-2 contact layer 26, an interlayer film 27 and p
On the mold layer 25 and on the n-type buried layer contact layer 26, 53 p / n diodes composed of aluminum electrodes 28 and 29 are formed in the wafer surface.

When a voltage of -5 V is applied to the aluminum electrode 28 of the p / n diode having the structure shown in FIG. 4, a leak current output from the aluminum electrode 29 is applied to the inside of the wafer as shown in FIG. As a result of measurement at the points, it was found that the values showed different values. P / n in FIG.
From the result of the CV measurement, the depletion layer of the diode was 0.5 μm in depth when a voltage of −5 V was applied to the aluminum electrode 28.
In order to investigate the relationship between the defect caused by the n-type buried layer 24 and the difference in the leak current obtained in FIG. 5, according to the flowchart shown in FIG.
First, the aluminum electrodes 28 and 29 are removed by immersing the semiconductor device in heated phosphoric acid (first step), and then the field oxide film 22, the silicon oxide film 23, and the interlayer film 27 are formed.
Is removed using hydrofluoric acid (second step).

Next, in FIG. 5 in the wafer on which the p / n diode is formed, a p / n diode whose leakage current is actually measured is cut out (third step).
Using a SIMS chip, the secondary ion intensity distribution in the depth direction of boron and silicon of the p-type layer 25 having the surface area of 500 μm ² □ was set to primary ion Ar ⁺ , the acceleration voltage was 4 keV, and the raster region of the primary ion beam was 550 μm ² □. The analysis area was measured at 100 μm ² □ at the center of the p-type layer 25 so that the incident angle of the primary ions was 10 degrees with respect to the sample.

By measuring the secondary ion intensity of boron, the secondary ion intensity of silicon, and a sample in which silicon has a known concentration of boron in advance under the above-mentioned measurement conditions, the silicon in the silicon which has been determined in advance is obtained. The secondary ion intensity of boron being measured is converted into boron concentration from the relative sensitivity coefficient of boron, and the measurement is stopped when the boron concentration becomes 1 × 10 ¹⁸ cm ⁻² .

Next, the SIM is measured using a stylus type surface roughness meter.
Measure the depth of the crater generated by the S measurement (No. 5
Step), a boron concentration distribution in the depth direction as shown in FIG. 7 is obtained. Next, SIMS measurement was performed on the other four chips under the same conditions while monitoring the concentration distribution of boron in the depth direction (sixth step), and the boron concentration was 1 × 10 ¹⁸ cm, as in the first chip. Stop measurement at ^-2 . As a result, the p-type layer 25 has a depth of 0.2 for each chip.
μm was etched.

Next, after the natural oxide film on the surface is removed using a dilute hydrofluoric acid solution (seventh step), etching is performed for 20 seconds using a Seco solution (eighth step), and the p-type layer 25 is removed. The number of etch pits generated immediately below the region having a depth of 0.5 μm is measured (ninth step). As a result, as shown in FIG. 8, the defect density at five points in the wafer surface can be obtained. By comparing the defect density with the defect in FIG. 5, the defect density of the chip having a higher leak current is higher than that of the chip having a lower leak current. It was found that the density was increasing.

[0024]

As described above, according to the present invention, even if different crystal defects exist in the upper layer of the region where the defect density is to be measured, dry etching or focused ion beam with low acceleration and low Irradiation at a low angle condition removes defects in the upper layer, and then performs chemical etching using a solution in which etch pits are generated due to the presence of crystal defects, and observes the generated etch pits to observe the crystal in the upper layer. The distribution of the desired crystal defect density in the depth direction can be accurately measured without being affected by defects.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a sample on which depth-direction defect density measurement was performed according to a first specific example of the present invention.

FIG. 2 is a diagram illustrating a process of performing a depth direction defect density measurement according to a first specific example of the present invention.

FIG. 3A is a view showing an example of a sampling position in detecting a defect density of a crystal defect layer in a semiconductor device to be inspected, and FIG. First
FIG. 8 is a diagram showing the depth direction distribution of the defect density at five locations in the wafer surface obtained by the specific example of FIG.

FIG. 4 is a cross-sectional view of a sample on which defect density measurement was performed according to a second specific example of the present invention.

5A is a diagram showing an example of a sampling position when detecting a defect density of a crystal defect layer in a semiconductor device to be inspected, and FIG. 5B is a diagram showing a sampling position in FIG. A voltage of -5 V was applied to the aluminum electrode 28 of the sample
FIG. 9 is a diagram showing a result of measuring a leak current output from a wafer 9 at five locations in the wafer and a measurement position in the wafer.

FIG. 6 is a diagram illustrating a process of performing a defect density measurement according to a second specific example of the present invention.

FIG. 7 shows secondary ion mass spectrometry (hereinafter SIMS).
5 is a boron depth direction concentration distribution in a sample obtained by measurement.

8A is a diagram showing an example of a sampling position when detecting a defect density of a crystal defect layer in a semiconductor device to be inspected, and FIG. 8B is a diagram showing a sampling position in FIG. A voltage of -5 V is applied to the aluminum electrode 28 of the sample
FIG. 9 is a diagram showing a result of measuring a leak current output from a wafer 9 at five locations in the wafer and a measurement position in the wafer. FIG. 11 is a diagram showing the measurement results of the defect densities at five locations in the wafer surface and the measurement positions in the wafer obtained by the second specific example of the present invention.

FIG. 9 is a cross-sectional view of a sample on which defect density measurement was performed according to a conventional example.

[Explanation of symbols]

 1,21 p-type silicon single crystal substrate 2,22 field oxide film 3,23 silicon oxide film 4,24 n-type buried layer 5,25 p-type layer 6,26 n-type buried layer contact layer 7,27 interlayer film 8 Aluminum electrode 28 Aluminum electrode (voltage application side) 29 Aluminum electrode (current detection side)

Claims (6)

[Claims] When a crystal defect layer is present in a plurality of layers in a substrate of a semiconductor device, the crystal defect layer is detected and evaluated. A method for measuring crystal defects, comprising: a step of removing so as not to occur; and a step of measuring a crystal defect of a lower layer after the step of removing the upper layer. 2. The method according to claim 1, wherein the semiconductor device has a desired element portion formed by an ion implantation method. 3. The method according to claim 1, wherein the step of removing the upper crystal defect layer is dry etching. 4. The method according to claim 1, wherein the step of removing the upper crystal defect layer includes etching by scanning a focused ion beam in a plane of the sample.
The method for measuring crystal defects according to the above. 5. A method for measuring a crystal defect in a lower layer, comprising:
The method according to any one of claims 1 to 4, wherein an etch pit generated by chemical etching is observed. 6. An etching operation is repeated on the same portion of the semiconductor substrate where the crystal defect layer is expected to be present, and each crystal in a layer having a different etching depth is obtained. 6. The method according to claim 1, wherein the defect layers are individually detected and evaluated.