JPH11121740A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decreases the number of processes for forming a source drain region and to form the source/drain region having the more shallow depth of junction in a method of manufacturing an insulated-gate field-effect transistor having an LDD (low doped drain) structure. SOLUTION: First insulating films 16a and 16b are formed on a semiconductor substrate 11, wherein a low-concentration source/drain region is to be formed. Semiconductor films 18a and 18d are formed on the semiconductor substrate 11 in the region, wherein the high-concentration source/drain is to be formed. Furthermore, impurities for supplying carriers are introduced into the semiconductor films 18a-18d by ion implantation and also introduced into the semiconductor substrate 11 through the first insulating films 16a and 16b and the semiconductor films 18a-18d. Then, heating is performed, and the impurities in the semiconductor films 18a-18d are diffused in the semiconductor substrate 11. At the same time, the impurities in the semiconductor films 18a-18d and the semiconductor substrate 11 are activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an LDD (Low Doped Drain).
A) a method of manufacturing an insulated gate field effect transistor having a structure;

[0002]

2. Description of the Related Art FIGS. 4 and 5 show a source / drain region (hereinafter referred to as an S / D region) of a CMOS (complementary insulated gate field effect transistor) comprising an n-channel MOS and a p-channel MOS. FIG. 7 is a cross-sectional view showing a conventional method of forming a single pixel on the same semiconductor substrate.

First, as shown in FIG. 4A, an insulating film 2 for element isolation is formed on a silicon substrate 1 by a LOCOS method. The formation region of the insulating film 2 becomes an element isolation region,
Both sides are element forming regions including an nMOS region and a pMOS region. Subsequently, a p-well 1 is placed on the nMOS region side.
Then, gate insulating films 3a and 3b and gate electrodes 4a and 4b are formed on the silicon substrate 1 in the nMOS region and the pMOS region, respectively.

Next, as shown in FIG. 4B, one side of the pMOS region is covered with a resist film 5a and a gate electrode 4a is formed.
Is used as a mask to ion-implant an n-type impurity at a low dose into the silicon substrate 1 in the nMOS region. Next, FIG.
After removing the resist film 5a, as shown in FIG.
The S region is covered with a resist film 5b, and a p-type impurity is ion-implanted at a low dose into the silicon substrate 1 in the pMOS region using the gate electrode 4b as a mask.

Next, after removing the resist film 5b,
The silicon substrate 1 is heated to activate the impurity ions to form low concentration source / drain regions 6a to 6d. After that, as shown in FIG. 4D, an insulating film 7 is formed. Next, as shown in FIG. 5A, the insulating film 7 is etched by anisotropic etching, and the gate electrodes 4a and 4b are etched.
Then, insulating films 7a and 7b are formed on the side wall of b.

[0006] Next, as shown in FIG.
The S region is covered with a resist film 5c, and n-type impurities are ion-implanted into the silicon substrate 1 at a high dose using the gate electrode 4a as a mask. Next, as shown in FIG. 5C, after removing the resist film 5c, the nMOS region is changed to the resist film 5c.
Then, ions are implanted into the silicon substrate 1 at a high dose with a p-type impurity using the gate electrode 4b as a mask.

Next, after removing the resist film 5d,
The silicon substrate 1 is heated to activate the impurity ions to form the high concentration source / drain regions 8a to 8d. As described above, a region near the gate electrodes 4a and 4b has a low concentration and a region far from the gate electrodes 4a and 4b has a high concentration, that is, an LDD.
S / D regions 9a to 9d having a structure are formed.

[0008]

By the way, in order to form the S / D regions 9a to 9d of the LDD structure, it is necessary to form low concentration diffusion regions 6a to 6d and high concentration diffusion regions 8a to 8d. . In the above-mentioned manufacturing method, since they are formed in separate steps, there is a problem that it takes time and effort.

In addition, as the size of the device is reduced, the junction depth of the S / D regions 9a to 9d tends to be reduced. However, in ion implantation, there is a limit that the dose amount and the acceleration voltage can be reduced, so that the pn can be formed shallowly.
There is also a limit to the depth of the junction, and it is no longer meeting recent requirements. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the related art, and it is possible to reduce the number of steps for forming a source / drain region and form a source / drain region having a smaller depth. It is intended to provide a method of manufacturing a semiconductor device which can be performed.

[0010]

The first object of the present invention is to provide a gate insulating film formed on a semiconductor substrate, a gate electrode thereon, and a semiconductor substrate formed on both sides of the gate electrode. An insulated gate field effect transistor having source / drain regions having a low concentration on a side near the gate electrode and a high concentration on a side far from the gate electrode is formed. In the method for manufacturing a semiconductor device, the low-concentration source /
Forming a first insulating film on the semiconductor substrate in a region where a drain region is to be formed, and forming a semiconductor film on the semiconductor substrate in a region where the high-concentration source / drain region is to be formed; And introducing an impurity for supplying carriers comprising electrons or holes into the semiconductor film by ion implantation into the semiconductor film, and introducing the impurities into the semiconductor substrate through the first insulating film and the semiconductor film. Performing a heat treatment to diffuse impurities in the semiconductor film into the semiconductor substrate, and activating the impurities in the semiconductor film and the semiconductor substrate. Forming a metal film over the entire surface after the step of performing the heat treatment to diffuse the impurities and activating the second invention, Performing a heat treatment to cause the semiconductor film and the metal film to react with each other to form a metal-semiconductor mixed layer on a surface layer of the semiconductor film; and removing the metal film, and forming the semiconductor film and the metal-semiconductor mixed layer. Forming a source / drain electrode made of silicon. The method of manufacturing a semiconductor device according to the first invention, wherein the material of the semiconductor substrate is silicon. Wherein the material of the gate electrode is polysilicon; the material of the semiconductor film is silicon; and the first insulating film is a silicon oxide film. The step of forming the first insulating film and the semiconductor film, which is solved by the method of manufacturing the device and is the fourth invention, comprises forming the gate insulating film on the semiconductor substrate and the gate electrode thereon. Forming a first insulating film on the surface of the semiconductor substrate other than the gate electrode forming region; forming a second insulating film on a side wall of the gate electrode to form the gate; Covering the first insulating film on the surface of the semiconductor substrate around the electrode;
Removing the portion of the first insulating film that is not covered with the second insulating film and exposing the semiconductor substrate; and selectively forming a semiconductor film on a surface of the semiconductor substrate exposed in a peripheral portion of the gate electrode. Forming a semiconductor device and removing the second insulating film from a side wall of the gate electrode. The semiconductor device manufacturing method according to any one of the first to third inventions, wherein According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth aspect, wherein the second insulating film is a silicon nitride film.

As described above, according to the present invention, after a first insulating film is formed on a semiconductor substrate, a second insulating film is formed on a side wall of a gate electrode, and the second insulating film is masked. In this method, the underlying first insulating film is etched, and a silicon film is selectively formed on the etched trace.
For this reason, it is possible to accurately secure a width corresponding to almost the thickness of the second insulating film from the end of the gate electrode as a region in which the low concentration diffusion region is to be formed, and to further extend the high concentration diffusion region outside the region. Can be secured with high accuracy.

In a state where a first insulating film is formed on a region where a low concentration diffusion region is to be formed, and a semiconductor film is formed on a region where a high concentration diffusion region is to be formed, the first insulating film is formed. And ion implantation through the semiconductor film. At this time,
Since the first insulating film and the semiconductor film are interposed, the impurity is introduced shallowly into the semiconductor substrate below the first insulating film and the semiconductor film.

[0013] Then, impurities are diffused from the semiconductor film into the semiconductor substrate by the subsequent heat treatment, so that a high concentration diffusion region is formed under the semiconductor film and the first region is formed.
Since the impurity is hardly diffused from the first insulating film into the semiconductor substrate under the insulating film, a low concentration diffusion region is formed. As described above, the source / drain regions having the LDD structure are formed at once in the semiconductor substrate on both sides of the gate electrode.

Therefore, the number of steps for forming the source / drain region having the LDD structure can be reduced, and the source / drain region having the LDD structure having a shallower junction depth can be formed. Furthermore, when a metal film is formed directly on a semiconductor substrate and subjected to a heat treatment, the metal may reach the pn junction of the source / drain region and cause a junction breakdown. However, in the present invention, the source / drain region has an LDD structure. A metal-semiconductor mixed layer is formed on the surface of the semiconductor film by forming a metal film on the entire surface except for the semiconductor film used for forming the drain region and heating the semiconductor film. For this reason, the distance from the surface to the pn junction of the source / drain region becomes longer by the thickness of the semiconductor film, so that the possibility that the metal reaches the pn junction of the source / drain region after heat treatment is reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A shows gate electrodes 14a and 1a.
It is sectional drawing which shows the state after forming 4b.

As shown in FIG. 1A, an LO is formed on an n-type silicon substrate 11 in a region to be an element isolation region.
The field insulating film 12 is formed by selective oxidation by the COS method. The periphery of the element isolation region is an element formation region where the silicon substrate 11 is exposed, and the element formation region is separated into an nMOS region and a pMOS region by the element isolation region. Subsequently, a p-well 11a is formed on the nMOS region side.

Next, after a silicon oxide film is formed by thermal oxidation, a polysilicon film and a silicon oxide film are formed thereon by a CVD method. Subsequently, these are patterned to form a gate insulating film 13a, a gate electrode 14a, and a protective insulating film 15a in an nMOS region, and a gate insulating film 13b, a gate electrode 14b, and a protective insulating film 15b in a pMOS region. At this time, the gate electrodes 14a, 1
Silicon is exposed on the side wall of 4b.

Next, as shown in FIG. 1B, the silicon substrate 11 is heated at 900 ° C. in an oxygen atmosphere, and a film is formed on the side walls of the gate electrodes 14a and 14b and the surface of the silicon substrate 11 by thermal oxidation. A silicon oxide film (first insulating film) 16 having a thickness of about 30 nm is formed. Next, FIG.
As shown in (1), a silicon nitride film (second insulating film) 17 having a thickness of about 150 nm is formed by the CVD method.

Next, as shown in FIG. 1D, the silicon nitride film 17 is etched by anisotropic etching using a fluorine-based reaction gas, and the silicon nitride films 17a and 17a are formed on the side walls of the gate electrodes 14a and 14b. Leave 17b. At this time, the silicon nitride films 17a and 17b are
The silicon oxide film 16 on one surface is formed on the gate electrodes 14a, 14
The end of b is covered with a width of about 150 nm corresponding to the thickness of the silicon nitride films 17a and 17b.

Subsequently, the silicon oxide film 16 not covered with the silicon nitride films 17a and 17b is etched.
As a result, the silicon oxide films 16a and 16b are left from the ends of the gate electrodes 14a and 14b with a width substantially equal to the thickness of the silicon nitride films 17a and 17b. Next, as shown in FIG. 2A, silicon films 18a to 18a having a thickness of about 50 nm are formed on the exposed silicon substrate 11 by epitaxial growth.
8d is selectively formed.

The epitaxial growth conditions are as follows.
You. That is, as a reaction gas, SiH_TwoCl _TwoAnd HCl, H_Twoof
Using a mixed gas, adjust the flow rate of each_TwoCl_Two700cc /
min, HCl 1000cc / min, H_Two300cc / min.
Next, as shown in FIG.
Silicon nitride films 17a, 17 on the side walls of poles 14a, 14b
b is removed.

Next, as shown in FIG.
The S region is covered with a resist film 19a. Subsequently, an n-type impurity, for example, As (arsenic) is introduced into the silicon substrate 11 in the nMOS region by ion implantation. The conditions for ion implantation are
The acceleration voltage is 40 keV and the dose is 1 × 10 ¹⁵ cm ⁻² . As a result, As is introduced into the silicon films 18a and 18b, and As is introduced into the silicon substrate 11 through the silicon films 18a and 18b and the silicon oxide film 16a. At this time, depending on the thickness difference between the silicon film 18a and the silicon oxide film 16a, the reaching depth of the impurities in the silicon substrate 11 thereunder also differs, but the silicon oxide film 16a and the silicon films 18a and 18b are interposed. Therefore, the silicon oxide film 16a and the silicon films 18a, 1
Impurities are introduced shallowly into silicon substrate 11 below 8b.

Next, as shown in FIG. 2D, after removing the resist film 19a, the other nMOS region is covered with a resist film 19b. Subsequently, a p-type impurity, for example, B (boron) is introduced into the silicon substrate 11 in the pMOS region by ion implantation of BF ₂ . The conditions for the ion implantation are an acceleration voltage of 40 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . As a result, B is introduced into the silicon films 18c and 18d, and B is introduced into the silicon substrate 11 through the silicon films 18c and 18d and the silicon oxide film 16b.
At this time, depending on the thickness difference between the silicon films 18c and 18d and the silicon oxide film 16b, the silicon substrate 11 thereunder is formed.
Although the depth at which the impurities reach the inside is different, the silicon oxide film 1
6b and the silicon films 18c and 18d, the silicon oxide film 16b and the silicon films 18c and 18d are interposed.
The impurity is introduced shallowly into the silicon substrate 11 below d.

Next, heat treatment is performed at a temperature of 850 ° C. for 40 minutes. As a result, as shown in FIG. 3A, impurities introduced by ion implantation diffuse from the silicon films 18a to 18d into the silicon substrate 11, so that the high-concentration diffusion regions 20a are formed under the silicon films 18a to 18d. ~ 2
0d is formed and the silicon oxide films 16a, 1
Below 6b, impurities are hardly diffused from the silicon oxide films 16a and 16b into the silicon substrate 11, so that low concentration diffusion regions 21a to 21d are formed. In this manner, n-type S / D regions 24a and 24b having the LDD structure are provided on both sides of gate electrode 14a in the nMOS region, and p-type S / Ds having the LDD structure are provided on both sides of gate electrode 14b in the pMOS region.
The regions 24c and 24d are respectively formed at a time.

Next, as shown in FIG. 3B, a metal film 25 made of titanium (Ti) having a film thickness of 25 nm is formed on the entire surface, and then subjected to a heat treatment as described below. As shown, silicide layers 25a to 25d are formed on the surface layers of the silicon films 18a to 18d. The heat treatment is performed by N
₂ at 650 ° C. for 1 minute, then NH ₄ OH + H ₂ O ₂ + H ₂ O
For 5 minutes and then in Ar at 800 ° C. for 1 minute.

At this time, when the metal film 25 is formed directly on the silicon substrate 11 and subjected to a heat treatment, the metal may reach the pn junction of the source / drain regions 24a to 24d, and the junction may be broken. In the embodiment, the metal film 25 is formed on the entire surface except for the silicon films 18a to 18d used for forming the source / drain regions 24a to 24d having the LDD structure, and the silicon film 1 is heated.
Silicide layers (metal-semiconductor mixed layers) 25a to 25d are formed on the surface layers of 8a to 18d. For this reason, the distance from the surface to the pn junction of the source / drain regions 24a to 24d is increased by the thickness of the silicon films 18a to 18d. Is unlikely to be reached.

Thereafter, a CMOS transistor is completed through predetermined steps. As described above, according to the embodiment of the present invention, as shown in FIGS. 1B to 2A, after the silicon oxide film 16 is formed on the silicon substrate 11, the gate electrodes 14a and 14b are formed. A silicon nitride film 17a on the side wall of
17b, and the silicon nitride films 17a, 1
7b as a mask, the underlying silicon oxide film 16 is etched, and the silicon films 18a-1
8d is selectively formed.

For this reason, the low concentration diffusion regions 21a to 21d
Can be accurately secured by the width of the silicon nitride films 17a and 17b from the end portions of the gate electrodes 14a and 14b as the region where the high concentration diffusion regions 20a to 20d are formed. Can be secured with high accuracy. Further, FIG.
As shown in (c) and (d), the low concentration diffusion region 21a
Silicon oxide films 16a, 16d,
In the state where the silicon films 18a to 18d are formed on the regions where the high concentration diffusion regions 20a to 20d are to be formed, ions are implanted through the silicon oxide films 16a and 16b and the silicon films 18a to 18d.

Thus, impurities can be introduced into the silicon substrate 11 at a shallow depth. Moreover, under the silicon films 18a to 18d, the high concentration diffusion regions 20a to 20d are formed.
d is formed and the silicon oxide films 16a, 16
Below b, low concentration diffusion regions 21a to 21d are formed. As described above, the S / D regions having the LDD structure are formed on the silicon substrate 11 on both sides of the gate electrodes 14a and 14b at a time.

Therefore, the number of steps for forming the S / D region having the LDD structure can be reduced, and the S / D regions 24a to 24d having a shallower junction depth can be formed.
Further, the metal film 25 is formed on the entire surface except for the silicon films 18a to 18d used for forming the S / D regions 24a to 24d having the LDD structure, and heated, so that silicide is formed on the surface of the silicon films 18a to 18d. Layers 25a-25
d, the metal becomes S
The possibility of reaching the pn junction of / D regions 24a to 24d is reduced. Thereby, pn junction destruction can be prevented.

In the above description, a CMOS is formed. However, by applying the above embodiment, it is also possible to form only an nMOS or only a pMOS.

[0032]

As described above, in the present invention, the first
After forming the insulating film on the semiconductor substrate, a second insulating film is formed on the side wall of the gate electrode, and further, the first insulating film as a base is etched and etched using the second insulating film as a mask. A silicon film is selectively formed on the mark.

Therefore, a region where a low concentration diffusion region is to be formed and a region where a high concentration diffusion region is to be formed can be secured with high accuracy. Further, the first insulating film is formed on the region where the low concentration diffusion region is to be formed, and the first insulating film is formed on the region where the high concentration diffusion region is to be formed.
Are implanted through the insulating film and the silicon film.

As a result, the impurity is introduced shallowly into the semiconductor substrate under the first insulating film and the silicon film, and the source / drain regions having the LDD structure are simultaneously formed in the semiconductor substrate on both sides of the gate electrode. You. Therefore, LD
The number of steps for forming a source / drain region having a D structure can be reduced, and a source / drain region having an LDD structure having a shallower junction depth can be formed.

Further, a metal film is formed on the entire surface except for the semiconductor film used for forming the source / drain regions having the LDD structure, and heated to form a metal-semiconductor mixed layer on the surface of the semiconductor film. Therefore, the possibility that the metal reaches the pn junction of the source / drain region when the heat treatment is performed is reduced. Thereby, pn junction destruction can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (part 1) illustrating a method for manufacturing a CMOS according to an embodiment of the present invention;

FIG. 2 is a sectional view (part 2) illustrating the method of manufacturing the CMOS according to the embodiment of the present invention;

FIG. 3 is a sectional view (part 3) illustrating the method of manufacturing the CMOS according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view (part 1) illustrating a method of manufacturing a CMOS according to a conventional example.

FIG. 5 is a sectional view (part 2) illustrating the method of manufacturing the CMOS according to the conventional example.

[Explanation of symbols]

 Reference Signs List 11 silicon substrate (semiconductor substrate), 12 field insulating film, 13a, 13b gate insulating film, 14a, 14b gate electrode, 15a, 15b protective insulating film, 16 silicon oxide film (first insulating film), 17 silicon nitride film ( 2nd insulating film), 18a-18d silicon film (semiconductor film), 19a, 19b resist film, 20a-20d high concentration diffusion region, 21a-21d low concentration diffusion region, 24a, 24b n-type S / D region, 24c, 24d p-type S / D region, 25 metal film, 25a to 25d silicide layer.

Claims (5)

[Claims] 1. A gate insulating film formed on a semiconductor substrate, a gate electrode on the gate insulating film, and source / drain regions formed on the semiconductor substrate on both sides of the gate electrode. A method of manufacturing an insulated gate field effect transistor having a source / drain region having a high concentration on a side far from the gate electrode, wherein the low concentration source / drain region Forming a first insulating film on a semiconductor substrate in a region where a high concentration source / drain region is to be formed, and forming a semiconductor film on a semiconductor substrate in a region where the high concentration source / drain region is to be formed; Impurities for supplying carriers comprising electrons or holes to the semiconductor film are introduced into the semiconductor film by ion implantation, and the first insulating film and the semiconductor Introducing a semiconductor film through the film into the semiconductor substrate; performing a heat treatment to diffuse the impurities in the semiconductor film into the semiconductor substrate; and activating the impurities in the semiconductor film and the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 2. The heat treatment is performed to diffuse impurities,
And a step of forming a metal film on the entire surface after the step of activating, and a step of performing a heat treatment to cause the semiconductor film and the metal film to react with each other to form a metal-semiconductor mixed layer on a surface layer of the semiconductor film. Forming a source / drain electrode composed of the semiconductor film and the metal-semiconductor mixed layer by removing the metal film. 3. The method according to claim 1, wherein a material of the semiconductor substrate is silicon, a material of the gate electrode is polysilicon, a material of the semiconductor film is silicon, and the first insulating film is a silicon oxide film. The method for manufacturing a semiconductor device according to claim 1, wherein the method comprises: 4. The step of forming the first insulating film and the semiconductor film, the step of forming the gate insulating film on the semiconductor substrate and the gate electrode thereon, and the formation region of the gate electrode. Forming the first insulating film on the surface of the semiconductor substrate other than the above, and forming a second insulating film on a side wall of the gate electrode to form a first insulating film on a surface of the semiconductor substrate around the gate electrode. A step of covering the film; a step of removing the portion of the first insulating film that is not covered with the second insulating film to expose the semiconductor substrate; and a surface of the semiconductor substrate exposed to a peripheral portion of the gate electrode. 4. The method according to claim 1, further comprising: selectively forming a semiconductor film; and removing the second insulating film from a side wall of the gate electrode.
The method for manufacturing a semiconductor device according to any one of the above. 5. The method according to claim 4, wherein the second insulating film is a silicon nitride film.