JPH11121686A - Method of assembling multilayered chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method, which efficiently executes the assembling work of a multilayered chip and minimizes the no. of chip units to be discarded due to connection defects. SOLUTION: This method of assembling a multilayered chip A having a laminated structure of plural laminated chip units 1-4 comprises a preceding step of combining the chip units 1-4 and conductivity jointing them between joint planes to form integrated composite chips A1, A2 and following the steps of combining and jointing the composite chips A1, A2 so as to form a laminated structure of the plural chip units 1-4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for assembling a multilayer chip having a structure in which a plurality of single chips are stacked in multiple stages.

[0002]

2. Description of the Related Art Conventionally, a semiconductor chip such as an IC or an LSI is generally mounted alone on a tape carrier or a resin substrate. As the mounting structure, there is a structure mounted by a tape automated bonding (TAB) method or a chip-on-board (COB) method, and an optimum structure is selected in consideration of various factors.

A semiconductor chip having such a mounting structure is assembled by a so-called chip-on-chip method (hereinafter, abbreviated as COC) in which another bare chip is stacked on the chip and joined. There is a laminated structure. According to such a laminated structure using COC, high density can be easily achieved.
It is conceivable that the laminated structure of the above is adopted for various types of devices such as small electronic devices, thin portable terminals, and IC cards.

Further, as a development of such a laminated structure based on COC, there has been proposed a multilayer chip having a multi-stage laminated structure by laminating three or more single chips. Since the lowermost chip of such a multilayer chip is usually bonded to a tape carrier or a resin substrate, the method of assembling a multilayer chip is to assemble the lowermost chip alone to the uppermost chip alone. It is considered to be a general method. In order to join the individual chips to each other in such an assembling method, an anisotropic conductive adhesive film (hereinafter abbreviated as A
CF) or anisotropic conductive adhesive paste is used as an adhesive medium, and conductive bonding is performed in a state where conductive bonding is performed via bumps on the bonding surface. There is also a form of bonding with a hydrophilic adhesive.

[0005]

However, in the above-mentioned conventional method of assembling a multilayer chip, when each single chip is joined from the lowermost layer to the uppermost layer, a conductive junction and a non-conductive connection are made between the joining surfaces. When such different types of joining steps are alternately repeated, the assembling workability is inefficient, resulting in a troublesome assembling work. In addition, when the bonding surfaces are bonded by non-conductive connection in the previous step, and another chip unit is conductively bonded to the chip complex integrated by the bonding, at least three chip units are multi-layered. Will be done. When a measurement test is performed on such a multi-layer stacked multilayer chip and a connection failure is determined, all chips constituting the multi-layer structure are regarded as defective and are discarded. Therefore, even chips that do not participate in the conductive bonding are discarded as defective products depending on the determination result of the connection quality, and there is a problem that chips constituting the multilayer chip are wasted.

Accordingly, the present invention was conceived in view of the above-mentioned circumstances, and it is possible to efficiently assemble a multi-layer chip and to reduce the number of chips to be discarded due to poor connection. It is an object of the present invention to provide a method for assembling a multi-layer chip capable of minimizing the number of chips.

[0007]

DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.

That is, the method for assembling a multi-layer chip provided by the present invention is a method for assembling a multi-layer chip having a structure in which a plurality of single chips are stacked in multiple stages. A step of combining and conducting conductive bonding of the chips connected in a conductive manner is a preceding step, and thereafter, by combining and bonding the respective chip composites integrated by conductive bonding, the plurality of chips are stacked in a multi-stage manner. It is characterized by:

In the method of assembling a multi-layer chip provided by the present invention in which the above-mentioned technical means have been taken, in the preceding step performed in advance, among the plurality of single chips necessary for the configuration of the multi-layer chip, the bonding surface between the bonding surfaces is determined. The chips that are conductively connected are combined and conductively joined. Each chip composite joined through such a conductive joining step has a structure in which a plurality of single chips are integrated. For example,
For each chip complex, the quality of the connection can be determined. If it is determined that the connection is defective, only a plurality of chips constituting the chip composite, that is, only chips involved in conductive bonding are discarded. Further, after the conductive bonding step, for example, the respective chip composites that have passed the determination of the connection quality are assembled and bonded to each other. As a result, all the necessary chips are stacked in multiple stages, and the assembly by joining the chips alone is completed.

Therefore, according to the method for assembling a multi-layer chip provided by the present invention, after performing a conductive bonding step in which the bonding surfaces are conductively connected, the chip composites integrated by the conductive bonding are bonded to each other. Therefore, since the same kind of bonding process is performed in a series of order such as a single chip, a chip composite, and a multilayer chip, the assembly operation of the multilayer chip can be efficiently performed. In addition, after the conductive bonding step, it is possible to determine whether the connection is good or defective with respect to the chip composite composed of a plurality of conductively bonded chips, so that even if the connection is determined to be defective at that time, only the conductive bonding is involved. Since the chip is discarded as a defective product, the number of chips to be discarded due to poor connection can be minimized without waste of the chips constituting the multilayer chip.

The chip may be a ROM or RAM having a memory function, or a CP having an operation / control function.
A semiconductor chip such as U is applicable, but is not particularly limited to a semiconductor chip having such a function, and may be a semiconductor chip having other functions or a semiconductor chip having various functions in combination. It goes without saying that it is good.

As a form of conductive bonding, an ACF is formed with bumps formed on the bonding surface of each chip unit facing each other.
It is preferable to press and bond anisotropic conductive adhesive paste between the bonding surfaces, but other bonding modes such as pin bonding or solder fusion may be used. Further, both or one of the chips may be conductively bonded in a wafer state. In this case, the chip composite in a conductively bonded state can be cut out by scribing the wafer itself.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIGS. 1 to 4 are process sectional views showing cross sections in respective steps in an embodiment of a method of assembling a multilayer chip according to the present invention. In particular, FIG. 2 shows a cross-sectional structure of the multilayer chip.

As shown in FIG. 4, a multilayer chip A assembled and completed according to the present embodiment is composed of four semiconductor bare chips 1 to 4 (hereinafter referred to as first to fourth chips) in multiple stages. It has a laminated structure of so-called COC. Such a multilayer chip A is finally mounted and joined to a tape carrier 5 made of a polyimide film or the like. Further, since each chip unit 1 to 4 is electrically connected to another chip unit or the lead terminal 5 a on the tape carrier 5, bumps 1 a to 4 serving as connection terminals are provided on one joint surface.
a is formed by an etching process or the like. The bonding surface on which such bumps 1a to 4a are formed is called a conductive bonding surface. On the other hand, the opposite surface of the conductive bonding surface is bonded without conducting to another chip alone, etc.,
It is called a simple joint surface.

The method of assembling the above-described multilayer chip A is as shown in FIG. 1 by combining the first and second chip units 1 and 2 and electrically connecting them to form an integrated first chip. In the first conductive bonding step for producing the composite A1, as shown in FIG. 2, the third and fourth chips 3 and 4 are combined in the same manner as in the first conductive bonding step. A second conductive bonding step for producing the composite A2, a simple bonding step for completing the multilayer chip A by bonding the first and second chip composites A1 and A2 without conducting each other as shown in FIG. ,and,
As shown in FIG. 4, it is schematically configured to include a wire bonding step of connecting predetermined terminals by wire bonding.

The details will be described in the order of each step.
In the first conductive bonding step shown in FIG. 1, the first chip unit 1 has its simple bonding surface adsorbed by the vacuum suction collet 6 and the conductive bonding surface is the conductive bonding surface of the second chip unit 2. They are aligned with their faces facing each other.
At this time, the predetermined bumps 1a and 2a on both bonding surfaces are aligned so as to face each other. In the vicinity of the center of the second chip unit 2, an ACF 7 a is preliminarily pressure-bonded in advance so as to cover the bump 2 a near the center. This ACF7a is thermosetting or thermoplastic,
Alternatively, a metal film is dispersed and mixed in an adhesive containing a resin of the mixed system as a base material to form a thin film. further,
The second chip unit 2 is placed on a transfer table or the like (not shown). From the state thus aligned, the first and second chips 1, 2
Are thermocompression-bonded in a state where the ACF 7a is sandwiched between the conductive bonding surfaces. As a result, the first and second chips 1 and 2 are integrated using the ACF 7a as an adhesive medium, and a first chip composite A1 having a laminated structure including the first and second chips 1 and 2 is manufactured. Is done. And the first
The ACF 7a sandwiched between the conductive bonding surfaces of the second chip units 1 and 2 has an electrical characteristic in the thickness direction between the conductive bonding surfaces, that is, the bumps 1a and 2a of the two chip units 1 and 2. It has conductivity only between the two, and maintains insulation in the horizontal direction with respect to the conductive joint surface. As a result, the first and second chips 1 and 2 are electrically connected between the conductive bonding surfaces via the bumps 1a and 2a.

Next, in a second conductive bonding step shown in FIG. 2, a second chip composite A2 is produced in the same manner as in the first conductive bonding step. In other words, the third chip unit 3 is aligned with the simple bonding surface being sucked by the vacuum suction collet 6, with the conductive bonding surface facing the conductive bonding surface of the fourth chip unit 4. At this time, the predetermined bumps 3a, 4a on both bonding surfaces are aligned so as to face each other, and are positioned near the center of the fourth chip unit 4 in such a manner as to cover the bump 4a near the center. ACF7b is preliminarily crimped in advance.
The ACF 7b is similar to the ACF 7a used in the first conductive bonding step. The fourth chip 4 is placed on a transfer table (not shown) or the like. From the aligned state, the third and fourth chips 3 and 4 are thermocompression-bonded with the ACF 7b sandwiched between the conductive bonding surfaces. Thus, the third and fourth chips 3 and 4 are integrated with the ACF 7b as an adhesive medium, and the third and fourth chips 3 and 4 are integrated.
And a second laminated structure composed of the fourth chip units 3 and 4
Is prepared. As a result, the third and fourth chips 3 and 4 are in a state of being conductively connected between the conductive bonding surfaces via the bumps 3a and 4a.

The first and second chip composites A1 and A2 manufactured through the first and second conductive bonding steps are manufactured.
Regarding A2, before and after the simple bonding step, which is the next step, a connection inspection for quality of connection is individually performed. Since this judgment inspection is performed using a conventionally known connection inspection device, it is not particularly shown. If any of the chip composites A1 and A2 is determined to be poorly connected by this determination test, the corresponding chip composites A1 and A2 are discarded prior to the next simple joining step. Thereby, when only the chip involved in the conductive bonding, for example, only the first chip composite A1 is determined to be defective, only the first and second chips 1 and 2 are discarded, and the other first and second chips are discarded. The second chip complex A2 proceeds to the next process as it is.

Then, the first and second chip composites A1 and A2, both of which have passed the determination of the connection quality, are further joined to the simple joining step shown in FIG. In the simple bonding step, the first chip composite A1 is in a state where the simple bonding surface of the first chip unit 1 integrated with the upper part is sucked by the vacuum suction collet 6. Then, the simple bonding surface of the second chip unit 2 integrated in the lower part of the first chip composite A1 is aligned with the posture facing the second chip composite A2. At this time, the first and second chip composites A1, A2
Are positioned so that they face each other. However, since the two simple bonding surfaces are not electrically connected, the positioning accuracy is not required to be higher than that of the above-described conductive bonding. The second chip composite A2 is placed on a transfer table (not shown) or the like. Further, the first chip complex A1 is
In 2, the alignment is performed with respect to the simple bonding surface of the third chip unit 3 integrated in the upper part. afterwards,
From the aligned state, the first and second chip composites A1 and A2 are joined with a non-conductive adhesive (not shown) sandwiched between their simple joining surfaces. As a result, all the required chips 1 to 4 are stacked in a multi-stage manner, and the multilayer chip A is completed.

Finally, in the wire bonding step shown in FIG. 4, the multilayer chip A is electrically connected to the lead terminals 5a of the tape carrier 5 via the wires 8 while being mounted and joined on the tape carrier 5. Is done. That is, the bumps which did not participate in the conductive bonding in the previous conductive bonding step, and in the state shown in FIG.
The bumps 4a formed near the ends on the conductive bonding surface are connected to the lead terminals 5a via the wires 8. As a result, the second chip composite A2 is connected to the wire 8
And a state in which it is electrically connected to the outside of the chip via the lead terminal 5a. Further, the first chip composite A1 in the multilayer chip A is not conductively connected to the outside of the chip by itself, and is therefore conductively connected to the second chip composite A2 via the wire 9. That is, the bump which did not participate in the conductive bonding in the previous conductive bonding step, the bump 2a formed near the end on the conductive bonding surface of the second chip unit 2 in the state shown in FIG. The bump 4 a is the same as the single unit 4, but is connected to a bump (not shown) at another position via a wire 9. As a result, the first chip complex A1 is electrically connected to the outside of the chip via the internal circuit of the second chip complex A2.

Next, the main points in the method for assembling the multilayer chip A having the above configuration will be described with reference to the drawings.

As shown in FIGS. 1 and 2, when completing the multi-layer chip A, as a preceding step performed earlier,
There are first and second conductive bonding steps, and these steps enable four single chips 1 required for the configuration of the multilayer chip A.
4, the set of the first and second chip units 1 and 2 and the set of the third and fourth chip units 3 and 4 whose conductive bonding surfaces are conductively joined to each other are individually conductively joined. .

Thus, for the first and second chip composites A1 and A2 obtained by the conductive bonding, the quality of the connection can be determined before the simple bonding step shown in FIG. When the connection is determined to be defective by such a determination, if the plurality of chips constituting the chip composite, for example, the first chip composite A1 is defective, the first
And only the second chips 1 and 2 are discarded.

Further, after the conductive bonding step, the chip composites A1 and A2 that have passed the judgment of the connection quality are assembled and bonded to each other. As a result, all the required four chips 1 to 4 are stacked in a multi-stage,
Then, the assembly by joining the fourth chips 1 to 4 is completed.

Therefore, according to the method of assembling the multilayer chip A according to the present embodiment, after performing the conductive bonding step in which the conductive bonding surfaces are conductively connected, the first and second integrated by the conductive bonding are performed. Since the chip composites A1 and A2 are bonded to each other, the same type of bonding process is performed in a series of the order of the chips 1 to 4, the chip composites A1 and A2, and the multilayer chip A, so that the multilayer chip A is assembled. Work can proceed efficiently.

In addition, after the conductive bonding step, the quality of the connection can be determined individually for the chip composites A1 and A2 composed of two conductively bonded single chips, so that it is temporarily determined that the connection is defective. Even though the chip is involved only in the conductive bonding, it is discarded as a defective product, so that the chip constituting the multilayer chip A is not wasted and the number of chips to be discarded due to poor connection is minimized. Can be stopped.

In this embodiment, the multilayer chip A is composed of four single chips 1 to 4. However, the number of chips is not particularly limited to four, and the multilayer chip is composed of at least three or more single chips. Anything should do.

In the simple joining step, the upper and lower chips are joined to each other without conducting connection. However, when the upper and lower chips have the same substrate potential,
It may be in a state where the bonding surfaces of the substrates are electrically connected to each other.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a cross section in a first conductive bonding step in an embodiment of a method of assembling a multilayer chip according to the present invention.

FIG. 2 is a process cross-sectional view showing a cross section in a second conductive bonding step following the step shown in FIG. 1;

FIG. 3 is a process cross-sectional view showing a cross section in a simple connection step following the step shown in FIG. 2;

FIG. 4 is a process cross-sectional view showing a cross section in a wire bonding step following the step shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st chip single unit 2 2nd chip single unit 3 3rd chip single unit 4 4th chip single unit 1a-4a Bump 7a, 7b Anisotropic conductive adhesive film (ACF) 8,9 wire

Claims (1)

[Claims] 1. A method for assembling a multi-layer chip having a structure in which a plurality of single chips are stacked in a multi-stage manner, wherein the plurality of single chips are connected and electrically conductively connected between bonding surfaces. A method for assembling a multi-layer chip, wherein a plurality of single chips are stacked in a multi-stage manner by combining a plurality of chip composites integrated by conductive bonding and then bonding them, with a step as a preceding step.