JPH11103570A - Semiconductor drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent switching loss from increasing due to DC short circuit or malfunction by providing a control signal latch circuit which keeps on-state for a predetermined interval immediately after transition of a control signal from ON to OFF and keeps off-state for a predetermined interval immediately after transition from OFF to ON. SOLUTION: Upon detection operation of any one of ON signal detecting section 41 or OFF signal detecting section 42, a signal latch section 43 latches the signal from a control signal isolating section 1 for a predetermined interval immediately after detection and holds a drive section 2 in a state of having performed the detection operation. The signal is unlatched upon elapsing a predetermined time. The drive section 2 drives an IGBT 3 while neglecting the signals outputted at irregular timing from a control circuit among ON and OFF signals outputted from the control signal isolating section 1. According to the arrangement, switching loss due to DC short circuit or malfunction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor driving circuit.

[0002]

2. Description of the Related Art In recent years, the development of power semiconductors has been actively promoted, and power conversion technology has been applied in various fields such as home electric appliances, industrial electric appliances, railway electric appliances and the like. In order to control a power semiconductor typified by a bipolar transistor, a MOSFET, and an IGBT, a control circuit that controls the entire power conversion circuit and a drive circuit that matches the characteristics of each semiconductor are required. Bipolar transistors apply a current signal to the base, and MOSFET, IGBT
Can be driven by applying a voltage signal to the gate.

FIG. 4 is a block diagram of a conventional semiconductor drive circuit 10 for driving a power semiconductor and a circuit using a power semiconductor IGBT 3. The semiconductor drive circuit 10 receives a control signal DR from a control circuit (not shown), insulates and outputs a control signal isolator 1, receives the insulated control signal, amplifies and outputs a drive signal to the IGBT 3 The driving unit 2 is configured as follows. FIG.
Shows one phase of an inverter as an example of a power conversion circuit. An IGBT 3P and an IGBT 3N are connected in series, both ends of which are connected to a DC power supply 12,
AC power is supplied to the load from a series connection point of T3P and IGBT3N. A diode 11P and a diode 11N are connected to each IGBT in anti-parallel. The gates of the IGBT 3P and IGBT 3N have a semiconductor drive circuit 10 corresponding to the semiconductor drive circuit 10 of FIG.
P and the semiconductor drive circuit 10N are connected to each other, and controlled by control signals DRP and DRN from the control circuit 13 to perform power conversion. Since the method of controlling the inverter circuit is a known technique, the description is omitted here.

In the case of a voltage type inverter, each IGB shown in FIG.
If both T are simultaneously turned on, a DC short circuit occurs and a short-circuit overcurrent flows from the DC power supply. Therefore, in the control circuit 13, IGBT3P to IGBT3
When changing the N or the IGBT to be conducted from the IGBT 3N to the IGBT 3P, it is a general control signal output method to change the IGBT through a mode in which both IGBTs are temporarily turned off. The time during which both are temporarily turned off is generally called dead time.

FIG. 6 shows waveform examples of the control signals DRP and DRN. When the control signal DRP is "H", the IGPT 3P is turned on, and when the control signal DRP is "L", the IGPT 3P is turned off. Similarly, when the control signal DRN is “H”, the IGPT
3N is turned on, and the IGPT 3N is turned off in the “L” state. Here, T indicates a cycle of one cycle of the inverter operation, and DT indicates a dead time. Control signal DRP
FIG. 7 shows an example of a change in the emitter-collector voltage across the IGBT when the control signal DRN changes from "L" to "H" after the dead time DT time elapses from "H" to "L". IGBT when the control signal DRN changes from "H" to "L" and the control signal DRP changes from "L" to "H" after the time set as the dead time elapses
FIG. 8 shows an example of a change in the emitter-collector voltage at both ends.

FIG. 7 shows the timing when the IGBT 3N changes from off to on after the IGBT 3P changes from on to off. V3P is the emitter-collector voltage of the IGBT 3P, and V3N is the emitter-collector voltage of the IGBT 3N. is there. FIG. 8 is the reverse of FIG.
This is the timing when the IGBT 3P changes from off to on after 3N changes from on to off. FIG.
8 and IGBT output from control circuit 13 in FIG.
The control signal DRP on the 3P side is as shown by the solid line in the figure. The portion indicated by the dashed line will be described later.

FIG. 7 shows a case where the IGBT 3P is turned off while a current is flowing through the diode 11P. IGB with current flowing through diode 11P
Since the current path does not change even if T3P is turned off, the emitter-collector voltage does not change at this timing and the emitter-collector voltage changes when the next IGBT 3N turns on at this timing. FIG. 8 shows a diode 11N
Shows a case where the IGBT 3N is turned off while a current is flowing through the IGBT 3N. Even if the IGBT 3N is turned off while a current is flowing through the diode 11N, no change in the current path occurs. Therefore, no change in the emitter-collector voltage occurs at this timing, and a change in the emitter-collector voltage occurs when the next IGBT 3P is turned on. Occurs.

[0008]

When a control signal as shown in FIG. 7 is transmitted to a circuit for one phase of the inverter shown in FIG. 5, the potential of the IGBT 3P fluctuates due to a change in the emitter-collector voltage. . That is, when the IGBT 3P is turned off and the IGBT 3N is turned on, the IGBT 3P is turned off.
Of the DC power supply changes from the positive side to the negative side of the DC power supply. In the case of FIG. 8, the IGBT 3N is turned off,
When the IGBT 3P is turned on, the potential on the emitter side of the IGBT 3P changes from the negative side of the DC power supply to the positive side. The ground of the drive circuit 10P of the IGBT 3P is IG
It is connected to the emitter side of the BT3P, and drives the gate based on the emitter. Therefore, when the potential of the IGBT itself changes, the potential of the drive circuit naturally changes. On the other hand, the potential of the control circuit 13 is at a potential insulated from the IGBT, and the potential of the control circuit does not fluctuate even if the potential of the IGBT 3P fluctuates. Therefore IGBT3
The portion affected by the potential change in P becomes the control signal insulating portion 1 in the semiconductor drive circuit.

Generally, the actual configuration of the control signal insulating unit 1 is configured using a photocoupler, a pulse transformer, an optical connector and the like. In particular, the photocoupler is small, inexpensive, and can be controlled only by passing a small current to the primary-side diode. However, when the photocoupler is used for the control signal isolator 1 in the drive circuit of the IGBT 3P, the aforementioned IGBT 3P
Malfunction may occur when the potential fluctuation occurs. An example of the malfunction is indicated by a dashed line in the P-side gate signals in FIGS.

In the case of FIG. 7, the control circuit 13 is an IGBT 3P
The IGBT 3P has a photocoupler malfunction while the emitter potential of the IGBT 3P changes from the positive side to the negative side while the emitter potential of the IGBT 3P changes from the positive side to the negative side even though the "L" signal is kept being output to keep the IGBT in the OFF state. A signal for turning on the IGBT is transmitted to the semiconductor drive circuit 10P regardless of the control signal.
When the IGBT 3N is turned on, the IGBT 3P is turned on regardless of the control signal.
Both IGBTs of T3N are turned on, resulting in a DC short circuit.

When a DC short circuit occurs, an overcurrent flows from the DC power supply. When the overcurrent flows, the malfunction of the photocoupler ends and the IGBT 3P is turned off again, so that the overcurrent is cut off. Since the overcurrent is suddenly cut off, an excessive back electromotive force is generated due to the inductance in the circuit, and the voltage exceeds the withstand voltage of the IGBT 3P, so that the IGBT 3P is broken. If the IGBT 3P is broken, not only will the inverter itself not function, of course, but also damage the load side or the power supply side. When an overcurrent of the IGBT is detected inside the control circuit 13 or the semiconductor drive circuit 10 and an overcurrent state occurs, the configuration is such that protection at the time of overcurrent can be performed by reducing the cutoff speed of the IGBT. However, the short-circuiting and the breaking operation for a short time due to the malfunction of the photocoupler as described above cannot be usually dealt with and cannot be protected.

FIG. 8 shows an operation in which the IGBT 3P is turned on while the IGBT 3N is turned off. Daio
Since the IGBT 3P is turned on while the current is flowing through the node 11N, the current of the diode 11N is commutated to the IGBT 3P. The switching loss occurs because the IGBT 3P is turned off and turned on again by the malfunction of the photocoupler in a state where the current flows in the IGBT 3P.
Since power semiconductors generate heat due to loss, they are usually
Use while cooling with Tosink. However, the switching loss due to the malfunction of the photocoupler is not usually considered in the cooling design using the heat sink. Therefore, when a loss that is not included in such a cooling design occurs, heat is generated that exceeds the cooling performance of the heat sink.
If the temperature exceeds the allowable junction temperature of the BT, the IGBT will be destroyed.

[0013]

In order to prevent such a problem, a control signal for instructing ON / OFF of a power semiconductor is input, and a control signal insulator for insulated output is provided. A drive unit provided between power semiconductors, for outputting the power semiconductor drive signal in accordance with the control signal insulating unit output, in a semiconductor drive circuit comprising the above, control for instructing on / off of the power semiconductor A control signal latch circuit is provided which holds the on state for a predetermined period from the moment when the signal changes from on to off and holds the off state for a predetermined period from the moment when the signal changes from off to on.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 6, once the input DRP of the control signal isolator is turned on, the on state continues for a (T-DT) period, during which the IGBT 3P is to be kept on. Once the DRP is turned off (T +
The off state continues for a DT) period, during which the IGBT 3P is to be kept off. Therefore, immediately after the ON signal or the OFF signal is transmitted to the semiconductor drive circuit, the control signal is output from the control signal insulating unit 1 for a period during which the control circuit does not output the ON signal or the OFF signal for the next switching. Even if the signal is temporarily cut and the control signal isolator outputs a signal for switching during the period when the ON signal or the OFF signal should not be output, the ON signal is ignored as a malfunction and the drive is ignored. The output of the unit 2 should not be changed. The above explanation is DRP
Although the case of the signal has been described, the same applies to the case of the DRN signal.

As described above, cooling by a heat sink is used for a power semiconductor, and a switching frequency must be determined in order to design cooling performance. When the switching frequency is determined, a minimum ON period and a minimum OFF period are set. During the minimum on-period and the minimum off-period, no signal for the next switching is output from the control circuit 13. Further, the control circuit 13
In the case of digital control using a PU or the like, a cycle time for calculation is required, and the next switching signal is not output during the cycle time.

The switching signal output from the control signal isolator during these periods is ignored as a malfunction, and the output of the driver 2 is not changed. The drive unit 2 drives the IGBT 3 ignoring only the ON signal and the OFF signal output from the control signal insulating unit 1 at timings that should not normally be output from the control circuit. It is possible to prevent an increase in junction temperature due to switching loss due to malfunction.

[0017]

FIG. 1 shows an embodiment of the present invention.
In the semiconductor driving circuit of FIG.
The control signal latch circuit 4 including an off signal detection unit 42 and a signal latch unit 43 is provided. Once either the ON signal detection unit 41 or the OFF signal detection unit 42 performs the detection operation, the signal from the control signal insulation unit 1 is latched in the signal latch unit 43 for a certain period from the moment of detection, The drive unit 2 operates to hold the state at the time of performing the detection operation. Here, the certain period refers to a period twice as long as the dead time, or a minimum on-period and a minimum off-period, or a period based on a cycle time for CPU operation. After the elapse of the certain period, the signal latch unit 43 releases the latch of the signal, and the ON signal detecting unit 41 and the OFF signal detecting unit 42 operate to receive the signal from the control signal insulating unit 1.

FIG. 2 shows an example of a specific configuration of the control signal latch circuit 4 of FIG. FIG. 3 is an operation time chart of the circuit of FIG. The control signal insulator 1 is a photocoupler 10
1 and a resistor 102, and 2 of the photocoupler 101
The next side is pulled up by a resistor 102. When a current flows through the diode on the primary side of the photocoupler 101, it is regarded as an ON signal. The symbols in FIGS. 2 and 3 correspond to each other, and the output signal of the photocoupler 101 is a voltage signal.
01 is set. Since only CONT is a current signal, IC
ONT. In the V101 time chart, a signal due to a malfunction not found in ICON is superimposed. The ON signal detection unit 41 and the OFF signal detection unit 42 have similar configurations, and the OFF signal detection unit 42
Since the inverters 411 and 418 are merely added to the input and output of the circuit, the detection operation of the off signal detector 42 will be described.

When the off signal is transmitted from the control circuit, the output of the photocoupler 101 changes from "L" to "H" and the OR
It is transmitted to the gate 422. Here, AND gate 426
Since the output of the OR gate 422 and its inverted output are input, when the output of the photocoupler 101 is "L", the steady output is "L". Therefore OR gate 42
2 also changes from “L” to “H”. Inverter gate 423, resistor 424, capacitor 425, AND4
Reference numeral 26 denotes a differentiating circuit using an integrating circuit of a resistor 424 and a capacitor 425. The output of the OR gate 422 is "L".
When the signal changes from “H” to “H”, a positive pulse is output.
By adjusting the time constants of the resistor 424 and the capacitor 425, the output time of the pulse of the AND gate 426 can be set to a desired time. Further, the off signal detecting section 42
Is self-held by the output of the AND 426, the output of the control signal isolator 23 during the operation of the differentiating circuit is not affected. The diode 42
Numeral 7 is for speeding up the reset operation of the integration circuit.

As described above, the ON signal detecting section 41 supplies the input and output of the OFF signal detecting section 42 with an inverter 411,
Since only 418 is added, a negative pulse is output when the output of the photocoupler 101 changes from “H” to “L”. In the signal latch unit 43, the AND gate 432 is provided immediately after the ON operation during a period in which a signal transmitted directly from the photocoupler 101 may malfunction due to a potential change.
Immediately after the OFF operation, the mask operation is performed by the OR gate 431, and the drive unit 2 operates to cut the malfunction signal.

[0021]

By using the semiconductor drive circuit having the configuration of FIG. 1 according to the present invention, the potential of the IGBT 3P fluctuates due to the change in the emitter-collector voltage of the IGBT 3N due to the timing in FIGS. Causes a malfunction and outputs an erroneous signal, the signal is not transmitted to the drive unit 2 and the operation of the drive unit 2 is the same as the output control signal of the control circuit. Therefore, a DC short-circuit caused when the IGBT 3P and the IGBT 3N are simultaneously turned on. It is possible to prevent an increase in switching loss due to a state or malfunction. In this description, I
Although the description has been given of a circuit example in which two GBTs are connected in series, it is needless to say that the same effect can be obtained in a multi-series circuit of two or more. Although a drive circuit for an IGBT is taken as an example of a power semiconductor, the present invention is naturally effective for a semiconductor drive circuit for driving other power semiconductors.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor drive circuit according to the present invention.

FIG. 2 is an embodiment of a signal latch circuit according to the present invention.

FIG. 3 is a time chart of the signal latch circuit according to the present invention.

FIG. 4 is a block diagram of a conventional semiconductor drive circuit.

FIG. 5 is a configuration example of one phase of an inverter circuit.

FIG. 6 is an explanation of dead time.

FIG. 7 is an example of an operation waveform of an inverter.

FIG. 8 is another example of the operation waveform of the inverter.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 control signal insulating unit 10 semiconductor drive circuit 11 diode 12 DC power supply 13 control circuit 101 photocoupler 102 resistor 2 drive unit 3 IGBT 4 control signal latch circuit 41 on signal detection unit 42 off signal detection unit 43 signal latch unit 411 invar -Target 412 OR gate 416 AND gate CONT Control signal DR Control signal V3P Emitter-collector voltage

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 17/78 H03K 17/78 K // H02M 3/00 H02M 3/00 S

Claims (1)

[Claims] 1. A control signal isolator for receiving a control signal for instructing on / off of a power semiconductor as an input and insulating and outputting the control signal.
A driving unit provided between the control signal insulating unit and the power semiconductor, and configured to output the power semiconductor drive signal in accordance with the output of the control signal insulating unit; A control signal latch circuit that holds the off state for a predetermined period from the moment the control signal for commanding the off state changes from on to off and holds the on state for a predetermined period from the moment the control signal changes from off to on; Characteristic semiconductor drive circuit.