JPH11103076A - Manufacture of semiconductor acceleration sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor acceleration sensor in which yield and productivity can be improved. SOLUTION: A P<+> type buried sacrificing layer 3a is formed on one surface side specified position of a single crystal silicon substrate 1, an N-type epitaxial layer 4 is formed on the surface side on which the P<+> type buried sacrificing layer 3a is formed, and a piezo-resistor 5 and a diffusion wiring 6 are formed in the epitaxial layer 4. A notched part 10 up to the P<+> type buried sacrificing layer 3a is formed by anisotropical etching, a metal wiring 11 and an electrode pad are formed so as to be electrically connected with the diffusion wiring 6, and a wiring protecting film 12 is formed on one main surface side of the single crystal silicon substrate 1. An etchant introducing port up to the P<+> type buried sacrificing layer 3a is formed, etchant is introduced, the P<+> type buried sacrificing layer 3a is eliminated by etching, and a frame 14, a deflecting part 15, a weight part 16 and a retaining member 17 are formed. A part of the epitaxial layer 4 is eliminated by etching, a slit 13 is formed, and the wiring protecting film 12 and a protecting film 8 on the single crystal silicon substrate 1 are eliminated by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an automobile, an aircraft,
The present invention relates to a method for manufacturing a semiconductor acceleration sensor used for home electric appliances and the like.

[0002]

2. Description of the Related Art In general, a cantilever type and a doubly supported type have been proposed as acceleration sensors. As a detection method, there are a method of detecting mechanical strain as a change in electric resistance and a method of detecting a change in capacitance. For example, Japanese Patent Application Laid-Open No. 6-109755 discloses a doubly-supported acceleration sensor that detects mechanical strain as a change in electric resistance.
No. 100782.

FIG. 13 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to a conventional example, and FIG. 14 is a schematic plan view showing a state of the semiconductor acceleration sensor shown in the upper figure as viewed from above. First, a silicon oxide film 2 is formed on an n-type single crystal silicon substrate 1 by thermal oxidation or the like, and the silicon oxide film 2 is etched using a photoresist (not shown) patterned in a predetermined shape as a mask. Thus, an opening 2a is formed, and the photoresist is removed by plasma ashing or the like. At this time, the opening 2a is formed at a location surrounding the substantially square central portion 1a of the single crystal silicon substrate 1.

Subsequently, using the silicon oxide film 2 in which the opening 2a is formed as a mask, p-type impurities such as boron (B) are deposited and subjected to thermal diffusion or ion implantation and annealing to thereby sacrifice the p + type burying. A layer 3a is formed (FIG. 13A), and the silicon oxide film 2 is removed by etching.

Next, an n-type epitaxial layer 4 is formed on the surface of the single crystal silicon substrate 1 on which the p + type buried sacrificial layer 3a is formed.
Is formed and p-type impurities such as boron (B) are deposited and thermally diffused or ion-implanted and annealed by using a photoresist (not shown) as a mask.
A p + type impurity layer 33 reaching the + type buried sacrificial layer 3a is formed, and the photoresist is removed (FIG. 13B). Here, the epitaxial layer 4 is formed to have a thickness that bends when an acceleration is applied, because the epitaxial layer 4 later becomes the bent portion 15.

Next, a piezo resistor 5 is formed by diffusing a p-type impurity such as boron (B) in a portion corresponding to the bent portion 15 of the epitaxial layer 4 (FIG. 13C). A diffusion wiring 6 is formed by diffusing a p-type impurity such as boron (B) into the epitaxial layer 4 so as to be electrically connected, and is formed on the single crystal silicon substrate 1 and the epitaxial layer 4.
A silicon oxide film 7 is formed thereon (FIG. 13D).

Next, a protective film 8 such as a silicon nitride film is formed on the silicon oxide film 7 by a CVD method or the like, and a photoresist (not shown) patterned in a predetermined shape is used as a mask. By etching the protective film 8, an opening 9 is formed at a position corresponding to the outer peripheral edge of the weight 16 described later, and the photoresist is removed (FIG. 13E).

Next, the silicon oxide film 7 in which the opening 9 is formed
By using the protective film 8 as a mask and performing anisotropic etching of the single crystal silicon substrate 1 using an alkaline etchant such as a potassium hydroxide (KOH) solution, the notch reaching the p + type buried sacrificial layer 3a The part 10 is formed (FIG. 13F).

Next, the silicon oxide film 7 / protective film 8 at a desired location on the diffusion wiring 6 is removed by etching, and the metal wiring 11 is formed by sputtering or vapor deposition so as to be electrically connected to the diffusion wiring 6. Then, an electrode pad (not shown) is formed (FIG. 13G).

Next, an etchant made of an acidic solution containing hydrofluoric acid or the like is introduced into the cut portion 10, and the p + type buried sacrificial layer 3a and the p + type impurity layer 33 are removed by isotropic etching. Frame 1 of epitaxial layer 4
3 to form a flexure 15 to which the neck 16a of the weight 16 is connected. Then, as shown in FIG. 14, a slit 13 that partially divides the bending portion 15 so that the bending of the bending portion 15 is concentrated is formed by RIE (Reactive Ion Etc).
By forming the protective film 8, the silicon oxide film 7, and the epitaxial layer 4 by the hing) or the like, the beam 15b is formed in the bending portion 15 (FIG. 13H).

Finally, after the protective film 8 on the single crystal silicon substrate 1 is removed by etching, a lower stopper 18 having a concave portion 18a at a position corresponding to the weight portion 16 is bonded by anodic bonding or the like (FIG. 13 (i)). ).

In this semiconductor acceleration sensor, when acceleration is applied to the weight portion 16, the weight portion 16 is displaced in a direction opposite to the direction in which the acceleration is applied, and the bending portion 15 is bent, and the bending portion 1 is bent.
The piezoresistor 5 formed on one surface of the deflecting member 5 is bent, and the resistance value of the piezoresistor 5 changes. The change in the resistance value is converted into an electric signal to detect the acceleration.

[0013]

However, in the method of manufacturing a semiconductor acceleration sensor having the above-described structure, the time required for etching when removing the p + type buried sacrificial layer 3a and the p + type impurity layer 33 by etching is reduced. If it gets too long,
There has been a problem that the metal wiring 11 is corroded by the etchant, and a defect such as disconnection occurs.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor acceleration sensor capable of improving yield and productivity.

[0015]

According to the first aspect of the present invention,
Forming, on one main surface of the semiconductor substrate having one main surface and two main surfaces, a sacrificial layer extending outwardly from an outer edge of at least a portion of a central portion of the semiconductor substrate; and A step of forming an epitaxial layer with a thickness corresponding to a bending portion that bends when an acceleration is applied, and a step of forming an acceleration detecting portion for detecting acceleration applied to the bending portion at a predetermined position of the epitaxial layer Forming a metal wiring and an electrode pad for extracting a signal from an acceleration detection unit, and anisotropically etching the semiconductor substrate at a portion corresponding to an outer peripheral edge of a weight unit that bends the bending unit when acceleration is applied, Forming a notch reaching the sacrificial layer; removing the sacrificial layer by isotropic etching to form a flexure comprising the epitaxial layer; In the method of manufacturing a semiconductor acceleration sensor having a weight portion formed, a wiring protective film is formed so as to cover the acceleration detecting portion, the metal wiring, and the electrode pad before the sacrificial layer is removed by etching. It is assumed that.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to the first aspect, a piezoresistor whose resistance value changes due to bending is formed as a part of the acceleration detecting portion corresponding to the bending portion. Then, the acceleration is detected by converting a change in the resistance value of the piezoresistor into an electric signal.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to the first aspect, the acceleration detecting portion is substantially opposed to the bending portion and / or the weight portion on the side of the epitaxial layer forming surface. An electrode is provided, and the acceleration is detected by detecting the deflection of the bending portion and / or the weight portion during acceleration application as a change in capacitance by the electrode.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to third aspects, a high-concentration impurity layer is formed as the sacrificial layer. It is assumed that.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to third aspects, a porous silicon layer is formed as the sacrificial layer. It is assumed that.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to fifth aspects, a chromium film is used as the wiring protection film. is there.

According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to any one of the first to fifth aspects, a fluorine resin is used as the wiring protective film. is there.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to fifth aspects, a silicon nitride film is used as the wiring protection film. It is.

According to a ninth aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to the eighth aspect, the silicon nitride film is formed at a low temperature of 300 ° C. or less by using a plasma CVD method. It is a feature.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to second aspects or the fourth to ninth aspects, it is preferable that the sacrificial layer is removed by etching. Only the wiring protection film on the electrode pad is thinned by pattern etching to a desired thickness. After the sacrificial layer is removed by etching, the wiring protection film is entirely etched to expose only the electrode pad. It is characterized by having made it.

According to an eleventh aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to any one of the first to tenth aspects, the etching of the cut portion is stopped before reaching the sacrificial layer. After leaving the semiconductor substrate slightly below the sacrifice layer, forming an etchant introduction port reaching the sacrifice layer in the wiring protective film and the epitaxial layer, introducing the etchant from the etchant introduction port, and etching and removing the sacrifice layer. The semiconductor substrate slightly remaining under the sacrificial layer is removed by etching.

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to the eleventh aspect, the semiconductor substrate remaining under the sacrificial layer is removed by anisotropic etching using an alkaline etchant. It is characterized by doing so.

According to a thirteenth aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to the eleventh aspect, the semiconductor substrate remaining under the sacrificial layer is removed by RIE. It is.

According to a fourteenth aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to any one of the first to thirteenth aspects, the bottom surface of the weight is removed by etching to reduce the thickness. It is characterized by the following.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the twelfth to fourteenth aspects, at the time of the etching, the bottom surface of the weight portion is simultaneously removed by etching. It is characterized in that the thickness is reduced.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to one embodiment of the present invention. Note that the impurity concentration of the single crystal silicon substrate 1 used in the present embodiment is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

First, a silicon oxide film 2 is formed on one main surface of a single crystal silicon substrate 1 which is an n-type semiconductor substrate having a thickness of 400 to 600 μm by thermal oxidation or the like, and a resist ( An opening 2a is formed by etching the silicon oxide film 2 using a mask (not shown) as a mask, and the resist is removed by plasma ashing or the like. At this time, the opening 2a is formed at a location surrounding the substantially square central portion 1a of the single crystal silicon substrate 1.
The shape of the central portion 1a is not particularly limited, and may be, for example, a circle, an ellipse, or a rectangle (rectangle, square).

Subsequently, using the silicon oxide film 2 in which the opening 2a is formed as a mask, a p-type impurity such as boron (B) is deposited and subjected to thermal diffusion or ion implantation and annealing to form a high-concentration impurity layer. A certain p + type buried sacrificial layer 3a is formed (FIG. 1A), and a silicon oxide film 2 is formed.
Is removed by etching.

In this embodiment, p-type impurity deposition and thermal diffusion or ion implantation and annealing are performed using the silicon oxide film 2 as a mask. However, the present invention is not limited to this. Alternatively, deposition and thermal diffusion or ion implantation and annealing may be performed using the silicon nitride film as a mask.

In this embodiment, the p + type buried sacrificial layer 3a is formed on the single crystal silicon substrate 1. However, an n type impurity such as phosphorus (P) is deposited and thermally diffused or ion implanted. Alternatively, the n + type buried sacrificial layer may be formed by performing an annealing process.

Further, the p + type buried sacrificial layer 3a is
It may extend from the entire outer edge of a so as to completely surround that portion, or may extend from a portion of the outer edge. When extending from the whole, the p + type buried sacrificial layer 3a may have an annular shape, for example, the central portion 1a is circular, and the p + type buried sacrificial layer 3a is formed by a concentric circle and a central portion formed by a concentric circle. 1a, or the central portion 1a is an inner square, and the p + -type buried sacrificial layer 3a is formed by an outer square concentric with and in the same direction as the inner square, and an annular shape between the inner square and the outer square. May be a part. Further, the p + -type buried sacrificial layer 3a may be a portion formed by a portion between the circular central portion 1a and the outer square or a portion formed by a combination of the opposite portions. Alternatively, an elliptical shape may be used.

The p + type buried sacrificial layer 3a is
When extending from a part of the outer edge of a, the p + type buried sacrificial layer 3
a is an equal angle around the center 1a (eg, 90 °)
In the case of 90 °, the p + -type buried sacrificial layer 3a has four beam forms facing each other at the central portion 1a (that is, at the central portion 1a). Crossing a cross). In other words, the p + type buried sacrificial layer 3a may extend radially from the central portion 1a, and the number thereof is not limited.

Next, an n-type epitaxial layer 4 is formed on one main surface of the single-crystal silicon substrate 1 with a thickness corresponding to the bending portion 15 that bends when an acceleration is applied. By performing deposition and thermal diffusion or ion implantation and annealing of a p-type impurity such as boron (B) at a portion corresponding to the above, a piezo resistor 5 that converts a resistance change due to the bending of the bending portion 15 into an electric signal is formed. The diffusion wiring is formed by depositing a p-type impurity at a higher concentration than the piezoresistor 5 and performing thermal diffusion or ion implantation and annealing so as to be electrically connected to the piezoresistor 5 (FIG. 1B). 6 to form a single-crystal silicon substrate 1
(FIG. 1C) A silicon oxide film 7 is formed on the two main surfaces and on the epitaxial layer 4.

Next, a protective film 8 such as a silicon nitride film is formed on the silicon oxide film 7 by a CVD method or the like, and the silicon oxide film 7 on the two main surfaces of the single crystal silicon substrate 1 / part of the protective film 8 is removed. Reactive ion etching (RIE)
ching) to remove by etching

An opening 9 is formed at a position corresponding to the outer peripheral edge of FIG. 1 (FIG. 1D).

Next, the silicon oxide film 7 having the opening 9 formed therein / the protective film 8 is used as a mask to form the single crystal silicon substrate 1.
By performing anisotropic etching using an alkaline etchant such as a potassium hydroxide (KOH) solution,
A notch 10 reaching the p + type buried sacrificial layer 3a is formed (FIG. 1E).

Next, the silicon oxide film 7 / protective film 8 at a desired position on the diffusion wiring 6 is removed by etching, and aluminum (Al) is formed by sputtering or vapor deposition so as to be electrically connected to the diffusion wiring 6. A metal wiring 11 and an electrode pad (not shown) are formed, and a wiring protection film 12 such as a chromium film, a silicon nitride film, and a fluororesin is formed on the surface of the single crystal silicon substrate 1 on which the metal wiring 11 is formed. (FIG. 1F).

In the case where the silicon nitride film is used as the wiring protection film 12, Al which is commonly used as the metal wiring 11 may cause problems such as alloy spikes at 500 ° C. or more. It is desirable to grow at a low temperature by a method or the like.

When the fluororesin is used as the wiring protective film 12, the process can be simplified because spin coating can be performed.

Next, a part of the wiring protection film 12, the protection film 8, the silicon oxide film 7, and the epitaxial layer 4 is removed by etching by RIE, anisotropic etching or isotropic etching. An etchant inlet (not shown) reaching the layer 3a is formed.

Next, an etchant (50% hydrofluoric acid aqueous solution: 69% nitric acid aqueous solution: acetic acid = 1: 1 to 3: 8 by volume) composed of an acidic solution containing hydrofluoric acid or the like was introduced from the etchant inlet. The p + type buried sacrificial layer 3a is removed by isotropic etching to form the cut groove 3.

Next, a desired portion of the epitaxial layer 4 is removed by etching to form a slit 13, thereby forming a frame-like frame 14 having an upper surface side and a lower surface side.
It has a central part 15a and a beam part 15b, and the beam part 15b is at least part of the inner peripheral side surface of the frame 14 and the central part 15a.
, A bending portion 15 in which the beam portion 15b and the central portion 15a are integrally connected, a weight portion 16 suspended from the central portion 15a via a neck portion 16a, and a lower surface of the frame 14. A support member 17 that supports the side and surrounds the outer peripheral edge of the weight portion 16 through the cut portion 10 is formed (FIG. 1G).

Finally, the silicon oxide film 7 / protective film 8 on the two main surfaces of the wiring protective film 12 and the single-crystal silicon substrate 1 are removed by etching, and a concave portion 18a is provided at a position corresponding to the weight portion 16. The lower stopper 18 is bonded to the two main surfaces of the single crystal silicon substrate 1 by anodic bonding or the like (FIG. 1).
(H)).

Therefore, in the present embodiment, the p + type buried sacrificial layer 3a is removed by etching after forming the wiring protective film 12 on the metal wiring 11 and the electrode pads (part of the metal wiring). The metal wiring 11 and the electrode pad can be prevented from being corroded or disconnected by the etchant used for etching the p + type buried sacrificial layer 3a, thereby improving the chip yield including reliability.

Second Embodiment FIG. 2 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention. Since the manufacturing process up to FIG. 2C of the semiconductor acceleration sensor according to the present embodiment is the same as the manufacturing process up to FIG. 1C as the first embodiment, the description is omitted here. 2
Description will be made from the manufacturing process (d).

A desired portion of the silicon oxide film 7 on the diffusion wiring 6 is removed by etching, and a metal wiring 11 made of Al or the like and an electrode pad are formed so as to be electrically connected to the diffusion wiring 6 by sputtering or evaporation. (Not shown) (FIG. 2D).

Next, a silicon nitride film 19 as a wiring protection film is formed on the silicon oxide film 7 by a CVD method or the like, and the silicon nitride film 19 / silicon nitride film 19 on the two main surfaces of the single crystal silicon substrate 1 is formed. The portion is etched away by RIE or the like to form an opening 20 at a position corresponding to the outer peripheral edge of the weight portion 16 (FIG. 2E). Here, the silicon nitride film 19
Are formed so as to cover the metal wiring 11 and the electrode pads (not shown). In addition, the silicon nitride film 19
For the same reason as in the first embodiment, it is desirable to perform low-temperature growth by a plasma CVD method or the like.

Next, using the silicon oxide film 7 / silicon nitride film 19 in which the opening 20 has been formed as a mask, anisotropically forming the single crystal silicon substrate 1 using an alkaline etchant such as a potassium hydroxide (KOH) solution. A notch 10 reaching the p + type buried sacrificial layer 3a is formed by performing the reactive etching (FIG. 2F).

Next, the silicon oxide film 7 / silicon nitride film 19 on one main surface of the single crystal silicon substrate 1 and part of the epitaxial layer 4 are removed by RIE, anisotropic etching or isotropic etching. And an etchant inlet (not shown) reaching the p + type buried sacrificial layer 3a.
An etchant (50% hydrofluoric acid aqueous solution: 69%) consisting of an acidic solution containing hydrofluoric acid etc.
Nitric acid aqueous solution: acetic acid = 1: 1 to 3: 8 by volume)
The p + type buried sacrificial layer 3a is removed by isotropic etching to form the cut groove 3.

Next, by removing a desired portion of the epitaxial layer 4 by etching to form a slit 13, a frame-shaped frame 14 having an upper surface side and a lower surface side is formed.
It has a central part 15a and a beam part 15b, and the beam part 15b is at least part of the inner peripheral side surface of the frame 14 and the central part 15a.
, A bending portion 15 in which the beam portion 15b and the central portion 15a are integrally connected, a weight portion 16 suspended from the central portion 15a via a neck portion 16a, and a lower surface of the frame 14. A support member 17 that supports the side and surrounds the outer peripheral edge of the weight portion 16 through the cut portion 10 is formed (FIG. 2G).

Finally, the silicon nitride film 19 and the silicon oxide film 7 on the two main surfaces of the single-crystal silicon substrate 1 are removed by etching, and the recess 1 is formed at a position corresponding to the weight 16.
2a is bonded to the two main surfaces of the single crystal silicon substrate 1 by anodic bonding or the like (FIG. 2).
(H)).

Therefore, in the present embodiment, after the silicon nitride film 19 is formed on the metal wiring 11 and the electrode pad (not shown), the p + type buried sacrificial layer 3a is removed by etching. The metal wiring 11 and the electrode pad can be prevented from being corroded or disconnected by the etchant for etching removal, and the chip yield including reliability is improved.

In the present embodiment, the entire surface of the silicon nitride film 19 is removed. However, the present invention is not limited to this. As shown in FIG. 3, a portion on an electrode pad (not shown) is formed. Only the silicon nitride film 19 may be thinned by pattern etching, and after the p + type buried sacrificial layer 3a is removed by etching, the silicon nitride film 19 may be entirely etched to expose only the electrode pads. Accordingly, portions other than the electrode pads are covered with the silicon nitride film 19, and the moisture resistance of the sensor element can be improved. Here, only the silicon nitride film 19 on the electrode pad is thinned by pattern etching because the p + type buried sacrificial layer 3a is etched and removed, and the surface of the substrate becomes uneven. To decrease,
This is because the pattern processing (photolithography step) becomes difficult, and if only the silicon nitride film 19 on the electrode pad is thinned by pattern etching in advance, the pattern processing is performed after the p + -type buried sacrificial layer 3a is removed by etching. This is because only the electrode pad can be exposed by the entire surface etching without performing the above.

Third Embodiment FIG. 4 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention. The manufacturing process up to FIG. 4D of the semiconductor acceleration sensor according to the present embodiment is the same as the manufacturing process up to (d) shown in FIG. 1 as the first embodiment. 4
Description will be made from the manufacturing process (e).

The silicon oxide film 7 having the opening 9 formed therein
Using the protective film 8 as a mask, the cut portion 10 is formed by performing anisotropic etching of the single-crystal silicon substrate 1 using an alkaline etchant such as a potassium hydroxide (KOH) solution. At this time, the etching is stopped before reaching the p + -type buried sacrificial layer 3a, so that the single crystal silicon substrate 1 remains under the p + -type buried sacrificial layer 3a by several tens of μm (FIG. 4E).

Next, the silicon oxide film 7 / protective film 8 at a desired location on the diffusion wiring 6 is removed by etching, and is made of Al or the like by sputtering or vapor deposition so as to be electrically connected to the diffusion wiring 6. A metal wiring 11 and an electrode pad (not shown) are formed, and a wiring protection film 12 such as a chromium film, a silicon nitride film, and a fluorine resin is formed on one main surface side of the single crystal silicon substrate 1 (FIG. 4F). ).

Next, the silicon oxide film 7 / silicon nitride film 19 on one main surface of the single crystal silicon substrate 1 and a part of the epitaxial layer 4 are removed by RIE, anisotropic etching or isotropic etching. And an etchant inlet (not shown) reaching the p + type buried sacrificial layer 3a.
An etchant (50% hydrofluoric acid aqueous solution: 69%) consisting of an acidic solution containing hydrofluoric acid etc.
Nitric acid aqueous solution: acetic acid = 1: 1 to 3: 8 by volume)
The p + type buried sacrificial layer 3a is removed by isotropic etching to form the cut groove 3.

Next, in FIG. 4E, the single-crystal silicon substrate 1 left under the p + -type buried sacrificial layer 3a is removed by anisotropic etching, RIE, or the like to remove desired portions of the epitaxial layer 4. To remove slit 1
By forming the frame 3, a frame-shaped frame 14 having an upper surface side and a lower surface side, a central portion 15a and a beam portion 15b are provided, and the beam portion 15b is at least a part of the inner peripheral side surface of the frame 14 and the central portion 15a. A flexible portion 15 extending between the two portions, a beam portion 15b and a central portion 15a are integrally connected, a weight portion 16 suspended from the central portion 15a via a neck portion 16a, and a lower surface side of the frame 14. And weight 1
A support member 17 is formed to surround the outer peripheral edge of No. 6 via the cutout portion 10 (FIG. 4 (g)).

Here, the shape of the single-crystal silicon substrate 1 remaining under the p + -type buried sacrificial layer 3a after etching differs depending on the etching method, and according to the anisotropic etching using an alkaline etchant. The shape shown by the solid line in FIG. 5A, and the shape shown by the broken line in FIG. 5A according to RIE. FIG. 5A shows the case where the same mask is used for forming the weight portion 16 regardless of the etching method, but is formed on the bottom surface of the cavity after removing the p + type buried sacrificial layer 3a. When the mask size when forming the weight portion 16 is adjusted so that the size of the through hole to be formed is the same,
As shown in FIG. 5B, the weight size can be increased by RIE. This is because, when the weight size is fixed, R
This indicates that the use of the IE can reduce the chip size.

Finally, the silicon oxide film 7 / protective film 8 on the two main surfaces of the wiring protective film 12 and the single crystal silicon substrate 1 are removed by etching, and a concave portion 18a is provided at a position corresponding to the weight portion 16. The lower stopper 18 is bonded to the two main surfaces of the single crystal silicon substrate 1 by anodic bonding or the like (FIG. 4 (h)).

Therefore, in this embodiment, the wiring protection film 12 is formed on the metal wiring 11 and the electrode pads (not shown).
Is formed, the p + type buried sacrificial layer 3a is removed by etching, so that the metal wiring 11 and the electrode pad can be prevented from being corroded or disconnected by the etchant for this etching removal, and the reliability is improved. The chip yield including the above is improved.

Since the weight 16 and the support member 17 are not separated even after the p + type buried sacrificial layer 3a is removed by etching, the substrate is not broken in this step, and the yield of the substrate can be greatly improved. .

In the case shown in FIGS. 2 and 3,
Stop etching before reaching the p + type buried sacrificial layer 3a,
After the p + type buried sacrificial layer 3a is removed by etching, p +
If the single crystal silicon substrate 1 remaining under the type embedded sacrifice layer 3a is removed by etching, the p + type embedded sacrifice layer 3 is removed.
Substrate destruction at the time of etching removal of a is eliminated, and the yield of the substrate can be greatly improved.

Embodiment 4 = FIG. 6 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention. The manufacturing process of the semiconductor acceleration sensor according to the present embodiment up to FIG. 6F is the same as the manufacturing process up to (f) of FIG. 4 shown as the third embodiment. FIG.
Description will be made from the manufacturing process (g).

After the silicon oxide film 7 / protective film 8 at the portion to be the bottom surface of the weight portion 16 is removed by etching, anisotropic etching using alkaline etchant or RIE using the silicon oxide film 7 / protective film 8 as a mask. Gives p +
By removing the single crystal silicon substrate 1 remaining under the mold buried sacrificial layer 3a and the portion serving as the bottom surface of the weight portion 16 by etching and removing the desired portion of the epitaxial layer 4 by etching to form the slit 13, A frame-like frame 14 having an upper surface side and a lower surface side, a central portion 15a and a beam portion 1
5b, the beam portion 15b extends between at least a portion of the inner peripheral side surface of the frame 14 and the central portion 15a, and the beam portion 1
5b and central portion 15a are integrally connected to flexible portion 1
5, a weight portion 16 suspended from a central portion 15a via a neck portion 16a, and a lower surface side of the frame 14,
A support member 17 that surrounds the outer peripheral edge of the weight portion 16 via the cutout portion 10 is formed (FIG. 6G).

Finally, the silicon oxide film 7 / protective film 8 on the two main surfaces of the wiring protective film 12 and the single-crystal silicon substrate 1 are removed by etching, and the lower stopper 21 having a flat shape is subjected to single-crystal bonding by anodic bonding or the like. It is bonded to the two main surfaces of the silicon substrate 1 (FIG. 6 (h)).

Therefore, in the present embodiment, the wiring protection film 12 is formed on the metal wiring 11 and the electrode pads (not shown).
Is formed, the p + type buried sacrificial layer 3a is removed by etching, so that the metal wiring 11 and the electrode pad can be prevented from being corroded or disconnected by the etchant for this etching removal, and the reliability is improved. The chip yield including the above is improved.

Since the weight 16 and the supporting member 17 are not separated even after the p + type buried sacrificial layer 3a is removed by etching, the substrate is not broken in this step, and the yield of the substrate can be greatly improved. .

Since the bottom of the weight portion 16 is removed by etching, a flat stopper can be used as the lower stopper 21 to be joined to the single-crystal silicon substrate 1, eliminating the need to form a recess. In addition, the processing cost of the stopper becomes unnecessary, and the manufacturing cost of the chip can be reduced.

In all of the above embodiments,
If the thickness of the weight portion 16 is reduced by removing the bottom surface of the weight portion 16 by etching, the lower stopper 21 having a flat shape can be used.

Embodiment 5 = FIG. 7 is a schematic plan view showing a state of the semiconductor acceleration sensor according to the present embodiment as viewed from above, and FIG. 8 is a plan view of the semiconductor acceleration sensor according to the present embodiment. FIG. 9 is a schematic cross-sectional view showing the manufacturing process at AA ′ in FIG. 7, and FIG. 9 is a schematic cross-sectional view showing the manufacturing process at BB ′ in FIG. 7 of the semiconductor acceleration sensor according to the present embodiment. FIG. 10 is a schematic cross-sectional view showing a manufacturing process of the semiconductor acceleration sensor according to the present embodiment at CC ′ in FIG. 7.

First, a silicon oxide film 2 is formed on one main surface of the single crystal silicon substrate 1 by thermal oxidation or the like, and the silicon oxide film 2 is etched to form a substantially square center of the single crystal silicon substrate 1. A substantially elongated opening 2a extends outwardly from the outer edge of portion 1a and is spaced at equal angles (90 °). Note that the opening 2a may be formed at a location surrounding the center.

Subsequently, using the silicon oxide film 2 in which the opening 2a is formed as a mask, p-type impurities such as boron (B) are deposited and thermally diffused or ion-implanted and annealed to perform p + -type burying. A sacrificial layer 3a is formed (FIGS. 8A, 9A, and 10A), and the silicon oxide film 2 is removed by etching.

In this embodiment, the p + -type buried sacrificial layer 3a is formed on the single-crystal silicon substrate 1. However, an n-type impurity such as phosphorus (P) is deposited and thermally diffused or ion-implanted. Alternatively, the n + type buried sacrificial layer may be formed by performing an annealing process.

The p + type buried sacrificial layer 3a is
It may extend from the entire outer edge of a so as to completely surround that portion, or may extend from a portion of the outer edge. When extending from the whole, the p + type buried sacrificial layer 3a may have an annular shape, for example, the central portion 1a is circular, and the p + type buried sacrificial layer 3a is formed by a concentric circle and a central portion formed by a concentric circle. 1a, or the central portion 1a is an inner square, and the p + -type buried sacrificial layer 3a is formed by an outer square concentric with and in the same direction as the inner square, and an annular shape between the inner square and the outer square. May be a part. Further, the p + -type buried sacrificial layer 3a may be a portion formed by a portion between the circular central portion 1a and the outer square or a portion formed by a combination of the opposite portions. Alternatively, an elliptical shape may be used.

The p + type buried sacrificial layer 3a is
When extending from a part of the outer edge of a, the p + type buried sacrificial layer 3
a is an equal angle around the center 1a (eg, 90 °)
In the case of 90 °, the p + -type buried sacrificial layer 3a has four beam forms facing each other at the center 1a (ie, a cross at the center). Which intersects). In other words, the p + type buried sacrificial layer 3a may extend radially from the central portion 1a, and the number thereof is not limited.

Next, on one main surface of the single-crystal silicon substrate 1, a thickness n corresponding to the bending portion 15 which bends when acceleration is applied is applied.
Type epitaxial layer 4 is formed on both sides by low pressure CVD,
A silicon oxide film 7 is formed by pyrogenic oxidation or the like, a protective film 8 such as a silicon nitride film is formed on the silicon oxide film 7 by a low pressure CVD method or the like, and a weight 3 on the two main surfaces of the single crystal silicon substrate 1 is formed. The opening 9 is formed by etching and removing the silicon oxide film 7 / protective film 8 at a position corresponding to the outer peripheral edge of FIG. 8B (FIGS. 8B, 9B, and 10B).

In the present embodiment, the silicon oxide film 7 / the protective film 8 are formed, but the present invention is not limited to this. Only the silicon oxide film 7 or the protective film 8 may be formed. . However, silicon oxide film 7 / protective film 8
Is formed, the internal stress of each film is compressed and pulled (or vice versa) to reduce the warpage of the beam 15b.

Next, using the silicon oxide film 7 having the opening 9 formed therein and the protective film 8 as a mask, potassium hydroxide (KO) is used.
H) The cut portion 10 is formed by performing anisotropic etching of the single-crystal silicon substrate 1 using an alkaline etchant such as a solution until reaching the p + -type buried sacrificial layer 3a (FIG. 8C, FIG. 9 (c)). Next, the movable electrode 22 and the movable electrode 22 are formed on the protective film 8 on one main surface side of the single crystal silicon substrate 1.
The metal wiring 23, the upper stopper bonding electrode 24, and the electrode pad 25 are formed of gold (Au), Al, or the like (FIGS. 8D, 9D, and 10C). At this time, the movable electrode 22 and the chromium (Cr) film are interposed to improve the adhesion to the underlayer.
The metal wiring 23, the upper stopper bonding electrode 24, and the electrode pad 25 may be formed. In addition, as a method of patterning the movable electrode 22, the metal wiring 23, the upper stopper bonding electrode 24, and the electrode pad 25, a metal layer is formed by performing vapor deposition, sputtering, or the like, and is formed into a predetermined shape using photolithography technology and etching technology. A method of patterning, or forming a resist or the like in advance at locations other than those where the movable electrode 22, the metal wiring 23, the upper stopper bonding electrode 24, and the electrode pad 25 are formed, and then forming a metal layer by performing evaporation or sputtering, etc. , There is a so-called lift-off method.

Next, a wiring protection film 12 such as a chromium film, a silicon nitride film, and a fluororesin is formed on one main surface side of the single crystal silicon substrate 1. When the silicon nitride film is used as the wiring protection film 12, the movable electrode 22, the metal wiring 23,
Since Al commonly used as the upper stopper bonding electrode 24 and the electrode pad 25 may cause a problem such as an alloy spike at 500 ° C. or more, it is preferable to grow the Al at a low temperature by a plasma CVD method or the like.

In the case where the wiring protective film 12 is made of fluororesin, the process can be simplified since spin coating can be performed.

Next, the wiring protection film 12, the silicon oxide film 7
/ Protective film 8 and part of epitaxial layer 4 are etched and removed by RIE, anisotropic etching or isotropic etching to form an etchant inlet (not shown) reaching p + type buried sacrificial layer 3a. I do.

Next, an etchant (50% hydrofluoric acid aqueous solution: 69% nitric acid aqueous solution: acetic acid = 1: 1 to 3: 8 by volume) composed of an acidic solution containing hydrofluoric acid or the like was introduced from the etchant inlet. The p + type buried sacrificial layer 3a is removed by isotropic etching to form the cut groove 3.

Next, by using the wiring protective film 12 in which the opening 12a is formed as a mask, a desired portion of the epitaxial layer 4 is removed by etching to form a slit 13, thereby forming a frame having an upper surface side and a lower surface side. Frame 14
And a central portion 15a and a beam portion 15b.
5a, the beam portion 15b and the central portion 15a are integrally connected to each other, a weight portion 16 suspended and supported by the central portion 15a via a neck portion 16a, A support member 17 that supports the lower surface side and surrounds the outer peripheral edge of the weight portion 16 through the cutout portion 10 is formed (FIGS. 8E, 9E, and 10D).

Finally, the wiring protective film 12 and the silicon oxide film 7 / protective film 8 on the two main surfaces of the single crystal silicon substrate 1 are removed by etching (FIGS. 8 (f), 9 (f), 1).
0 (e)), a lower stopper 18 having a concave portion 18a at a position corresponding to the weight portion 16 is bonded to the two main surfaces of the single crystal silicon substrate 1 by anodic bonding or the like, and a portion corresponding to the weight portion 16 is formed. The movable electrode 22
The upper stopper 26 having the fixed electrode 27 formed so as to face the upper stopper is bonded to the upper stopper bonding electrode 24 by anodic bonding or the like (FIGS. 8 (g), 9 (g), 10).
(F)). Here, the fixed electrode 2 is provided on the upper stopper 26.
7 and a contact hole 28 for making contact with the electrode pad 25 are formed.

Therefore, in the present embodiment, after the wiring protection film 12 is formed on the movable electrode 22, the metal wiring 23, the upper stopper bonding electrode 24 and the electrode pad 25, p +
Since the mold buried sacrificial layer 3a is removed by etching, the movable electrode 22, the metal wiring 23, and the upper stopper bonding electrode 2 are etched by an etchant for this etching removal.
4 and the electrode pads 25 can be prevented from being corroded or disconnected, and the chip yield including reliability is improved.

In the present embodiment, the acceleration is detected by converting the change in the capacitance between the opposing electrodes (the movable electrode 22 and the fixed electrode 27) into an electric signal and detecting the acceleration. This eliminates the need for a process for forming the diffusion wiring 6 and the contact hole, thereby simplifying the process.

In the piezoresistor 5, the sensitivity changes with temperature. In the present embodiment, the sensitivity does not change with temperature, the sensitivity-temperature characteristics are improved, and the sensitivity is adjusted by adjusting the gap between the electrodes. Becomes possible.

In the present embodiment, as shown in FIG. 4, when the cut portion 10 is formed, if the single-crystal silicon substrate 1 is left under the p + -type buried sacrificial layer 3a, the p + Since the weight portion 16 and the support member 17 are not separated even after the mold embedded sacrificial layer 3a is removed by etching,
Substrate destruction in this step is eliminated, and the yield of the substrate can be greatly improved.

In the present embodiment, as shown in FIG. 6, if the bottom of the weight portion 16 is removed by etching to reduce the thickness of the weight portion 16, a lower stopper having a flat shape can be obtained. It is not necessary to form a concave portion, and the processing cost of the stopper becomes unnecessary, and the manufacturing cost of the chip can be reduced.

In all of the above embodiments,
Although the case of the p + type buried sacrificial layer 3a as the sacrificial layer has been described, the present invention is not limited to this. If a porous silicon layer is formed as the sacrificial layer, the single crystal silicon substrate 1 and the epitaxial layer 4 The selectivity of about 150 times or more can be obtained as compared with the above, and the bending portion 15 can be formed with high accuracy.

Here, as a method for forming the porous silicon layer, for example, as shown in FIG. 11, electrodes 30a and 30b are arranged in an electrolytic bath 29 so as to face each other, and electrodes 30a and 30b are formed.
Ob is connected to an external DC power supply (not shown).
Then, the electrolytic bath 29 is filled with an electrolytic solution 31 containing a strong acid such as a hydrofluoric acid (HF) solution, and the electrodes 30a, 30b
A single-crystal silicon substrate 1 on which a silicon oxide film 2 patterned in a predetermined shape is formed on one main surface by a substrate fixing jig 32 is disposed therebetween. And the electrode 30
a, 30b to make the electrode 30a a cathode,
By using 0b as the anode, fluorine ions are generated in the electrolytic solution 31, and the fluorine ions are converted into the p + -type buried sacrificial layer 3a.
Is dissolved to form a porous silicon layer. Further, the single crystal silicon substrate 1 may be directly made porous using an anodizing method.

Further, in all the above-described embodiments, the case where the etchant is introduced only from the etchant introduction port has been described. However, the present invention is not limited to this, and the cut portion 10 or the cut portion 10 and the etchant introduction port are not limited to this. An etchant may be introduced from both.

Further, in all of the above embodiments, the lower stopper is joined after forming the slit 13, but the slit 13 may be formed after joining the lower stopper.

Further, in all of the above-described embodiments, the portion adjacent to the beam portion 15b and the slit 13 on the inner side surface of the frame 14 are formed at the same time. However, the present invention is not limited to this. After the slits 13 on the inner side surface of the frame 14 are formed, the slits 13 adjacent to the beam 15b may be formed (or vice versa). However, if the slit 13 on the inner side surface of the frame 14 is formed and then the slit 13 adjacent to the beam portion 15b is formed, the cut groove 3 becomes RI
It is not etched by E or the like.

In all the above embodiments, after the p + type buried sacrificial layer 3a is removed by etching,
Although the slit 13 is formed, the present invention is not limited to this. The p + -type buried sacrificial layer 3a may be removed by etching after the slit 13 is formed.

Further, the slit 13 of the epitaxial layer 4
If a high-concentration connection layer connected to the p + -type buried sacrificial layer 3a is formed in advance by deposition of p-type or n-type impurities and thermal diffusion or ion implantation and annealing at the formation location, the accuracy is further improved. A slit 13 can be formed.

Here, the boundary between the beam portion 15b and the central portion 15a of the bending portion 15 and the boundary between the beam portion 15b and the frame 14 have curved edges in order to avoid concentration of stress.
It is desirable to form a slit 13 having a shape.

In the fifth embodiment, the beam 15
The slit 13 is formed at a location other than the location where the beam portion 15b is formed, of the location adjacent to “b” and the inner side surface of the frame 14, but is not limited thereto. For example, as shown in FIG. Alternatively, a slit may be formed by etching away the epitaxial layer 4 between the bending portion 15 and the frame 14. In this case, the movable electrode 2
2 is formed on the upper surface side of the weight portion 16 (the surface on which the epitaxial layer 4 is formed). However, by making the epitaxial layer 4 a part of the weight 16, the weight 16
Can be increased in volume, and the sensitivity can be further increased. This can be applied to the first to fourth embodiments in which the piezoresistor 5 is formed.

Further, in all of the above embodiments, the case where four beams 15b are formed has been described. However, the present invention is not limited to this, and any number of beams such as eight beams, twelve beams, etc. A beam may be formed.

In all of the above embodiments,
If the metal wiring is arranged rotationally symmetrically with respect to a center line passing through the center of gravity of the weight portion 16 and perpendicular to the sensor, 4
Since the metal wirings are formed evenly on the beam portions 15b, a structure can be obtained in which thermal distortion is evenly applied and offset does not easily occur.

[0107]

According to the first aspect of the present invention, a sacrificial layer is formed on one main surface of a semiconductor substrate having one main surface and two main surfaces, the sacrificial layer extending outwardly from an outer edge of at least a portion of a central portion of the semiconductor substrate. And forming an epitaxial layer on one main surface of the semiconductor substrate with a thickness corresponding to a bending portion that bends when an acceleration is applied, and an acceleration applied to the bending portion at a predetermined position of the epitaxial layer. Forming an acceleration detecting section for detecting a signal, forming a metal wiring and an electrode pad for extracting a signal from the acceleration detecting section, and a portion corresponding to an outer peripheral edge of a weight portion that bends the bent portion when acceleration is applied. Forming a cut portion reaching the sacrificial layer by anisotropically etching the semiconductor substrate, and removing the sacrificial layer by isotropic etching to form the epitaxial layer. In the method for manufacturing a semiconductor acceleration sensor having a bent portion made of: and a weight portion suspended and supported by the bent portion, before the sacrificial layer is removed by etching, the acceleration detecting portion, the metal wiring, and the electrode pad are cleaned. Since the wiring protective film is formed so as to cover, it is possible to prevent corrosion or disconnection of the acceleration detecting portion, the metal wiring, and the electrode pad by an etchant for etching and removing the sacrificial layer, thereby improving the yield and the productivity. The manufacturing method of the semiconductor acceleration sensor which can be provided.

According to a second aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to the first aspect, a piezoresistor whose resistance value changes due to the bending is formed as a part of the acceleration detecting part corresponding to the bending part. Since the acceleration is detected by converting the change in the resistance value of the piezoresistor into an electric signal, the same effect as that of the first aspect can be obtained.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to the first aspect, the acceleration detecting portion is substantially opposed to the bending layer and / or the weight portion on the side of the epitaxial layer forming surface. The invention according to claim 1, wherein an electrode is disposed, and the acceleration is detected by detecting the deflection of the bending portion and / or the weight portion during acceleration application as a change in capacitance by the electrode. In addition to the effect, the process can be simplified as compared with the case of forming a piezoresistor, the sensitivity temperature characteristics are improved, and the sensitivity setting can be adjusted by the gap between the electrodes.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to third aspects, a high-concentration impurity layer is formed as the sacrificial layer. The selectivity is improved in addition to the effects of the invention according to any one of the first to third aspects.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to third aspects, a porous silicon layer is formed as the sacrificial layer. In addition to the effects of the invention according to any one of claims 1 to 3, selectivity is further improved.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to fifth aspects, a chromium film is used as the wiring protection film. Item 5. In addition to the effect of the invention described in Item 5, the chromium film is not lost by etching during the etching removal of the sacrifice layer, and the acceleration detecting portion, the metal wiring, and the metal oxide are removed by the etchant for etching the sacrifice layer. Corrosion or disconnection of the electrode pad can be prevented.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to fifth aspects, a fluorine resin is used as the wiring protection film. In addition to the effects of the invention described in any of the above items 5, the wiring protective film can be formed by spin coating, and the process can be simplified.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to fifth aspects, a silicon nitride film is used as the wiring protection film. In addition to the effect of the invention according to claim 5, the silicon nitride film does not disappear by etching during the etching removal of the sacrifice layer, and the acceleration detecting unit and the metal are removed by the etchant for etching the sacrifice layer. Corrosion or disconnection of wiring and electrode pads can be prevented, and if only the silicon nitride film on the electrode pads is removed by etching after the sacrificial layer is removed by etching, the moisture resistance of the sensor element is improved. Can be done.

According to a ninth aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to the eighth aspect, the silicon nitride film is formed at a low temperature of 300 ° C. or less by using a plasma CVD method. In addition to the effect of the invention described in claim 8, aluminum commonly used as metal wiring can be used.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to second aspects or the fourth to ninth aspects, the method further comprises the steps of: Only the wiring protection film on the electrode pad is thinned by pattern etching to a desired thickness. After the sacrificial layer is removed by etching, the wiring protection film is entirely etched to expose only the electrode pad. Therefore, in addition to the effect of the invention according to claim 1 or claim 2 or claim 4 or claim 9, after the sacrificial layer is removed by etching, the substrate surface becomes uneven, Pattern strength (photolithography process) becomes difficult because the strength of
By thinning only the wiring protection film on the electrode pad by pattern etching in advance, after etching and removing the sacrificial layer, only the electrode pad can be exposed by etching the entire surface without patterning.

According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to tenth aspects, the etching for forming the cut portion is stopped before reaching the sacrificial layer. After leaving the semiconductor substrate slightly below the sacrifice layer, forming an etchant introduction port reaching the sacrifice layer in the wiring protective film and the epitaxial layer, introducing the etchant from the etchant introduction port, and etching and removing the sacrifice layer. Since the semiconductor substrate slightly left under the sacrificial layer is removed by etching, in addition to the effect of the invention according to any one of claims 1 to 10, it is possible to remove the sacrificial layer by etching. In this case, the substrate can be prevented from being broken.

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor acceleration sensor according to the eleventh aspect, the semiconductor substrate remaining under the sacrificial layer is removed by anisotropic etching using an alkaline etchant. Thus, in addition to the effect of the invention described in claim 11, etching can be easily and relatively quickly removed.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to the eleventh aspect, the semiconductor substrate remaining under the sacrificial layer is removed by RIE. In addition to the effects of the invention of
The semiconductor substrate remaining under the sacrificial layer can be removed by etching without being immersed in a liquid, eliminating the risk of destruction of the substrate due to the viscosity and surface tension of the liquid when pulled up from the etchant. Since the etching proceeds vertically, the chip size can be reduced when the weights have the same size.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the first to thirteenth aspects, the bottom of the weight is removed by etching to reduce the thickness. Therefore, in addition to the effect of the invention according to any one of the first to thirteenth aspects, a stopper having a flat shape, a substrate, or the like can be joined to a surface of the semiconductor substrate different from the surface on which the epitaxial layer is formed. It is not necessary to form a concave portion at a position corresponding to a weight portion such as a substrate or a substrate, so that manufacturing costs can be reduced.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor acceleration sensor according to any one of the twelfth to fourteenth aspects, at the time of the etching, the bottom surface of the weight portion is simultaneously removed by etching. Since the thickness is reduced, the bottom surface of the weight portion can be etched without increasing the number of steps, in addition to the effect of the invention according to any one of the twelfth to fourteenth aspects.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to one embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention.

FIG. 4 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a shape of a cut portion when a single crystal silicon substrate left under a p + type buried sacrificial layer according to the present embodiment is removed by etching; (B) shows a case where the mask size is adjusted.

FIG. 6 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to another embodiment of the present invention.

FIG. 7 is a schematic plan view showing a state of the semiconductor acceleration sensor according to the present embodiment as viewed from above.

FIG. 8 shows a semiconductor acceleration sensor according to the present embodiment;
FIG. 7 is a schematic cross-sectional view showing a manufacturing process at AA ′ of FIG.

FIG. 9 is a diagram of the semiconductor acceleration sensor according to the present embodiment;
13 is a schematic cross-sectional view showing a manufacturing step at BB ′ of FIG.

FIG. 10 is a schematic cross-sectional view showing a manufacturing process of the semiconductor acceleration sensor according to the present embodiment at CC ′ in FIG. 7;

FIG. 11 is a schematic sectional view showing an apparatus for forming a porous silicon layer according to another embodiment of the present invention.

FIG. 12 is a schematic perspective view showing a partially broken state of a semiconductor acceleration sensor according to another embodiment of the present invention.

FIG. 13 is a schematic sectional view showing a manufacturing process of a semiconductor acceleration sensor according to a conventional example.

FIG. 14 is a schematic plan view showing a state of the semiconductor acceleration sensor according to the upper diagram as viewed from above.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 1a Central part 2 Silicon oxide film 2a Opening 3 Notch groove 3a p + type buried sacrificial layer 4 Epitaxial layer 5 Piezoresistance 6 Diffusion wiring 7 Silicon oxide film 8 Protective film 9 Opening 10 Cutout 11 Metal wiring DESCRIPTION OF SYMBOLS 12 Wiring protective film 13 Slit 14 Frame 15 Flexing part 15a Central part 15b Beam part 16 Weight part 16a Neck part 17 Support member 18 Lower stopper 18a Depression 19 Silicon nitride film 20 Opening 21 Lower stopper 22 Movable electrode 23 Metal wiring 24 Upper stopper Bonding electrode 25 electrode pad 26 upper stopper 26a concave portion 27 fixed electrode 28 contact hole 29 electrolytic cell 30a, 30b electrode 31 electrolytic solution 32 substrate fixing jig 33 p + type impurity layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takuro Ishida 1048 Odakadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd.

Claims (15)

[Claims] Forming a sacrificial layer on one main surface of a semiconductor substrate having one main surface and two main surfaces, the sacrificial layer extending outwardly from an outer edge of at least a portion of a central portion of the semiconductor substrate; Forming an epitaxial layer on one main surface with a thickness corresponding to a bending portion that bends when an acceleration is applied, and forming an acceleration detection portion for detecting acceleration applied to the bending portion at a predetermined portion of the epitaxial layer. Forming a metal wiring and an electrode pad for extracting a signal from the acceleration detection unit, and anisotropically forming a portion of the semiconductor substrate corresponding to an outer peripheral edge of a weight portion that bends the bending portion when acceleration is applied. Etching to form a cut portion reaching the sacrificial layer; removing the sacrificial layer by isotropic etching to form a bent portion made of the epitaxial layer; In a method of manufacturing a semiconductor acceleration sensor having a weight portion suspended and supported by a recess portion, a wiring protection film is formed so as to cover the acceleration detection portion, the metal wiring and the electrode pad before the sacrificial layer is removed by etching. A method for manufacturing a semiconductor acceleration sensor, comprising: 2. A piezoresistor whose resistance value changes due to bending is formed at a position corresponding to the bending portion as the acceleration detecting portion, and the change in the resistance value of the piezoresistor is converted into an electric signal, thereby accelerating the acceleration. 2. The method for manufacturing a semiconductor acceleration sensor according to claim 1, wherein the detection is performed. 3. An electrode, which is substantially opposed to the bent portion and / or the weight portion on the side of the epitaxial layer forming surface, is formed as the acceleration detection portion, and the bent portion and / or the weight portion when an acceleration is applied. 2. The method according to claim 1, wherein the acceleration is detected by detecting the deflection of the electrode as a change in capacitance by the electrode. 4. The method according to claim 1, wherein a high-concentration impurity layer is formed as the sacrificial layer. 5. The method for manufacturing a semiconductor acceleration sensor according to claim 1, wherein a porous silicon layer is formed as the sacrificial layer. 6. The method for manufacturing a semiconductor acceleration sensor according to claim 1, wherein a chromium film is used as said wiring protection film. 7. The method according to claim 1, wherein a fluorine resin is used as the wiring protection film. 8. The method of manufacturing a semiconductor acceleration sensor according to claim 1, wherein a silicon nitride film is used as said wiring protection film. 9. The method for manufacturing a semiconductor acceleration sensor according to claim 8, wherein said silicon nitride film is formed at a low temperature of 300 ° C. or less by using a plasma CVD method. 10. Prior to etching and removing the sacrificial layer, only the wiring protection film on the electrode pad is pattern-etched to a desired thickness to reduce the thickness, and after removing the sacrificial layer by etching, the wiring is removed. 10. The method of manufacturing a semiconductor acceleration sensor according to claim 1, wherein the protection film is entirely etched to expose only the electrode pad. 11. The etching for forming the cut portion is performed as follows:
Stopping before reaching the sacrificial layer, leaving a semiconductor substrate slightly under the sacrificial layer, forming an etchant inlet in the wiring protective film and the epitaxial layer to reach the sacrificial layer,
4. The semiconductor device according to claim 1, wherein said semiconductor substrate slightly remaining under said sacrificial layer is removed by etching after said sacrificial layer is etched and removed by introducing an etchant from said etchant inlet. Item 11. A method for manufacturing a semiconductor acceleration sensor according to any one of Items 10. 12. The semiconductor acceleration sensor according to claim 11, wherein the semiconductor substrate remaining under the sacrificial layer is removed by anisotropic etching using an alkaline etchant. Method. 13. The method according to claim 11, wherein the semiconductor substrate remaining under the sacrificial layer is removed by RIE. 14. The method of manufacturing a semiconductor acceleration sensor according to claim 1, wherein a bottom surface of said weight portion is removed by etching to reduce a thickness. 15. The apparatus according to claim 12, wherein, at the time of said etching, a bottom surface of said weight portion is simultaneously removed by etching to reduce the thickness.
The manufacturing method of the semiconductor acceleration sensor according to any one of the above.