JPH1098217A - Method for forming josephson junction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable improvement of the production yield, even with a micromachined Josephson junction area by deeply cutting out by the electron cyclotron resonance(ECR) plasma etching an upper superconductor layer into a specified plane shape until a tunnel barrier layer is reached. SOLUTION: A laminate structure (21+22+23) (Fig. A) is formed with a preetched sample 10, i.e., resist 27 disposed thereon for defining the junction area. An ECR plasma etching step 101 follows, to etch deeply an upper superconductor layer 23 until reaching a tunnel barrier layer 22, thus obtaining an etched sample 11 by cutting out the superconductor layer 23 into a specified plane shape (Fig. C). This sample 11 has improved characteristics with the generation of residues reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a Josephson junction used as an active element in a superconducting integrated circuit. However, the present invention relates to a method for producing a Josephson junction having good junction characteristics with good reproducibility and consequently improving the yield.

[0002]

2. Description of the Related Art A Josephson junction which is formed by sandwiching a thin tunnel barrier layer between a lower superconductor layer and an upper superconductor layer and is used as an active element in a cryogenic environment is also known.
In pursuit of high-speed performance, further miniaturization will be required in the future. Thus, so far, a method comprising the following steps has been considered suitable for producing such a small Josephson junction.

In each of the drawings described here, the left side is a cross-sectional view up to that step, and the right side is a plan view up to that step. First, as shown in FIG. A laminated structure (21 + 22 + 23) is formed by sequentially laminating a lower superconductor layer 21, a barrier layer 22 serving as a tunnel barrier layer of a Josephson junction, and an upper superconductor layer 23 thereon. Although a conductive ground plane is often formed between the substrate 20 and the lower superconductor layer 21, it is not shown in the drawings because it is not involved in the present invention. Next, as shown in FIG. 3B, in order to cut the lower superconductor layer 21 into a predetermined plane shape, a resist layer 24 patterned according to the predetermined plane shape is formed on the upper superconductor layer 23. Using this as an etching mask, etching is performed by a reactive ion etching (RIE) method, which is one of the anisotropic dry etching with high dimensional accuracy, and as shown in FIG. 22 + 23) is cut out into a predetermined plane shape.
As shown in FIG. 3D, a series of insulating films 25 are formed on this structure, and then immersed in an organic solvent, and a resist layer 24 is formed thereon by a so-called lift-off method.
Together, they are removed, and the surface of the upper superconductor layer 23 is exposed again as shown in FIG.

Next, as shown in FIG. 4A, a bonding area defining resist 27 having a predetermined flat area, for example, one of two orthogonal sides W1 and W2 is placed on the upper superconductor layer 23. Is formed by patterning. At this time, if the predetermined planar shape is a square, naturally, W1 = W2. 4 (B), the upper superconductor layer 23 is etched to the surface of the barrier layer 22 by the RIE method using the resist 27 as an etching mask, as shown in FIG. As shown in FIG. 4C, a laminated structure (21 + 2) in which the upper superconductor layer 23 is cut out into a predetermined planar shape.
2 + 23). The area of the barrier layer 22 and the area of the lower superconductor layer 21 thereunder are much larger than the area of the cut-out upper superconductor layer 23, but the effective area as a Josephson junction is these three layers 21, 22, Since 23 is defined by the overlapping area, if only the upper superconductor layer 23 is cut out to a predetermined area as described above,
The area is the effective area of the Josephson junction to be finally manufactured.

[0005] However, for the sake of convenience when describing the disadvantages of the conventional manufacturing method described later hereafter, or when describing the present invention, the structure shown in FIG. Before the RIE for cutting out the upper superconductor layer 23, the laminated structure (21 + 22 + 23) with the patterned resist 27 is denoted by reference numeral 10, which is referred to as "pre-etching sample". The structure shown in FIG. 4C, that is, the laminated structure (21 + 22 + 23) after RIE is also denoted by reference numeral 11, and this is called an "etched sample".

After obtaining the etched sample 11, FIG.
As shown in (A), a series of oxide films 28 are deposited while leaving the bonding area defining resist 27, and then immersed in an organic solvent to remove the resist 27 by a so-called lift-off method. As shown in FIG. 5 (B), the surface of the upper superconductor layer 23 cut into a predetermined plane shape is exposed again.

Although the process of fabricating a Josephson junction may be considered substantially up to this point, in general, a completion of a Josephson junction device is seen through a wiring layer forming process following this. That is, for the structure of FIG.
After etching to an appropriate depth for surface cleaning as required, a superconducting layer 29 for wiring formation on the upper superconducting layer 23 is formed as shown in FIG.
Next, in order to cut out the wiring-constituting superconductor layer 29 into a desired predetermined shape or wiring pattern finally, as shown in FIG.
As shown in FIG. 6C, a patterned resist 30 having a corresponding shape is formed, and the superconducting layer 29 is also etched by a suitable dry etching method such as RIE using this as an etching mask, as shown in FIG. A wiring pattern 29 corresponding to the planar shape of the patterned resist 30 or the wiring layer 29 of the corresponding wiring pattern can be obtained. Thereafter, if the patterned resist 30 is removed, a Josephson having a fine Josephson junction is finally obtained. The joining element is completed. However, in the step of FIG. 6, a lift-off method can be adopted instead of the etching.

[0008]

However, when electrical characteristics of many of the fine Josephson junctions manufactured as described above are taken, even if they have undergone the same manufacturing process, the characteristics vary. In some cases, the so-called sub-gap voltage range from zero voltage to the gap voltage has significantly degraded current-voltage characteristics, and this phenomenon is particularly noticeable when the junction area is reduced from 1 μm square to less. The tendency tends to be noticeable. And this is because
As shown in FIG. 7, it is already known that the influence is due to the etching residue.

That is, as described above, FIG.
Although the effective area of the Josephson junction to be finally formed is defined by the RIE process 100 of the upper superconductor layer 23 in FIG. 4, the etched sample 11 shown in FIG. In FIG. 7, if the RIE is insufficient for the portion where the upper superconductor layer 23 and the barrier layer 22 are in contact with each other, the enlarged portion surrounded by a virtual line circle in FIG. As schematically shown, a residue 31 may be generated around the lower edge of the upper superconductor layer 23. In this case, the residue 31 acts as an extremely thin and amorphous upper superconductor layer, so that the upper superconductor layer 23 itself is formed into a moderate shape from the beginning, and a part thereof is made thin. This is the same as a result that has passed, and the desired design expectation cannot be obtained.

Therefore, conventionally, attempts have been made to improve the characteristics by increasing the etching time, that is, by performing so-called over-etching. For example, Reference 1: IEEE Transactions on Supercond., Vol.5, N
In O.2, pp.2334-2337, assuming that the reference etching time required to etch the upper superconductor layer to the depth up to the barrier layer is t, twice the amount corresponding to 100% increase of t. It has been disclosed that by continuing RIE for a time 2t, a submicron Josephson junction having good device characteristics was obtained. That is, it is considered that the probability that the residue 31 was completely removed was increased by increasing the RIE time. By the way, if the additional over-etching time is Δt with respect to the reference etching time t, Δt = t in the case of the method disclosed in the above document.

However, the method of taking the over-etching time Δt to be considerably longer, as in the method disclosed in the above-mentioned document, causes deterioration of the resist pattern 27 used as an etching mask, and the shape of the upper superconductor layer 23 after etching is reduced. There is a problem that causes deterioration and reduction. This naturally increases the variation in the joining characteristics. If the over-etching is excessively performed, a large amount of the conductive material that has been removed by etching is deposited around the upper superconductor layer 23, which also causes deterioration of the bonding characteristics. In particular, in the RIE method, the gas pressure in the etching chamber at the time of etching was relatively high, and therefore, the probability that the etched substance was re-adhered to the barrier layer 22 or the like was high.

Actually, as shown in FIG. 8A, when the upper superconductor layer 23 is cut into a predetermined planar shape, a conventional RIE is used.
When the method was followed, considerable variations were found in the properties of the fabricated Josephson junctions. That is, FIG.
As shown in (B), 2 inches (5
cm) Diameter chips of 5 mm square are arranged in five rows and five columns on a silicon wafer 20, and 100 Josephson junction arrays with different dimensions in each chip are manufactured with the same pattern in each chip according to the conventional method. As a result, the chip c located at the center of the wafer 20, the two chips b and d located slightly outside the diagonal direction, and the chip a located at the peripheral corner.
The variation of the critical current value Ic with respect to the junction size of the Josephson junction samples a to d taken from each of the above is expressed as a maximum / minimum deviation from the average value of the critical current value Ic in%. It became to be shown in.

As is apparent, in the Josephson junction manufactured by the conventional manufacturing method, the variation becomes considerably large, especially as the junction size becomes smaller, for example, about 0.5.
In the sample group of μm square, the value reaches as much as 30% for a large deviation. Also, even if the joint size becomes relatively large from 1 μm square to more, the variation still remains.
Some are close to 15%. Of course, a large variation indirectly suggests that the properties of the individual joints are not very good, which is indeed the case. The fluctuation width in the in-plane direction of the wafer is large, and the characteristics are greatly different depending on the position where the sample is taken even for the same size.

The present invention has been made in view of such a fact. Even if the area of a Josephson junction is reduced from 1 μm square to a submicron square or less, a good product can be obtained without relying only on over-etching. With good reproducibility,
As a result, it is an object of the present invention to provide a new method for manufacturing a Josephson junction that can improve the manufacturing yield.

[0015]

In order to achieve the above object, the present invention provides: (a) forming a laminated structure by sequentially laminating a lower superconductor layer, a tunnel barrier layer, and an upper superconductor layer; A step of etching the upper superconductor layer by an electron cyclotron resonance (ECR) plasma etching method over a depth of up to a predetermined planar shape to cut out the upper superconductor layer; Is proposed.

Further, the present invention provides the above basic components.
(b) In addition to (a), when etching the upper superconductor layer by the above-mentioned ECR plasma etching method, a reference etching time required for etching the upper superconductor layer to a depth reaching the tunnel barrier layer. (c) the overetching time Δt is set to be 20% or less of the reference etching time t.

The present invention also proposes that the tunnel barrier layer in the above-mentioned laminated structure is made of a material which is resistant to ECR plasma etching and functions as an etching stop layer. When the target upper superconductor layer is made of a niobium or niobium nitride-based material, such a material is
It is proposed to use aluminum oxide as a material that functions as an appropriate etching stop layer when performing CR plasma etching and that functions satisfactorily as a tunnel barrier layer.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example of manufacturing a Josephson junction according to the present invention will be described with reference to FIG. However, the present invention
Substantially, this is a modification of one elementary process itself in a series of steps in the conventional Josephson junction fabrication method already described, so that for other elementary steps, the description of the conventional example described above should also be used effectively. Can be.

That is, first, the sample 10 before etching in the state shown in FIG.
Until a laminated structure (21 + 22 + 23) is obtained, FIG.
A series of steps shown in (E) may be followed, and these steps are not particularly modified in the present invention. However, as shown in FIG.
Then, as shown in FIG. 1B, instead of the conventional RIE process, the process proceeds to an ECR plasma etching process 101, and the upper superconductor layer 23 of the sample 10 before etching is replaced with the tunnel barrier layer 22. ECR over the depth of
Perform plasma etching. As a result, as shown in FIG. 1C, an etched sample 11 obtained by cutting the upper superconductor layer 23 into a predetermined planar shape can be obtained.
In the case of, the generation of residues is better suppressed than before, and the characteristics are improved. This will be verified later through specific examples.

The subsequent steps may follow the steps of FIG. 5 and subsequent steps which have already been described. However, as described above, in the process group before the application of the present invention, first, in order to cut out the entire laminated structure (21 + 22 + 23) into a predetermined planar shape, FIG. 6 (C) to FIG. 6 (C) in order to cut the wiring forming superconductor layer 29 into a predetermined shape or a predetermined wiring pattern after applying the present invention and the etching step used in the step (C). The etching process used when the process proceeds to may be desirably an ECR plasma etching process.

Further, assuming that the time required for ECR plasma etching of the upper superconductor layer 23 to the depth reaching the barrier layer 22 is a reference time t, in addition to this, the over-etching time Δt is longer and the ECR etching time is longer. May be continued. However, this is also a finding based on experiments performed by the present inventor. However, according to the present invention, since the generation of residues is reduced in the first place, the overetching time Δt may be zero, or a significant time is required. However, it is not necessary to take such a long time, and it is sufficient to increase the reference etching time t by 20% or less. Shorter over-etching time Δt not only increases the production efficiency, but also prevents the resist pattern 27 used as an etching mask from deteriorating and reduces the risk of causing deterioration or reduction in the shape of the upper superconductor layer 23 after etching. It is effective because it can be performed, and eventually has the effect of improving reproducibility and improving bonding characteristics. The advantages of the present invention are clear when compared with the above-mentioned known documents in which overetching was performed over a period of time 100% longer than the reference time t.

However, in the case of ECR plasma etching, the gas pressure in the etching chamber can be reduced by one to two orders of magnitude as compared with the conventional RIE. Therefore, whether or not overetching is performed in the first place, there is a low possibility that the constituent material of the etched upper superconducting layer 23 is re-adhered to, for example, the barrier layer 22 or the like. This is convenient for obtaining a son junction.

FIG. 1 (D) shows the E in FIG. 1 (B).
EC that can be used in the CR plasma etching process 101
A schematic configuration example of the R etching apparatus 30 is also shown.
However, since the apparatus itself may be a known apparatus, the substrate holder 37 is placed in the etching chamber 31 connected to a vacuum pump (not shown) and evacuated.
The sample 10 before etching supported by is stored. A plasma generating chamber 32 communicates with the etching chamber 31 through an opening, and a main coil 35 for generating a magnetic field necessary for generating ECR is provided so as to surround the plasma generating chamber 32. Microwave power is applied to the plasma generation chamber 32 from a microwave power supply 34 provided outside via a waveguide 39, and the plasma generation chamber 32 is provided outside via a substrate holder 37 also on the side of the sample 10 before etching. High-frequency power from the high-frequency power supply 33 is applied. Substrate holder 37 or sample 10
An auxiliary coil 36 that can be vertically adjusted to make the magnetic flux around the sample 10 uniform is also provided around the sample.

Further, in order to prevent sample contamination and to avoid the trouble of repeatedly evacuating and evacuating, the sample 10 before etching is loaded into the etching chamber 31 and the etched sample is removed.
In order to carry out the etching from the etching chamber 31 without breaking the vacuum, the etching chamber 31 can be removed through the gate valve 42.
There is also provided a sample exchange chamber 41 and the like that can be selectively accessed. In the sample exchange chamber 41, or a separate chamber (not shown) which also desirably allows selective access to the etching chamber 31 without breaking vacuum, the applicant of the present invention has already disclosed in Japanese Patent Application Laid-Open No. 7-263769. As disclosed, a scanning electron microscope (not shown) for observing the state of the residue in the sample or the like may be provided. In addition, this type of device is provided with a cooling system and other various auxiliary devices, but is not shown in the figure for simplicity.

With such an apparatus structure, the material of the upper superconductor layer 23 in the sample 10 before etching is niobium (N
b) or a niobium-based material typified by niobium nitride (NbN) (in this case, the lower superconductor layer 21 is generally used).
Is usually the same material), but usually a mixture of carbon fluoride gas, ie, carbon fluoride (CF ₄ ) gas or carbon fluoride
A CF ₄ + O ₂ gas is introduced into the plasma generation chamber 32, a microwave and a high frequency power of a predetermined frequency and a predetermined power are applied from a microwave power supply 34 and a high frequency power supply 33, respectively, and a predetermined size is applied to the main coil 35. When a magnetic field more than that is generated, an ECR phenomenon occurs, and a plasma 38 is generated in the plasma generation chamber 32, and this is irradiated with the sample 10 stored in the etching chamber 31 through the communication opening, whereby the sample is 10 is anisotropic E
Etch by CR plasma etching.

At this time, the barrier layer 22 located under the upper superconductor layer 23 to be subjected to the ECR plasma etching has a resistance to the ECR plasma etching of the upper superconductor layer 23, and may be used as a so-called etching stop layer. It is desirable that the barrier layer 22 be made of a material that can function, so that the thickness of the barrier layer 22 can be prevented from being largely deviated from the design dimensions. And manufacturing control becomes easier. As an example of such a material, for example, as described above, the upper superconductor layer 23 is made of niobium (Nb).
When a niobium-based material such as niobium nitride (NbN) is used, and carbon fluoride (CF ₄ ) gas or CF ₄ + O ₂ gas in which oxygen is mixed with carbon fluoride is used, aluminum oxide (AlO
_X ).

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, ECR was performed on a sample 10 before etching using aluminum oxide (AlO _x ) for the tunnel barrier layer 22 and niobium (Nb) for the upper superconductor layer 23 for the above-described reason. A case where plasma etching is performed will be described. In FIG. 1 (D), the distance between the exit of the plasma generation chamber 32 of the ECR etching apparatus 30 and the sample 10 is 5 cm, the substrate temperature of the sample 10 is 20 ° C., the frequency of the microwave power supply 33 is 2.45 GHz, the output is 360 W, the bias is Frequency of the high frequency power supply 33 for 13.56 MHz,
The output is 5 W, the gas pressure in the apparatus is 0.4 Pa, the magnetic flux generated by the main coil 35 is 875 Gauss, and the flow rate is 50 sccm in the plasma generation chamber 32.
EC of Nb upper superconductor layer 23 by CF ₄ gas introduced in
R plasma etching was attempted. At this time, the etching rate of the Nb upper superconductor layer 23 reached about 55 nm / min, but the etching rate of the aluminum oxide (AlO _x ) barrier layer 22 was at most about 2 nm / min. This indicates that the barrier layer 22 made of aluminum oxide (AlO _x ) has a sufficient function as an etching stop layer. Also, adjust the vertical position of the auxiliary coil 36 that can generate a magnetic flux of about 100 Gauss, and
We tried to make the magnetic field around 10 as uniform as possible. The above-mentioned gas pressure in the apparatus is one or two orders of magnitude lower than that required in the conventional RIE.

In summary, the present invention relates to a Josephson junction made with such manufacturing parameters,
As in FIG. 8 already described, the critical current value with respect to the junction size
When the variation characteristics of Ic were individually obtained for each manufactured at each position on the wafer, the results were as shown in FIG. 2 (A), and extremely favorable results were obtained. FIG. 2 (A) showing this characteristic example can be compared with the conventional example already described with reference to FIG. 8 (A), and the samples a to d in FIG. FIG. 2 (B), which shows whether or not it has been taken, is substantially the same as FIG. 8 (B). That is, also in this embodiment of the present invention, each of the 5 mm (5 mm)
In the corner chip, 100 Josephson junction arrays having different dimensions are manufactured with the same pattern in each chip. In FIG. 2B, the Josephson junction array formed on the center chip c is formed. The characteristic corresponds to the characteristic of sample c in FIG. 2A, and similarly, the characteristic of the Josephson junction formed on two chips b and d located slightly outside the center in the diagonal direction is the characteristic of FIG. The characteristics of the Josephson junctions formed on the samples b and d in the middle and on the chip a located at the peripheral corner correspond to those of the sample a in FIG.

As apparent from a comparison between FIG. 2A and FIG. 8A, according to the present invention, this is the case over the entire dimensional range, but in particular, 0.5 μm square. The effect of improving the variation in the miniaturized junction dimension area is extremely large, and the fluctuation range of the critical current value Ic is reduced to about 20% at most, compared to the previous example, and in some cases, It has decreased to about half of the conventional fluctuation width. In addition, it was found that the deviation in the in-plane direction of the wafer was also reduced, which is a desirable result.

Although the preferred embodiment of the present invention and one embodiment have been described above in detail, any modification according to the gist of the present invention is free. For example, in the above description, EC
On the upper superconducting layer 23 of the pre-etching sample 10 to be etched in the R plasma etching step 101, a bonding pattern defining resist 27 of a rectangular pattern having an area dimension W1 × W2 according to a planar shape to be finally obtained. Is formed, and in the presence of the resist 27, the upper superconducting layer 23 is cut out uniformly into a corresponding rectangular planar shape, but this can be changed to a two-step process. That is, first, a stripe-shaped resist having a width W1 is formed, and the upper superconductor layer 23 is subjected to ECR plasma etching into a stripe having a width W1, and then a second stripe having a width dimension W2 in a direction orthogonal to the width direction is formed. The upper superconductor layer 23 having a rectangular pattern defined by the area dimension W1 × W2 may be obtained by forming a resist in a shape and performing ECR plasma etching on the upper superconductor layer 23 in a stripe shape again. . As described above, the method of cutting out the upper superconductor layer 23 of the rectangular pattern as a result using the respective striped resists is a method suitable for obtaining a fine rectangular pattern and a pattern having sharp corners.

[0031]

According to the present invention, when the upper superconductor layer of the junction is cut into a predetermined planar shape in the course of the production process of the Josephson junction, the generation of an etching residue which is a cause of a defect is suppressed, and good results are obtained. Josephson junctions with excellent junction characteristics can be manufactured with good reproducibility.

Also, in the case of over-etching according to a specific embodiment of the present invention, the over-etching time can be shortened as compared with the conventional case, which also becomes a factor for improving the bonding characteristics and the production efficiency. improves.

Further, in the first place, since the present invention uses ECR plasma etching, the gas pressure in the etching chamber can be lower by one to two orders of magnitude as compared with the conventional RIE. Has the effect that it is unlikely that the redeposition itself will occur.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a characteristic portion of a method of the present invention and an apparatus which can be used in the present invention.

FIG. 2 is an explanatory diagram showing the characteristics of a Josephson junction manufactured according to the present invention and the positions at which each sample is obtained.

FIG. 3 is an explanatory diagram of an initial stage of a manufacturing process of a Josephson junction.

FIG. 4 is an explanatory view of a state before and after cutting an upper superconductor layer of a Josephson junction into a predetermined planar shape by RIE according to a conventional method.

FIG. 5 is an explanatory diagram of a process leading to completion of a single Josephson junction.

FIG. 6 is an explanatory diagram of a step of attaching a wiring layer to an upper superconductor of a Josephson junction.

FIG. 7 is an explanatory diagram of a residue that may be generated as a result of RIE.

FIG. 8 is a diagram illustrating characteristics of a Josephson junction manufactured by a conventional method and sample acquisition positions.

[Explanation of symbols]

 10 Pre-etched sample, 11 Etched sample, 21 Lower superconductor layer, 22 Tunnel barrier tank, 23 Upper superconductor layer, 27 Joint area defining resist, 30 ECR etcher, 31 Etching chamber, 32 Plasma generation chamber, 33 High frequency Power supply, 34 microwave power supply, 35 main coil, 36 auxiliary coil, 37 substrate holder, 38 plasma, 39 waveguide, 101 ECR plasma etching process.

Continued on the front page (72) Inventor, Tadashi Kurosawa 1-1-4 Umezono, Tsukuba, Ibaraki Pref.

Claims (4)

[Claims] After a lower superconductor layer, a tunnel barrier layer, and an upper superconductor layer are sequentially laminated to form a laminated structure, the upper superconductor layer is provided with an electron cyclotron over a depth up to the tunnel barrier layer. Etching the upper superconductor layer into a predetermined planar shape by etching with a resonance plasma etching method; and a method of manufacturing a Josephson junction. 2. The method according to claim 1, wherein when the upper superconductor layer is etched by the electron cyclotron resonance plasma etching method, the upper superconductor layer has a depth to reach the tunnel barrier layer. Over-etching is further performed by an over-etching time Δt longer than a reference etching time t required for over-etching; however, the over-etching time Δt is not more than 20% of the reference etching time t. Method. 3. The method according to claim 1 or 2, wherein:
The tunnel barrier layer is made of a material having resistance to the electron cyclotron resonance plasma etching and functioning as an etching stop layer. 4. The method according to claim 1, wherein said upper superconductor layer to be subjected to electron cyclotron resonance plasma etching is made of a niobium or niobium nitride-based material; and said tunnel barrier layer is made of aluminum oxide. Being a method.