JPH1098110A - Manufacture of semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can cope with plural kinds of load, while preventing rise of manufacturing cost due to increase in the number of masks used in the manufacturing process. SOLUTION: By impurity ion implantation with the first ion implantation mask, plural depression-type MOS transistor Td are formed on a chip 11, and by impurity ion implantation with the second ion implantation mask, a part of plural depression type MOS transistors Td is changed in to an enhancement type MOS transistor T1, thus an internal circuit is configured. As a switch element Tr3 which selects whether a high voltage exceeding a power source voltage VDD is applied or not to an output terminal To1 of the chip 11, a high-voltage-resistant enhancement type MOS transistor is formed with the first ion implantation mask, when a high voltage is not applied, and a depression-type MOS transistor is formed with the first and second ion implantation masks, when the high voltage is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an output circuit of a semiconductor device. In recent years, semiconductor devices have become increasingly sophisticated and multifunctional, and load circuits of various specifications are connected to general-purpose products. In such an output circuit of a general-purpose semiconductor device, as one method for enabling an output operation corresponding to various types of load circuits, an optimum output for a connected load circuit is obtained by changing a mask in a manufacturing process. The circuit is configured. And it is necessary to reduce the manufacturing cost of such a semiconductor device.

[0002]

2. Description of the Related Art An example of an output circuit of a conventional general-purpose semiconductor device is shown in FIG. In the output circuit 2 of the semiconductor device 1, the power supply Vcc is supplied to the source of the open drain type P-channel MOS transistor Tr1, the data D is input from the internal circuit to the gate, and the drain is connected to the output terminal To1.

When the data D becomes L level and the output transistor Tr1 is turned on, H level output data is outputted from the output terminal To. When the data D becomes H level, the output transistor Tr1 is turned off. You.

A load circuit, for example, a fluorescent display tube 3 is connected to the output terminal To. In the semiconductor device 1 for driving the fluorescent display tube 3, a high resistance R is connected between the output terminal To1 and the terminal To2, and a terminal T is connected from an external circuit.
A voltage of -30 V is supplied to o2.

When the output transistor Tr1 is turned off, the high resistance R acts as a pull-down resistance, and the voltage level of the output terminal To becomes -30V. By such an operation, for example, either the power supply Vcc level of 5 V or -30 V is output from the output terminal To1, and the fluorescent display tube 3 is driven based on the potential difference.

In this semiconductor device 1, when connecting a load circuit which does not require the connection of the pull-down resistor R to the output terminal To, the wiring 4 for connecting the pull-down resistor R to the output terminal To is not provided. .

Whether or not to provide the wiring 4 is determined by changing the mask for patterning the aluminum wiring of the semiconductor device 1 in the manufacturing process. By changing the mask in such a manufacturing process, the semiconductor device 1 including the output circuits corresponding to a plurality of types of loads is configured.

[0008]

In the semiconductor device 1 as described above, a mask for patterning aluminum wiring is used in order to select whether or not to provide the wiring 4 and configure the output circuit 2 corresponding to a plurality of loads. Is required. Therefore, there is a problem that the number of masks increases and the manufacturing cost increases.

An object of the present invention is to provide a semiconductor device capable of coping with a plurality of types of loads while preventing an increase in manufacturing cost due to an increase in the number of masks used in a manufacturing process, and a method of manufacturing the same. .

[0010]

According to the first aspect of the present invention, a plurality of enhancement type or depletion type MOS transistors are formed on a chip by implanting impurity ions using a first ion implantation mask, and a second ion implantation mask is formed. By the implantation of the impurity ions through the mask, a part of the plurality of enhancement-type or depletion-type MOS transistors is changed to a depletion-type or enhancement-type MOS transistor, thereby forming an internal circuit. As a switch element for selecting whether or not to apply a high voltage exceeding a power supply voltage to an output terminal of the chip, when the high voltage is not applied, a high withstand voltage enhancement type MOS transistor is provided by the first ion implantation mask. Is formed, and when the high voltage is applied, a depletion type MOS transistor is formed by the first and second ion implantation masks.

According to a second aspect of the present invention, there is provided a semiconductor device in which a depletion type MOS transistor and an enhancement type MOS transistor are provided in an internal circuit. Is provided in the output circuit, and the switch element
When the high voltage is not applied, the process comprises a high breakdown voltage enhancement type MOS transistor formed in the process of manufacturing the enhancement type MOS transistor of the internal circuit, and when the high voltage is applied, the process of manufacturing the depletion type MOS transistor of the internal circuit. And a depletion-type MOS transistor formed by

According to a third aspect of the present invention, an enhancement type MOS
In the switch element constituted by a transistor, a low dose is set near a gate in a drain region or a drain / source region to which a high voltage is applied.

(Function) In the first and second aspects, the switch element provided in the output circuit is an enhancement type MOS transistor and a depletion type M transistor constituting an internal circuit.
It is formed simultaneously in the same process as the OS transistor.

According to the third aspect of the present invention, in the enhancement type MOS transistor constituting the switch element, the drain region or the drain / source region near the gate is made to have a low dose, thereby ensuring the withstand voltage.

[0015]

FIG. 1 shows an outline of a semiconductor device embodying the present invention. The semiconductor device 11 has a mask RO
M (MROM) 12 and CPU 13 are provided.
Data D output from the PU 13 is output from the output terminal To1 via the output circuit 14.

The output terminal To1 is connected to a fluorescent display tube 3 as a load circuit, and the terminal To2 is supplied with -30 V from an external circuit to drive the fluorescent display tube 3. FIG. 3 shows a specific configuration of the output circuit 14 and the mask ROM 12 of the semiconductor device 11. The mask ROM 12 uses an ion implantation program method in which cell information is written by selecting, in a manufacturing process, whether an N-channel MOS transistor constituting a storage cell is an enhancement type cell transistor Te or a depletion type cell transistor Td. Be composed.

In the manufacturing process of the above cell transistor, as shown in FIG. 3, first, all the cell transistors are ion-implanted with N-type impurities based on patterning using a predetermined first ion implantation mask, and depletion is performed. It is formed as a type cell transistor Td.

Next, as shown in FIG. 4, in order to form the cell transistor Te, a P-type impurity is ion-implanted into the selected cell transistor Td based on the patterning using the second ion implantation mask, and the enhancement is performed. Type cell transistor Te is formed.

The cell information read from the mask ROM 12 is input to the CPU 13, and the data D is output from the CPU 13 to the output circuit 14. In the output circuit 14, the data D is input to the gate of an output transistor Tr2 composed of a P-channel MOS transistor, the source is connected to the power supply VDD, and the drain is connected to the output terminal To1.

The output terminal To1 is connected to the source of a switching element Tr3 composed of an enhancement type P-channel MOS transistor, the power supply VDD is supplied to the gate of the switching element Tr3, and the drain of the switching element Tr3 has a high resistance value. It is connected to the terminal To2 via a pull-down resistor R.
The transistor Tr3 is formed as a high withstand voltage type in which the drain and source regions have a low dose near the gate and can withstand a potential difference of -30V. Then, the power supply VDD is supplied to the gate, so that the gate is always kept in the off state.

In the semiconductor device 11 configured as described above,
A voltage of -30 V is supplied to the terminal To2 from the external circuit,
When the output transistor Tr2 of the output circuit 14 is turned on by the data D output from the PU 13, an output signal of the power supply VDD level is output from the output terminal To1, and when the output transistor Tr2 is turned off, -30V is output from the output terminal To1. Is output. The liquid crystal display device 3 is driven by such an output signal.

At this time, -30 is connected to the terminal To2 as described above.
Even if the voltage of V is supplied, the switching element Tr3 has a sufficient withstand voltage, so that the destruction of the switching element Tr3 is prevented.

When the semiconductor device 11 is used by connecting a load circuit which requires connection of a pull-down resistor R to the output terminal To1, an enhancement type is formed in the process of forming the cell transistor Te. Using the second ion implantation mask, P-type impurities are ion-implanted to make the switch element Tr3 depletion-type, thereby forming the output circuit 14.

If the switching element Tr3 is of the depletion type, the switching element Tr3 is always turned on even when the power supply VDD is supplied to the gate, so that the output terminal To1 and the terminal To2 are connected via the pull-down resistor R. . Therefore,
The pull-down resistor R is connected to the output terminal To1.

The output circuit 14 of the semiconductor device 11 formed by the above-described manufacturing process has the following effects. (A) Selection of whether the switching element Tr3 of the output circuit 14 is of the enhancement type or of the depletion type using an ion implantation mask for selecting whether the cell transistor of the mask ROM 12 is of the enhancement type or of the depletion type. Can be. Therefore, the mask R
Since there is no need to separately provide a mask for forming the output circuit 14 in addition to the mask for forming the cell transistor of the OM 12, the manufacturing cost can be reduced. (B) If the switching element Tr3 is a depletion type,
A pull-down resistor R can be connected to the output terminal To1. If the switching element Tr3 is of an enhancement type, the connection between the output terminal To1 and the pull-down resistor R is cut off. At this time, since the switching element Tr3 has a low dose in the vicinity of the gate electrode in the source / drain region, a sufficient breakdown voltage can be secured.

Although the pull-down resistor R is formed in the semiconductor device 11 in the above embodiment, if the pull-down resistor R is an external element of the semiconductor device 11 as shown in FIG. The switching element Tr3 may be connected between the output terminal To1 and the terminal To2.

Since the potential of the switching element Tr3 is particularly concentrated between the drain region to which the pull-down resistor R is connected and the gate, the dose is reduced only in the drain region Dr near the gate G as shown in FIG. It is good also as a structure which reduces.

In the above embodiment, the output circuit is constituted by P-channel MOS transistors. However, the same concept can be realized in the case of using N-channel MOS transistors. Further, the present invention can be applied to an output circuit that applies a high voltage to an output terminal by a pull-up resistor.

The technical ideas that can be grasped from the above-described embodiment other than the above-mentioned claims will be described below together with their effects. (1) The method of claim 2, wherein the enhancement-type MO
The S transistor and the depletion type MOS transistor were formed at the same time in the manufacturing process of the enhancement type MOS transistor and the depletion type MOS transistor constituting the cell transistor of the mask ROM. A switch element can be formed using a mask for forming a cell transistor of a mask ROM.

[0030]

As described in detail above, the present invention prevents an increase in manufacturing cost due to an increase in the number of masks used in a manufacturing process, and enables an output circuit of a semiconductor device capable of coping with a plurality of types of loads. The manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment.

FIG. 3 is a cross-sectional view illustrating a transistor of one embodiment.

FIG. 4 is a cross-sectional view illustrating a transistor of one embodiment.

FIG. 5 is a circuit diagram showing a modification of the output circuit.

FIG. 6 is a cross-sectional view showing a modification of the high withstand voltage enhancement type MOS transistor.

FIG. 7 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 11 chip 14 output circuit Td depletion type MOS transistor Te enhancement type MOS transistor Tr3 switch element To1 output terminal VDD power supply

Claims (3)

[Claims] A plurality of enhancement-type or depletion-type MOS transistors are formed on a chip by implanting impurity ions with a first ion implantation mask, and the impurity ions are implanted with a second ion implantation mask. A method of manufacturing a semiconductor device in which a part of a plurality of enhancement type or depletion type MOS transistors is changed to a depletion type or enhancement type MOS transistor to form an internal circuit, wherein a high voltage exceeding a power supply voltage is applied to an output terminal of the chip. When the high voltage is not applied as a switch element for selecting whether or not to apply a voltage, a high withstand voltage enhancement type MOS transistor is formed by the first ion implantation mask, and when the high voltage is applied, For the first and second ion implantation Method of manufacturing a semiconductor device and forming a depletion type MOS transistor by disk. 2. A semiconductor device comprising a depletion type MOS transistor and an enhancement type MOS transistor in an internal circuit, wherein a switch element for selecting whether or not to apply a high voltage exceeding a power supply voltage to an output terminal is provided. In the output circuit, the switch element is constituted by a high breakdown voltage enhancement type MOS transistor formed in a manufacturing process of the enhancement type MOS transistor of the internal circuit when the high voltage is not applied, and the switch element is applied when the high voltage is applied. A semiconductor device comprising a depletion type MOS transistor formed in a manufacturing process of a depletion type MOS transistor of an internal circuit. 3. A switch element comprising an enhancement type MOS transistor, wherein a dose near the gate is low in a drain region or a drain-source region to which a high voltage is applied.
13. The semiconductor device according to claim 1.