JPH1098098A - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid as much as possible the occurrence of crystal defects caused by thermal stress strain near the interface between a substrate and a CVD oxide film, when in order to form an element isolation region of trench structure in a semiconductor substrate, performing of thermal process after the CVD oxide film is buried in the inside of trench of the substrate. SOLUTION: When forming an element isolation region in a semiconductor device, including at least one element on a main surface of a semiconductor substrate 10, a trench 15 of a specified depth for element isolation is formed on the main surface of the semiconductor substrate, and on a side wall surface and a bottom surface of the trench 15, impurity ions of element having a lattice constant smaller than substrate configuration element are implanted, for forming an impurity ion implantation layer 16. Then a CVD oxide film 17 is buried inside the trench. Then, a thermal process is performed such that the impurity ion implantation layer inside the trench is combined with the configuration element of the substrate, so as to form a combination layer. Thus thermal stress of the substrate and the CVD oxide film is relaxed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device manufactured thereby, and more particularly to a method of forming an element isolation region having a trench structure and a method of forming an element isolation region having a trench structure formed thereby. Regarding the structure.

[0002]

2. Description of the Related Art Element isolation in a semiconductor device exists to prevent electrical interference between elements so that individual elements can be controlled completely independently during operation of the elements. As long as they are arranged, the area of the element isolation region relatively increases as the size of the element decreases.

Conventionally, as a method for forming an element isolation region,
For example, a method of forming a field thermal oxide film by a LOCOS (Local Oxidation of Silicon) method or an STI (Shallo
2. Description of the Related Art There is known a method of forming an element isolation region having a trench (groove) structure by a Trench Isolation method.

In a bipolar integrated circuit, trench isolation which can reduce an isolation region and a parasitic capacitance is adopted as an element isolation technique. In the trench isolation, a device is isolated by forming a groove in a semiconductor substrate and burying a polycrystalline silicon layer in the groove via an insulating film.
No. 25947.

On the other hand, since element isolation in a CMOS integrated circuit does not require a deep isolation like a trench, a field oxide film obtained by improving a selective oxidation method is usually used. Tend to adopt.

In particular, when the element design of a semiconductor device of a submicron level is considered in the design rule, the field thermal oxide film is oxidized in a lateral direction called a bird's beak, and a pattern conversion difference with respect to an exposure pattern cannot be ignored. The adoption of a device isolation region having a structure is being studied.

FIGS. 3A to 3D show a substrate (semiconductor wafer) in a main step of a method for forming an element isolation region when a conventional trench isolation is employed in a CMOS integrated circuit or a BiCMOS integrated circuit.
2 shows the cross-sectional structure of the device.

First, as shown in FIG. 3A, a main surface of a P-type silicon substrate 50 is thermally oxidized to form a thermal oxide film 51, and then polycrystalline by LP-CVD (low pressure vapor phase epitaxy). A silicon film 52 and a CVD oxide film 53 are sequentially formed. This CVD oxide film 53 becomes a mask material when etching the substrate in a later step.

Next, a resist is coated on the CVD oxide film 53, and is exposed and developed to form a resist pattern 54.
Is formed, and RIE is performed using this resist pattern as a mask.
The above-mentioned CVD oxide film 53, polycrystalline silicon film 52, anisotropic etching using (reactive ion etching).
By sequentially etching the thermal oxide film 51, an opening 54a is formed by opening a position where a groove is to be formed.

Next, after the resist pattern 54 is removed by ashing, as shown in FIG. 3B, the semiconductor substrate 50 is anisotropically etched by RIE using the CVD oxide film 53 as an etching mask. A trench 55 for element isolation having a predetermined depth is formed on the main surface.

Next, as shown in FIG. 3C, in order to bury an insulating film in the trench 55, an LP-CV
By a method D, a 1.0 μm CVD oxide film 56 is deposited on the inside of the trench and on the entire surface of the CVD oxide film 53.

Since the volume of the CVD oxide film 56 shrinks due to heating in a later step, the CVD oxide film 56 is about 90% in advance at this time.
Heat treatment is performed at a temperature of 0 ° C. or more for about 1 hour. Thereafter, the CVD oxide film 56 and the CVD oxide film 53 are removed until the surface of the polycrystalline silicon film 52 is exposed, and the polycrystalline silicon film 52, the thermal oxide film 51 and the substrate 50 are removed.
The element isolation region is formed by leaving (embedding) the CVD oxide film 56 inside the trench 55 of FIG.

Further, after forming an impurity region (not shown) of a device (for example, a MOS transistor) in a surface layer portion (device region) other than the device isolation region, the device is completed. However, as described above, when heat treatment is performed at the time when the CVD oxide film 56 is deposited,
Due to the difference in thermal stress between the two, near the interface between them (especially substrate 5)
In the vicinity of the bottom corner of the trench (0), crystal defects 58 are likely to occur due to thermal stress distortion, the breakdown voltage of the element isolation region is reduced, and the manufacturing yield is reduced.

[0014]

As described above, the conventional method for forming an element isolation region involves a process of embedding a CVD oxide film in a trench of a semiconductor substrate and then performing a heat treatment in the vicinity of the interface between the substrate and the CVD oxide film. Therefore, there is a problem that crystal defects due to thermal stress distortion are easily generated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when performing a heat treatment after embedding a CVD oxide film in a trench of a substrate to form a trench structure element isolation region in a semiconductor substrate, Manufacturing of a semiconductor device which makes it difficult to generate crystal defects due to thermal stress distortion near an interface between a substrate and a CVD oxide film, prevents a decrease in breakdown voltage of an element isolation region, and can produce a highly accurate element isolation region at a high yield. The aim is to provide a method.

[0016]

According to the method of manufacturing a semiconductor device of the present invention, when forming an element isolation region in a semiconductor device including at least one or more elements on a main surface of a semiconductor substrate, the method comprises the steps of: Forming a trench for element isolation having a predetermined depth, and implanting impurity ions of an element having a lattice constant smaller than the lattice constant of a constituent element of the semiconductor substrate into sidewalls and a bottom surface of the trench, A step of burying a CVD oxide film inside the trench, and thereafter, performing a heat treatment to combine the implanted layer with the impurity element on the inner surface of the trench and a constituent element of the semiconductor substrate to form a bonding layer; And a step of reducing thermal stress with the CVD oxide film.

Further, the semiconductor device of the present invention is an element isolation region in a semiconductor device including at least one element on a main surface of a semiconductor substrate, and is formed at a predetermined depth on the main surface of the semiconductor substrate. A trench for element isolation, formed on sidewalls and a bottom surface of the trench, and an impurity ion of an element having a lattice constant smaller than a lattice constant of a constituent element of the semiconductor substrate and a constituent element of the semiconductor substrate are combined. And a CVD oxide film embedded in the trench and subjected to a heat treatment, wherein the bonding layer is a thermal stress relieving layer for relieving thermal stress between the semiconductor substrate and the CVD oxide film. It is characterized by.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1A to 1D and FIGS. 2A to 2C illustrate main steps of a method for forming an element isolation region according to a first embodiment of a method for manufacturing a semiconductor device of the present invention. 2 shows a cross-sectional structure of a semiconductor substrate.

First, as shown in FIG. 1A, a first insulating film 11, a polycrystalline semiconductor film 12,
A second insulating film 13 is sequentially formed by a P-CVD method.
In this case, the first insulating film 11 is, for example, a thermal oxide film having a thickness of 50 nm, and the polycrystalline semiconductor film 12 is, for example, LP-C
The second insulating film 13 is a polycrystalline silicon film having a thickness of 400 nm formed by the VD method, for example, LP-CVD.
This is a CVD oxide film having a thickness of 400 nm formed by the method.

Thereafter, a resist film having a thickness of, for example, 1.5 μm is applied on the CVD oxide film 13, and a desired portion is exposed and developed to be patterned.
4 is formed.

Next, as shown in FIG. 1B, the CVD oxide film 13, the polycrystalline silicon film 12, and the thermal oxide film 11 are sequentially formed by anisotropic etching using RIE using the resist pattern 14 as a mask. The opening 14a is formed by etching.

Next, after the resist pattern 14 is removed by ashing, as shown in FIG. 1C, the semiconductor substrate 10 is anisotropically etched by RIE using the CVD oxide film 13 as an etching mask. A trench 15 for element isolation having a predetermined depth (700 nm in this example) is formed on the main surface.

Next, as shown in FIG. 1D, impurity ions of an element having a lattice constant smaller than the lattice constant of the constituent elements of the semiconductor substrate 10 are implanted into the inner surface of the trench 15 to a predetermined depth to dope. A layer 16 is formed.

In this embodiment, a silicon (Si) substrate is used as the semiconductor substrate 10, and either carbon (C) ion or boron (B) ion is used as the impurity ion, so that when it is bonded to Si, It becomes smaller than the lattice constant of the crystal.

The above-described ion implantation must be performed under conditions that do not cause secondary defects. When carbon ions are implanted, the acceleration voltage is set to 30 Kev and the dose is set to 10 × 10 ^14.
/ Cm ² .

At the time of the above-described ion implantation, impurity ions are implanted from a direction having a predetermined inclination angle with respect to the main surface of the semiconductor substrate 10 while rotating the semiconductor substrate 10 in a horizontal plane. In addition, ions can be almost uniformly implanted into the bottom surface.

Next, as shown in FIG. 2A, in order to bury an insulating film in the trench 15, an LP-CV
A 1.0 μm CVD oxide film 17 is deposited on the entire surface of the CVD oxide film 13 including the inside of the trench by the method D.

Next, a heat treatment is performed to diffuse the impurity ions of the doping layer 16 (in this example, the carbon implanted layer) on the inner surface of the trench into the inside of the CVD oxide film 17, and the crystal of the substrate 10 and the CVD oxide film 17 is formed. Relieve distortion.

At the same time, as shown in FIG.
At the interface between the substrate 10 and the CVD oxide film 17, the impurity ions are combined with the constituent elements of the substrate (in this example, silicon) to form a bonding layer (in this example, Si—C having a Si—C bond).
A bonding layer 16a is formed.

The lattice constant of the Si—C bonding layer 16a is as follows:
Since it is smaller than the lattice constant of the Si crystal,
It functions as a thermal stress relieving layer having an effect of relieving a thermal stress difference from oxide film 17.

Since the CVD oxide film 17 undergoes volume shrinkage due to heating in a later step, it is preferable to previously perform a heat treatment at a temperature of about 900 ° C. or more for about 1 hour to shrink the volume. In this case, the heat treatment for shrinking the volume of the CVD oxide film 17 and the heat treatment for relaxing the thermal stress may be performed simultaneously.

Further, the Si—C bonding layer 16a has an effect of absorbing impurities at the time of RIE in a later step, and thus also functions as a gettering layer. Thereafter, as shown in FIG. 2C, CMP (Chemical Mechanical Polising;
The polycrystalline silicon film 1 by chemical mechanical polishing or the like.
Oxide film 17 and CVD until the surface of
By removing the oxide film 13 and leaving (burying) the CVD oxide film 17 inside the trenches of the polycrystalline silicon film 12, the thermal oxide film 11, and the substrate 10, an element isolation region is formed in the substrate 10.

Further, after forming an impurity region (not shown) of a device (for example, a MOS transistor) in a surface layer portion (device region) other than the device isolation region, the device is completed. The semiconductor device manufactured as described above has an element isolation region formed at a predetermined depth on the main surface of the semiconductor substrate as an element isolation region in the semiconductor device including at least one element on the main surface of the semiconductor substrate. And impurity ions of an element (in this example, carbon) having a lattice constant smaller than the lattice constant of a constituent element of the semiconductor substrate, formed on sidewalls and a bottom surface of the trench, and a constituent element of the semiconductor substrate. Are bonded to each other (in this example, S
an iC bonding layer) and embedded in the trench,
A thermally treated CVD oxide film, wherein the bonding layer acts as a thermal stress relieving layer for relieving thermal stress between the semiconductor substrate and the CVD oxide film.

When boron ions are used as impurity ions, the bonding layer 16a becomes a Si-B bonding layer. According to the method for manufacturing the element isolation region having the trench structure as described above, when heat treatment is performed after the CVD oxide film is embedded in the trench of the substrate, the difference in thermal stress between the substrate 10 and the CVD oxide film 17 in the trench. Crystal defects due to thermal stress distortion in the vicinity of the interface between the two (particularly in the vicinity of the bottom corner of the trench of the substrate) due to the above-mentioned problems are less likely to occur. An element isolation region with high accuracy can be manufactured with a high yield.

When forming the trench 15 for element isolation on the main surface of the substrate 10 as described above,
May be used to form a trench having a tapered side wall surface.

[0036]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a heat treatment is performed after a CVD oxide film is buried in a trench of a substrate in order to form an element isolation region having a trench structure in a semiconductor substrate. In this case, crystal defects due to thermal stress distortion near the interface between the substrate and the CVD oxide film are less likely to occur, preventing a decrease in breakdown voltage of the element isolation region, and manufacturing a highly accurate element isolation region at a high yield. .

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor substrate in a main step of a method for forming an element isolation region according to a first embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a sectional view showing the structure of the semiconductor substrate in a step following the step of FIG. 1;

FIG. 3 is a cross-sectional view showing a structure of a semiconductor substrate in a main step of a conventional method for forming an element isolation region of a semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate, 11 first insulating film (thermal oxide film), 12 polycrystalline silicon film, 13 CVD oxide film, 14 resist, 15 trench, 16 doping layer, 16a Si-C bond Layer 17: CVD oxide film.

Claims (7)

[Claims] When forming an element isolation region in a semiconductor device including at least one or more elements on a main surface of a semiconductor substrate, a trench for element isolation having a predetermined depth is formed in the main surface of the semiconductor substrate. Implanting an impurity ion of an element having a lattice constant smaller than a lattice constant of a constituent element of the semiconductor substrate into a side wall surface and a bottom surface of the trench; and embedding a CVD oxide film inside the trench. Thereafter, a heat treatment is performed to combine the impurity ion-implanted layer on the inner surface of the trench with a constituent element of the semiconductor substrate to form a bonding layer, thereby reducing a thermal stress between the semiconductor substrate and the CVD oxide film. A method for manufacturing a semiconductor device, comprising: 2. The step of forming the trench includes: forming a first insulating film, a polycrystalline silicon film on the semiconductor substrate,
A step of sequentially forming a second insulating film by a CVD method, a step of opening a desired portion of each of the films, and a step of performing anisotropic etching on the semiconductor substrate using the second insulating film as an etching mask 2. The method for manufacturing a semiconductor device according to claim 1, comprising: 3. The semiconductor substrate is a silicon substrate,
3. The method according to claim 1, wherein the impurity ions are one of carbon ions and boron ions. 4. The step of implanting impurity ions, wherein the impurity ions are implanted from a direction having a predetermined inclination angle with respect to a main surface of the semiconductor substrate while rotating the semiconductor substrate in a horizontal plane. The method of manufacturing a semiconductor device according to claim 1. 5. The method according to claim 1, wherein the step of forming the bonding layer by performing the heat treatment also serves to reduce the volume of the CVD oxide film embedded in the trench. A method for manufacturing the semiconductor device according to any one of the above. 6. An element isolation region in a semiconductor device including at least one or more elements on a main surface of a semiconductor substrate, comprising: an element isolation trench formed at a predetermined depth on the main surface of the semiconductor substrate; A coupling layer formed on a side wall surface and a bottom surface of the trench, wherein an impurity ion of an element having a lattice constant smaller than a lattice constant of a constituent element of the semiconductor substrate is combined with a constituent element of the semiconductor substrate; Embedded and heat treated CVD
A semiconductor device, comprising: an oxide film; wherein the bonding layer is a thermal stress relieving layer that relieves thermal stress between the semiconductor substrate and the CVD oxide film. 7. The semiconductor substrate is a silicon (Si) substrate, the impurity ions are one of carbon (C) ions and boron (B) ions, and the bonding layer is Si—C
7. The semiconductor device according to claim 6, wherein the semiconductor device is one of a bonding layer and a Si-B bonding layer.