JPH0448647A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce number of polishing processes, by forming protruding films, each comprising a conductive and insulating film, on a semiconductor layer, and by forming insulating side walls on both the side parts of each protruding film, and by thereafter depositing a semiconductor film overall and embedding this film in grooves, and by thereafter polishing the semiconductor films through using the protruding films as the last stops. CONSTITUTION:By a CVD method, an SiO2 film 18 of 2000-3000Angstrom in thickness is grown overall. Thereafter, by an RIE method, anisotropic etching is performed. Thereby, the side walls caused by the SiO2 film 18 remaining are formed on both the side parts of a polycrystalline silicon film 9 and a nitride film 10 which are protruded from an N<->-type semiconductor layer 3 and a field insulation film 6. In this case, the SiO2 film 18 remains on the inner peripheral surface of a U-shaped groove 14. Thereafter, polishing is performed using the nitride film 10 as a stopper, after a second polycrystalline silicon film 19 of about 2mum in thickness is grown overall by a CVD method. Then, the side spaces of the nitride film 10 and the first polycrystalline silicon film 9 thereunder are filled with the second polycrystalline silicon film 19. Thereby, the surfaces of the plural films on the N<->-type semiconductor layer 3 are levelled completely.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device equipped with a U-groove for element isolation, the number of polishing steps when forming a semiconductor element is reduced as much as possible, and! A conductive film or a first insulating film and a conductive film are formed on the semiconductor layer 3 and the field insulating film in order to reduce the margin when forming the poles and to planarize the semiconductor device after element formation. '! a step of depositing a film and further depositing a second insulating film; and a step of forming a trench extending in the depth direction inside the semiconductor layer;
a step of forming a third insulating film on the inner surface of the political situation, the conductive layer and the second insulating film, or the first insulating film;
forming a convex film in a desired region of the semiconductor layer and field insulating film by patterning the conductive film and the second insulating film, and forming an insulating sidewall on the sidewall of the convex film; The step of exposing the surface of the semiconductor layer other than the convex region including the insulating film sidewall and the field insulating film, and forming a conductive film or a semiconductor film in at least the region including the groove, The method includes the steps of polishing the thickness of the semiconductor film with the film as the end point, thereby forming a recessed portion formed by the plurality of convex films, and leaving the semiconductor film in the groove.

(Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device provided with a U-groove for element isolation.

[Conventional technology]

In semiconductor devices, U-grooves are sometimes provided to isolate elements. This U-groove is created by forming a groove in the depth direction of a semiconductor substrate, growing an insulating film on the inner surface of the groove, and then growing polycrystalline silicon with good wraparound properties using a vapor phase growth method etc. to fill the inside of the U-groove. Then, the polycrystalline silicon film is mechanically polished to leave the polycrystalline silicon only inside the U-groove.

When forming, for example, a P-type MOS transistor and an NPN junction bipolar transistor separated by such a U-groove, the following steps are generally performed.

FIG. 3 is a cross-sectional view showing a conventional manufacturing process of a semiconductor device.

First, an N° type half body layer 41N− is placed on the semiconductor substrate 40.
A type semiconductor layer 42 is laminated. Then, the N-type semiconductor layer 42
After forming a field insulating film 43 in regions other than the collector contact layer forming region C and base layer forming region B of the bipolar transistor and the transistor forming region M of the bipolar transistor, N-type impurity ions are press-injected and diffused to form the collector. A contact layer 44 is formed on the N- type semiconductor layer 42 (FIG. 3(a)).

Then, after laminating the SiO□ film 45 film chamber 5 film 46, PSG film 47, and photoresist 48 on the whole, the photoresist 48 and the PSG film 47 are patterned to form an opening 49 surrounding the bipolar transistor forming HMA. Form.

Next, using the PSG film 47 and the photoresist 4 days as a mask by reactive ion etching method (1?IE method) etc.,
Anisotropic etching is performed from the nitride film 46 to the inside of the semiconductor substrate 40 to form a U-groove 50 in the thickness direction of each layer (FIG. 3(b)).

After removing the PSGIl 147 remaining on the nitrided M46, an insulating film 5 is formed on the inner surface of the U groove 50 by thermal oxidation.
1 (at this time, no oxide film is formed except for the inner surface of the U groove 50 due to the nitrided M46).
first polycrystalline silicon M5 so as to completely fill the inside of the
After laminating the second polycrystalline silicon film 52, the second polycrystalline silicon film 52 is polished (mechanically polished) to expose the nitride film 46 and the field insulating film 43, and the polycrystalline silicon film 52 remains in the U groove 50 ( Figure 3(c)).

Next, the upper surface of the polycrystalline silicon film 52 within the U-groove 50 is thermally oxidized to grow a silicon oxide film 53 to form a lid on the surface of the U-groove 50 (FIG. 3(d)). Time U groove 5
Since the surface other than the surface of 0 is covered with nitride 846, no oxide film is formed. After this, the nitride film 46 and the SiO2 film 4
5 is removed with phosphoric acid and hydrochloric acid, respectively.

Next, after forming a gate oxide film 54 in the exposed region of the semiconductor layer 42, the gate oxide film 54 except outside the MOS transistor formation region is removed using a resist mask, and then a second polycrystalline silicon M55 is laminated on the entire surface. Thereafter, P-type impurity ions are implanted into the bipolar transistor formation region A, N-type impurity ions are implanted into the MOS transistor formation region M, and a SiO□ film 56 is laminated over the entire structure. Next, N
- on the semiconductor layer 42! 54 to 56 are patterned by photolithography, and at this time the gate insulating film 54 is patterned.
may be left in the gate electrode formation region G, around the emitter formation region E, and on the collector contact layer 44 (FIG. 3(c)), and in the gate electrode formation region G. Polycrystalline silicon film 55 is used as gate electrode 5
7, and the remaining part around the mitter formation region E is used as the base electrode 58.

Thereafter, P-type impurity ions are implanted into the emitter formation region and the MOS transistor formation region M.

Then, the entire Sigh film 59 (and gate insulating film 54
), the Sing film 59 (including the gate insulating film 54 when it remains) is anisotropically etched until the N-type semiconductor layer 42 is exposed, and the polycrystalline silicon film 5
SiO□M59 is left on the side of 5 (FIG. 3(f)).

After this, P-type impurity ions are implanted into the MOS transistor formation region M.

Next, a third polycrystalline silicon film 60 is laminated on the entire surface, and after implanting N-type impurity ions into this, as shown in FIG. 3(g), this third polycrystalline silicon film 60 is The emitter electrode 61 is left on the side of the emitter formation region by etching and used as the emitter electrode 61.

Thereafter, annealing is performed to diffuse the P-type impurity on both sides of the gate electrode 57 in the MOS transistor formation region M to form a source layer S and a drain layer d. At the same time, the P-type impurity implanted into the N-type semiconductor layer 42 on the emitter head E and the P-type impurity in the polycrystalline silicon film 55 around it are diffused into the N-type semiconductor layer 42. A base layer is formed, and an N-type impurity contained in the polycrystalline silicon 60 on the emitter formation region E is diffused into the base layer to form an emitter layer e.

Next, as shown in FIG. 3(h), the glabellar insulating film 6
2 and contact holes 63 to 68 are provided. Then, the source layer S is formed through the contact holes 63 to 68.
, the gate electrode 57, the drain layer d1 collector contact layer 44, the base electrode 58, and the emitter electrode 61, respectively, are formed with wiring electrodes 69 to 74 made of metal such as aluminum.

[Problem to be solved by the invention]

By the way, when forming the semiconductor device 1 by such a method, as shown in FIG.
There is a disadvantage that a step is formed in the region between the drains, and that disconnection and migration are likely to occur in the wiring layer formed thereon.

Further, there is a problem that the emitter electrode 61 of the bipolar transistor protrudes from the base electrode 57, impairing planarization. In this case, it is possible to polish and planarize the third polycrystalline silicon film 60 constituting the emitter electrode 61 in advance, but this increases the number of times of polishing and requires extra time for device formation. Become.

Furthermore, when forming contact holes 63 and 65 on the source layer S and drain layer d of the MOS transistor,
Positional deviations may occur, and a margin must be ensured, which is disadvantageous in that it impedes miniaturization of elements.

Moreover, since polycrystalline silicon films are laminated in each of the steps of filling the U-groove 50, forming the gate electrode 57 and base electrode 58, and forming the emitter electrode 61, There is a problem that the number of forming steps increases.

The present invention was made in view of these problems, and aims to reduce the number of polishing steps as much as possible when forming a semiconductor element, reduce the margin when forming an electrode, and reduce the number of polishing steps when forming a semiconductor element. Semiconductor device after formation! An object of the present invention is to provide a method for manufacturing a semiconductor device that can planarize a semiconductor device and improve the reliability of an electrode formed thereon.

[Means for Solving the Problems] The above problems are solved by the semiconductor layer 3 as illustrated in FIG.
and a step of depositing a conductive film 9 or a first insulating film 8 and a conductive film 9 on the field insulating film 6, and further depositing a second insulating film 1O, a step of forming a groove 14 extending in the horizontal direction, a step of forming a third insulating film 15 on the inner surface of the political condition 14, and a step of forming the conductive layer 9 and the second insulating film 10, or the first insulating film. 8
, forming a convex film in desired areas of the semiconductor layer 3 and field insulating film 6 by patterning the conductive film 9 and the second insulating film 10; A step of forming an insulating sidewall I8 and exposing the surface of the semiconductor layer 3 other than the convex region including the insulating sidewall 18 and the field insulating film 6, and forming a conductive layer in the region including at least the groove 14. After the film or semiconductor film 19 is formed, by polishing the thickness of the semiconductor film 19 using the convex film as the end point, the concave portions formed by the plurality of convex films and the grooves 4 are polished. A semiconductor device l having a step of leaving the semiconductor film 19
This is achieved by the manufacturing method.

[For production]

According to the present invention, the U-shaped groove 1 formed in the semiconductor layer 3
As a step before embedding the polycrystalline semiconductor film 19 etc. in 4,
Conductive film 9 and insulating film 10, or insulating film 8 and conductive film 9
and a convex film made of an insulating film IO is formed on the semiconductor layer 3, an insulating sidewall 18 is formed on the side thereof,
After this, a semiconductor film 19 is deposited on the entire surface and this is applied to the groove 14.
After embedding the semiconductor ff19 with the convex film as the end point.
I try to polish it.

Therefore, the semiconductor film process 9 located on both sides of the convex film is
The conductive film 9 inside the convex film is formed by the insulating sidewall 18.
It will be separated from

Therefore, the conductive layer 9 constituting the convex film is applied as a gate electrode or an emitter electrode, and the surrounding semiconductor M
If 19 is made into an ST and applied as a source electrode, drain electrode, or base electrode, the process of forming a semiconductor film used for the source electrode and the like and the process of patterning the same can be omitted, and the number of steps can be reduced.

Further, the semiconductor element formed by these has a uniform thickness, and the glabellar insulating film formed thereon is flattened. Furthermore, since the base electrode is formed on the side of the emitter electrode in a self-aligned manner, there is no need to perform etching to flatten the emitter electrode and the base electrode.

Furthermore, according to the polishing of the semiconductor film 19, the semiconductor layer 19 remains even in areas where no electrode is formed, and after forming the emitter electrode, base pole, etc., the glabellar insulating film that covers the entire area is raised by the semiconductor layer. As a result, the entire glabellar insulating film including the element formation region is flattened, preventing disconnection and migration of the wiring electrodes formed thereon, and improving reliability of the semiconductor device. Not only that, but multilayer wiring will be promoted.

[Example] The details of the present invention will be explained below based on the drawings.

FIG. 1 is a sectional view showing an embodiment of the semiconductor device manufacturing process of the present invention, in which a P-type MO3) transistor and an NPN
An example of forming a junction bipolar transistor will be described.

Reference numeral l in the figure is an N-type semiconductor substrate made of silicon or the like, and on top of this is an N-type thick conductor layer 2N made of silicon.
- type semiconductor layer 3 is laminated to a thickness of about 1.5 pm and 1.0 μm, respectively, by epitaxial growth method, and the entire surface of N- type semiconductor layer 3 is covered with a 200-layer silicon oxide film (S10 □ A film) 4a is formed, and a nitride film 4b is laminated thereon by CVD method (
Figure 1(a)). In this case, the N-type thick conductor layer 2 becomes a buried layer.

Next, base formation region B, collector contact layer formation region C, and M are formed in the bipolar transistor formation region.
OS) Each transistor formation region M is covered with a resist mask 5, and nitride films 4b and 5 exposed from the resist mask 5 are formed by reactive ion etching (RIE).
While removing the iO1 film 4a, the N-type semiconductor layer 3
0.5 μm to form a recess (first
Figure (b)).

Next, after removing the resist mask 5 by ashing, a silicon oxide film (540, film) 6 is deposited by the CVD method, and this is etched using a chemical polishing method and a hydrofluoric acid buffer until the nitride layer 4b is exposed. And N
The SiO□WI6 remaining in the recessed portion of the −-type semiconductor layer 3 is used as a field insulating film (FIG. 1(C)).

After that, the nitride film 4b and the SiO□ film 4a are removed using phosphoric acid and hydrochloric acid, respectively, and then, using a photoresist (not shown) as an ion implantation protection mask, the collector contact layer forming region C is filled with N-type impurity ions, such as phosphorus, etc. Arsenic ions are implanted and diffused to form a collector contact layer 7 to a depth that reaches the N-type groove conductor layer 2 (FIG. 1(d)).
.

In addition, after forming SiO□M8 to a thickness of about 200 mm over the entire surface by thermal oxidation, a portion of this 5JOz film 8 in the bipolar transistor formation region A is selectively removed by photolithography to form a MOS transistor. SiO□#8 remaining in region M is used as a gate oxide film.

Next, a first polycrystalline silicon film 9 is applied to the entire surface by CVD.
about 3000 people, nitride #10 1000 people, PSG film 1
After growing photoresist 1 to a thickness of about 1 μm, photoresist 1 is grown on it.
2 is applied, exposed and developed to form a window 13 in the area surrounding the bipolar transistor forming area A,
Using this window 13 as a mask, the PSG film 11 and nitride film 10 are anisotropically etched to expose the underlying polycrystalline silicon film 9 (FIG. 1(e)).

Then, using the PS ([11] and photoresist 12 as masks, the polycrystalline silicon film 9, field oxide film layer 2, and upper layer of the semiconductor substrate 1 are etched by the RIE method. is formed in the vertical direction (FIG. 1(f)). In this case, a chlorine-based gas is used as the etching gas.

Next, after controllingly etching the PSG film 11 remaining on the nitride film 10 with hydrofluoric acid, thermal oxidation is performed to form a 5102M1 film with a thickness of approximately 500 to 3000λ on the inner surface of the U groove 14.
form 5. In this case, the parts other than the U groove 4 are protected by the nitride film 10 and are not oxidized (see Fig. 1 (g).
)) Note that before the thermal oxidation, boron ions may be implanted into the Um 14 as necessary to form a channel cut diffusion region in the lower part of the U groove 14.

After this, by using a resist mask (not shown), the U groove 1 is
4, a part of the field insulating film 6, the gate electrode formation region G, and the emitter formation region E, and remove the nitride M10 and polycrystalline silicon M9 exposed from the resist mask by R.
It is removed by etching using the IE method. This results in N
A convex film made of Wi nitride 10 and polycrystalline silicon film 9 is formed on gate oxide film 8 and field oxide film 6 on - type semiconductor layer 3 .

Of these, the polycrystalline silicon film 9 in the gate electrode formation region G
is used as the gate electrode 16, and polycrystalline silicon ff9 in the emitter formation region E is used as the emitter electrode 17.

Next, a 200% SiO
After growth of about 0 to 3,000 layers, anisotropic etching is performed using the EPR method to form SiO2#1 on the sides of the polycrystalline silicon M9 and nitride film 10 protruding from the N-type semiconductor layer 3 and field insulating film 6. Leave the sun to form a sidewall.

In this case, the 5i02 film 18 remains on the inner peripheral surface of the U groove 14.

After this, a second polycrystalline silicon film 19 is formed by CVD method.
After growing to a thickness of approximately 2 μm, polishing is performed using the nitride film 10 as a stopper, and the sides of the nitride M 10 and the first polycrystalline silicon film 9 thereunder are filled with the second polycrystalline silicon film 19. Therefore, the N-type semiconductor layer 3
The upper films are completely flattened. In this case, an amorphous silicon film may be used instead of the second polycrystalline silicon film.

Next, using a photoresist (not shown) as a mask, P-type impurity ions such as boron ions (B'') or boron difluoride ions (BF2'') are applied to form a bipolar transistor.
Implant into the second polycrystalline silicon [1190 e.g. B
When injecting ゛, injection artificial 27 + / ghee 20 k e
V, the dose amount is 5×10 IS/cd. Also,
Polycrystalline silicon film 19 in MOS transistor formation region M
Similar P-type impurity ions are implanted in BF2''
When implanting, the implantation energy is 60 keV and the dose is 5×10'S/cj. Note that the acceleration energy of this ion implantation is such that the impurity is polycrystalline polysilicon 19
However, the acceleration energy is selected to be low in order to prevent it from passing through the nitride film IO and being introduced into the underlying polysilicon 9.

This is followed by wet oxidation at 900'C or 80'C.
High-pressure oxidation at 0 to 850°C is performed to form an iO2 film 20 with a thickness of about 2000 on the top of the second polycrystalline silicon film 19.
(FIG. 1(k)), this SiO□ film 20 is grown as shown in FIG.
It becomes an interlayer insulating film.

Next, a mask is formed using the photoresist 21, and the nitride M10 in the gate electrode formation region G and emitter formation region E is selectively etched and removed using phosphoric acid boiling, and then the photoresist 21 is ashed (the first Figure 1 (1))
.

At this time, since the opening can be formed using the self-alignment line, the pattern of the mask formed by the photoresist 21 can be rough, and sophisticated exposure techniques and precise positioning accuracy are not required.

Then, the gate electrode formation region G of the first polycrystalline silicon film 9 exposed by the removal of the nitride [110] is implanted with an implantation energy of 30 keV and a dose IXIQ''/cj, for example.
Inject phosphorus ions under the following conditions.

Also, the first polycrystalline silicon film 9 in the emitter formation region E
For example, the implantation energy is 60 keV and the dose is 1X.
B'' is injected under the condition of 1014/cd.

The acceleration energy of the ion implantation is set to be low enough to introduce impurity ions into the polycrystalline silicon film 9, but not into the underlying polycrystalline film 19 through the SiO□ film 20. As a result, the ion implantation into the gate electrode formation region B and the ion implantation into the emitter formation region E can be performed using rough resist patterns and self-implanted ions.

After this, annealing is performed at 900° C. for 60 minutes to activate the impurities in the gate electrode 16 and diffuse boron from the second polycrystalline silicon Wi419 on both sides into the N-type semiconductor layer 3 to form the source layer S. , while forming P type diffusion layers 23 and 24 which will become the drain layer d, impurities are diffused from the emitter electrode E and the second polycrystalline silicon film 19 around it into the N- type semiconductor layer 3 to form the base layer. At the same time as forming the P type diffusion layer 25, the boron impurity in the first polycrystalline silicon film in the emitter formation region E is diffused into the N- type semiconductor layer 3 to form the P type diffusion layer 17. Furthermore, by diffusion of impurities through subsequent heat treatment, the diffusion regions of the P-type diffusion layers 25 and 17 are finally connected and electrically connected, forming an external base and an internal base, respectively.

Next, the emitter voltage 8i17 is injected with energy of 60k.
Arsenic ions are implanted under the conditions of eV and a dose of lXl0''/d.

Then, annealing is performed at 1100°C for 30 seconds to diffuse arsenic into the P half-diffusion layer 17-type semiconductor layer 3 and form the emitter layer e.
An N-type diffusion layer 26 is formed.

Note that when these impurity ions are implanted, a mask is formed each time using photoresist, although not particularly shown in the figure. As explained above, the openings in these masks are rough and slightly larger than the openings into which ions are implanted, and are well aligned, so there is no need to make them highly accurate. In other words, impurities can be introduced using the Selfa line, which is convenient for miniaturization.

Next, as shown in FIG. 1(m), the photoresist 27
After forming a mask and patterning a part of the SiO□ film 20 around the gate electrode 16 and emitter electrode 17 to form contact holes 28 to 31 for the source, drain, collector, and base, the gate electrode 16 and Electrodes 32 to 37 made of a metal material such as aluminum are formed on the emitter electrode 17 and the second polycrystalline silicon film 19 exposed from the contact holes 28 to 31 (FIG. 1(n)).

Note that, of the second polycrystalline silicon film 19, those existing on both sides of the gate electrode 16 serve as a source extraction electrode 38a and a drain extraction electrode 38b, and those around the emitter electrode 17 serve as a base extraction electrode 39.

Through the above steps, a P-type MO3) transistor and an NPN-type bipolar transistor are formed.

According to this, in the MOS transistor formation region M, since the gate is formed on the side of the pole 16 by self-alignment with polycrystalline silicon 11 to 19 containing high concentration impurities by polishing, N-type Not only does it become unnecessary to form a highly concentrated diffusion layer in the semiconductor layer 3, but also the interlayer insulating film 20 laminated in this region becomes the source lead electrode 38a.
, since it is raised by the drain extraction electrode 38b,
The MOS transistor is formed flat.

Furthermore, in the bipolar transistor formation region A,
During polishing, the emitter electrode 17 is embedded in the base extraction electrode 39 in a self-aligned manner and is formed flat, so there is no need to add a new process for flattening them.

Furthermore, according to this polishing, the second polycrystalline silicon film 19 remains even in areas where no elements are formed, and the glabellar insulating film 2o formed thereon is raised, so that the glabellar insulating film 20 is formed. In this state, the entire surface including the element formation region can be planarized, and occurrence of disconnection or migration in the multilayer wiring formed thereon can be suppressed.

Moreover, the source lead electrode 38a and the drain lead electrode 38
b and the base extraction electrode 39 can be extended to the top of the field insulating film 6, and aluminum 1t8ii can be formed on this, so it is necessary to consider the margin when forming the contact holes 28 to 31 in the interlayer insulation 1I120. Since the source layer S and drain layer d1 of a MOS transistor or the base layer of a bipolar transistor can be narrowed, the capacitance due to the PN junction can be reduced, and the device can be made closer to the proportional shrinkage side, allowing for miniaturization of the device. becomes possible.

In addition, since the source, drain, and base are formed by diffusion of impurities ion-implanted into single-crystal silicon [19], ions do not enter the N-type semiconductor substrate immediately after ion implantation, and shallow sources and Since it becomes possible to form a junction between the drain and the base, in this sense as well, it can be approached to a proportionally reduced scale, making it possible to miniaturize the device.

Note that the field oxide film 6 in the above embodiment is as follows:
A groove on the top of the N-type semiconductor layer 3 is formed, and 1! !
! Although the edge film is filled in, this step requires polishing and is time consuming, so a field oxide film formed by selective oxidation may also be used.

However, since the field oxide film formed by the selective oxidation method protrudes from the N- type semiconductor layer 3, it is preferable to perform some kind of treatment to flatten it.

For example, as shown in FIG. 2(a), an N-type semiconductor layer 3
About 200 F5in2 films and nitride I on top! ! After forming, the nitride film 4d is patterned by photolithography to leave the nitride film 4d in the MOS transistor formation region M, the base formation region B, and the collector contact formation region C.

Thereafter, using the nitride film 4d as an oxidation prevention mask, the surface of the N- type semiconductor layer 30 is selectively thermally oxidized to form an F iO□ film 6a with a thickness of about 5000 nm (FIG. 2(b)).

Next, the selectively formed SiO□ film 6a is etched with hydrofluoric acid so that its surface becomes flat with the surface of the N- type semiconductor layer 3 (FIG. 2(C)).

After this, if the nitride film 4d is removed with phosphoric acid boiling and the thin 5-hot film 4c is controlled-etched with hydronic acid, a state similar to that shown in FIG. 1(c) will be obtained. will be formed.

Alternatively, as shown in FIG. 1(b), about 200 people form an F5i02 film 4a and a nitride film 4b on the N-type semiconductor layer 3, and then pattern the nitride film 4b by photolithography. , further using the same patterning
After forming steps of about 2,000 to 3,000 steps in the N-type semiconductor layer by anisotropic etching, the surface of the N- type semiconductor layer 3 is selectively oxidized by thermal oxidation using the nitride film 4b as an oxidation prevention mask to form steps of about 5,000 to 6,000 steps. Forms a thermal oxide film on humans. The surface of the thermal oxide film rises from the initial semiconductor interface due to volume expansion, but since a 2,000 to 3,000 level difference is initially formed in the N-type semiconductor layer, there is a method that can flatten the surface exactly.

However, the surface of the field oxide is not necessarily as shown in Figure 1 (j
), the problem will be solved if over-polishing of about 2,000 to 3,000 is applied and even the tops of the low protrusions formed on the N-type semiconductor are exposed.

[Effects of the Invention] As described above, according to the present invention, as a step before burying a polycrystalline semiconductor film or the like in a U-shaped groove formed in a semiconductor layer, a conductive film or a conductive TG and an insulating film are formed. A convex film is formed on the semiconductor layer, an insulating sidewall is formed on the side of the film, a semiconductor film is deposited on the entire surface, the trench is filled with this, and the convex film is formed on the semiconductor layer. Since the semiconductor film is polished with the film as the end point, the semiconductor films located on both sides of the convex film are separated from the conductive film within the convex film by the insulating sidewalls.

Therefore, if the conductive layer constituting the convex film is applied as a gate electrode or emitter electrode, and the semiconductor film around it is made conductive and applied as a source electrode, drain electrode, or base electrode, it can be used as a source electrode, etc. The process of forming a semiconductor film and the process of patterning it can be omitted, making it possible to significantly reduce the number of man-hours.

Moreover, the semiconductor element formed by these has a uniform thickness, and the interlayer insulating film formed thereon can be flattened. Moreover, since the emitter electrode is embedded in the base electrode in a self-aligned manner and is formed flat, there is no need to perform polishing to make the space between the emitter electrode and the base electrode flat, reducing the number of steps. It becomes possible.

Furthermore, according to polishing of the semiconductor film, the semiconductor layer remains on the slope where no electrode is formed, and the interlayer insulating film that covers the entire surface is raised by the semiconductor layer after forming the emitter electrode, base electrode, etc. In addition, the entire glabellar insulating film, including the element formation head, is flattened, and the wiring formed on this film can be prevented from disconnecting or migration, which improves the reliability of semiconductor devices. can be increased.

In addition, as shown in FIG. 1 (Part 4) (1), the insulating film 1
By selectively removing 0, the gate voltage F'4911
Since the region G and the emitter forming slope E can be formed by self-alignment, the cost can be reduced by omitting a mask layer, and there is also the advantage that alignment precision is not required, which is advantageous for the formation of finer elements.

Furthermore, although the above description has been made regarding P-MOS and NPN type bipolar transistors, it is of course applicable to N-MOS or PNP type bipolar transistors, or a composite integrated circuit of all of these.

[Brief explanation of the drawing]

FIG. 2 is a cross-sectional view showing the process of an embodiment of the present invention; FIG. 2 is a cross-sectional view showing the process of processing a substrate used in the present invention; FIG. 3 is a cross-sectional view showing the conventional manufacturing process of a semiconductor device. FIG. (Explanation of symbols) 3...N-type semiconductor layer, 6.6a...srozM (field insulating film, 8
...Si0g film (gate oxidation M), 9...polycrystalline silicon (conductive m1ll), 10...nitriding! (insulating film), If-PSGg, 12...photoresist, 13...window, 4...groove, 5...5i (h film (insulating film), 8...5iO7 film (side wall) ), 9... Polycrystalline silicon (semiconductor film) 0... 5iOz film (interlayer insulating film). Engineering, 27... Photoresist, 3.24.25... P-type diffusion layer, 6...・N-type diffusion layer, 8 to 31... Contact hole, 2 to 37... Electrode, 8a... Source extraction electrode, 8b... Drain extraction electrode, 9... Base extraction electrode. Applicant Fujitsu Limited

Claims (1)

[Claims] On the semiconductor layer (3) and the field insulating film (6),
a step of depositing a conductive film (9), or a first insulating film (8) and a conductive film (9), and further depositing a second insulating film (10); A groove extending in the depth direction (14
), a step of forming a third insulating film (15) on the inner surface of the groove (14), and a step of forming a third insulating film (15) on the inner surface of the groove (14); By patterning the first insulating film (8), the conductive film (9), and the second insulating film (10), a convex shape is formed in desired regions of the semiconductor layer (3) and the field insulating film (6). forming an insulating sidewall (18) on the sidewall of the convex film, and forming a convex region including the insulating sidewall (18) and the semiconductor layer other than the field insulating film (6); (3) exposing the surface of the semiconductor film (19) after forming a conductive film or a semiconductor film (19) in a region including at least the groove (14); A method for manufacturing a semiconductor device, comprising a step of polishing the thickness to form a recess formed by a plurality of the convex films and leaving the semiconductor film (19) in the groove (14).