JPH1098097A - Field shield element isolation forming method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen an element isolating region in width, without deteriorating it in withstand voltage by a method, wherein a conductive film is filled into a V-shaped groove whose inner wall is covered with a field shield gate insulating film to form a field sealed electrode. SOLUTION: A resist pattern 32 is formed on the surface of a silicon substrate 31 except for an element isolating region. Then, the silicon substrate 31 is etched using the resist pattern 32 as a mask, whereby a V-shaped groove 33 is provided to the surface of an element-isolating region of the silicon substrate 31. Then, the resist pattern 32 is separated to be removed, and then the silicon substrate 31 is subjected to dry oxidation, whereby a field shield gate oxide film 34 is formed on the inner wall of the V-shaped groove 33 and the surface of the silicon substrate 31. The V-shaped groove 33 is filled with a polysilicon film to form a field electrode 35 buried deep in the silicon substrate 31. By this setup, an element-isolating region can be lessened in width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a field shield element isolation.

[0002]

2. Description of the Related Art A field shield element isolation method has been developed as one of element isolation techniques in a semiconductor device. In this element isolation method, a conductive film (field shield electrode) is provided on an element isolation region of a semiconductor substrate via an insulating film (field shield gate insulating film), and the potential of the conductive film is fixed. This is a method of fixing the surface potential of the semiconductor substrate in the isolation region to perform electrical isolation. A conventional method for forming the field shield element isolation is disclosed in Japanese Patent Application Laid-Open No. 2-216848. Hereinafter, this conventional forming method will be described with reference to FIGS.

In the conventional method, first, as shown in FIG. 6A, a silicon oxide film 12 for forming a field shield gate oxide film is formed on a surface of a semiconductor substrate 11. Next, a conductive film (polycrystalline silicon film or amorphous silicon film) 13 for forming a field shield electrode is formed on the silicon oxide film 12. Next, as shown in FIG. 6B, a resist pattern 14 is formed on the conductive film 13 in the element isolation region by a known photolithography technique. Then, using the resist pattern 14 as a mask, the conductive film 1 is used.
By patterning the silicon oxide film 3 and the silicon oxide film 12 by dry etching, the field shield gate oxide film 12a made of the residual silicon oxide film 12 and the residual silicon oxide film 12a are formed on the element isolation region of the semiconductor substrate 11 as shown in FIG. Field shield electrode 1 made of conductive film 13
3a is formed.

Next, after removing the resist pattern 14 as a mask material, a silicon oxide film 15 is formed on the entire surface as shown in FIG. Then, the entire surface of the silicon oxide film 15 is etched back by the anisotropic dry etching technique, so that the remaining silicon oxide film 15 is formed on the side wall of the field shield electrode 13a as shown in FIG.
Is formed. The side wall spacer 15a is connected to the exposed field shield electrode 1
It is formed for the purpose of separating and protecting the side wall of 3a from the gate electrode of the device formed on the device active region of the semiconductor substrate 11.

[0005] Thus, the step of forming the field shield element isolation portion is completed. From now on, a step of forming an element in the element active region of the semiconductor substrate 11 is performed. First, as shown in FIG. 7B, an oxide film 16 for forming a gate oxide film of the device is formed on the exposed surface of the active region of the semiconductor substrate 11 and the surface of the field shield electrode 13a. Subsequently, a conductive film 17 for forming a gate electrode of the device is formed on the entire surface of the semiconductor substrate 11. Further, a resist pattern 18 is formed on the conductive film 17 so as to correspond to a gate electrode forming portion of the device. And this resist pattern 1
By patterning the conductive film 17 and the oxide film 16 using the mask 8 as a mask, as shown in FIG. 7C, the gate oxide film of the device consisting of the remaining oxide film 16 is formed in the active region of the semiconductor substrate 11 at the position where the gate electrode is formed. Then, a gate electrode 17a of an element composed of 16a and the remaining conductive film 17 is formed.
Thereafter, ion implantation is performed to form impurity diffusion layers 19 corresponding to source / drain regions on both sides of the gate electrode 17a in the element active region of the semiconductor substrate 11, and sidewall spacers 20 are formed on the side walls of the gate electrode 17a. To form

[0006]

However, in the above-described conventional field shield element isolation forming method, the side wall spacer 15 is formed on the side wall of the field shield electrode 13a.
In order to separate and insulate the side wall of the electrode 13a from the gate electrode 17a of the element, the width B of the element isolation region is equal to the width L1 of the side wall spacer 15a, as shown in FIG. Overhangs the element active region A from the element isolation region width determined by the technology,
There is a problem that the width of the element isolation region is increased by the width L1. This problem has been one of the major problems in the miniaturization process.

When the width B of the element isolation region is reduced, as shown in FIG. 9, depletion regions K1 and K1 from the impurity diffusion layers 19 of the elements provided on both sides of the element isolation region.
2 is approaching, shortly before a short circuit, or short-circuiting decreases the withstand voltage for element isolation, which naturally limits the minimum separation width. Further, the gate electrode 17a of the device
When the resist pattern 18 is formed as shown in FIG. 7B to form the resist pattern 18, as shown in FIG. 10, the reflected light from the step portion by the field shield electrode 13a causes the resist pattern 18 to be affected by halation. Was. The influence of the halation causes instability of the gate electrode width, which causes a problem of causing deterioration of transistor characteristics.

[0008]

In order to solve the above-mentioned problems, the present invention provides a step of forming a V-shaped groove on the surface of an element isolation region of a semiconductor substrate, and forming a field shield gate insulating film on an inner wall of the V-shaped groove. Forming a field shield electrode by burying a conductive film in the V-shaped groove whose inner wall is covered with the field shield gate insulating film. And

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for forming a field shield element in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 are sectional views showing an embodiment of the present invention in the order of steps. In the embodiment of the present invention, first, as shown in FIG. 1A, a resist pattern 32 is formed on a surface of a silicon substrate 31 except for an element isolation region. Next, the silicon substrate 31 is etched by a dry etching technique using the resist pattern 32 as a mask, so that an upper diameter of 0.3 to 2.0 μmφ and a depth of 0.5 to 2 A V-shaped groove 33 of 0.0 μm is formed. here,
The depth of the V-shaped groove 33 is preferably set to be equal to or greater than the extension of the depletion region in the depth direction of the device to be used. The extension of the depletion region can be simulated from various conditions such as ion implantation conditions of the process, heat treatment conditions, and operating voltage, and is determined based on a calculation result. Next, ion implantation is performed using the resist pattern 32 as a mask, so that the V-shaped groove 33 is formed.
Is doped into the inner wall of the substrate to reduce the resistance.

Next, after the resist pattern 32 is peeled off and removed with a mixed chemical solution of sulfuric acid / hydrogen peroxide solution, 900 ° C. N
By performing dry oxidation in a ₂ / O ₂ atmosphere,
As shown in (b), a field shield gate oxide film 34 having a thickness of 300 to 700 mm is formed on the inner wall of the V-shaped groove 33 and the surface of the silicon substrate 31. Next, as shown in FIG. 1C, a polysilicon film is buried in the V-shaped groove 33, and a field shield electrode 35 is formed so as to be buried in the silicon substrate 31. Here, as an example of a method for forming the field shield electrode 35, a polysilicon film is formed by a low-pressure vapor deposition method so as to have a thickness equal to or greater than the depth of the V-shaped groove 33, and then a resist film is formed by a spin coating method. Then, the resist film and the polysilicon film are etched back until the field shield gate oxide film 34 on the surface of the silicon substrate 31 is exposed, so that the polysilicon film is left only in the V-shaped groove 33. To Next, the silicon substrate 31
By removing the field shield gate oxide film 34 on the front surface by a wet process using a hydrofluoric acid chemical solution as shown in FIG. 2A, the surface of the silicon substrate 31 (the surface of the active region of the silicon substrate 31) is exposed.

Thus, the step of forming the field shield element isolation section is completed. From the next step, a step of forming an element in the element active area of the silicon substrate 31 is performed. First, FIG.
As shown in (b), either a dry oxidation method using N ₂ / O ₂ gas, a hydrochloric acid oxidation method using hydrochloric acid gas, or a pyrogenic method by reacting hydrogen and oxygen to generate and burn water. A gate oxide film 36 having a thickness of 100 to 300 ° is formed on the surface of the active region of the silicon substrate 31. At this time, the surface of the field shield electrode (polysilicon film) 35 in the element isolation region is also oxidized, and a gate oxide film 36 is also formed on the surface. At this time, since the oxidation rate of the polysilicon film is about 1.5 to 1.7 times the oxidation rate of the silicon substrate, the polysilicon film has a higher oxidation rate on the field shield electrode 35 than on the active region of the silicon substrate 31. A thick gate oxide film 36 is formed. Thus, the field shield electrode 35 is sufficiently insulated. Thereafter, formation and patterning of a conductive layer are performed, and a gate electrode 37 is formed on the silicon substrate 31 at the element active area gate electrode formation position as shown in FIG. 2C. Further, ion implantation is performed to form the gate electrode 37.
An impurity diffusion layer 38 as a source / drain is formed in the element active region on both sides. Further, a side wall spacer 39 of the side wall of the gate electrode 37 is formed.

According to the above-described method, as shown in FIG.
And the field shield electrode portion does not have a structure protruding above the silicon substrate 31. Therefore, the side wall spacer of the field shield electrode formed conventionally is removed, and the element active region A of the side wall spacer is removed.
Overhang can be removed, and the element isolation region width B can be reduced. Further, since the surface is flattened and halation does not occur from the stepped portion due to the field shield electrode unlike the conventional case, the field shield element isolation portion has an adverse effect on element formation, that is, the gate electrode width becomes unstable. As a result, the problem of deteriorating transistor characteristics is eliminated. Further, when the field shield electrode 35 is buried in the V-shaped groove 33 of the silicon substrate 31, not only the electrical isolation but also the physical isolation function is performed.
As shown in FIG. 3, the depletion regions K1 and K2 can be prevented from becoming short-circuited or short-circuited, and a decrease in breakdown voltage of element isolation can be prevented even by miniaturization.

In the present invention, the groove for embedding the field shield electrode 35 is a V-shaped groove. This allows the field shield electrode 35 to be satisfactorily embedded and formed, and crystal defects are formed in the substrate near the groove. It can be prevented from occurring. In detail, FIG. 4 shows a state in which a polysilicon film 42 for forming an electrode is embedded in a U-shaped groove or a vertically etched groove 41 instead of the V-shaped groove in the present invention. In the U-shaped groove or the vertically etched groove 41, when the groove width is reduced to less than 1 μm due to the improvement of the miniaturization technology, a depletion 43 is almost formed in the center of the groove 41 in the process of embedding the polysilicon film 42. This is unsuitable for forming a field shield electrode. Further, crystal defects 44 due to stress are likely to occur in the substrate at the corners of the groove.

On the other hand, as shown in FIG. 5, when the polysilicon film 42 is buried in the V-shaped groove 33 according to the present invention, a slight amount Although a depression can be formed, no depletion occurs inside, and the trench can be completely filled with the polysilicon film 42. Further, when the angle θ of the corner of the groove becomes less than 90 °, the stress is alleviated.
Crystal defects hardly occur. The angle θ of the inner wall of the V-shaped groove 33 with respect to the surface of the substrate 31 is preferably in a range of 30 ° to 60 °, and most preferably 45 °. Angle θ of inner wall of V-shaped groove 33
Exceeds 60 °, depletion occurs in the polysilicon film 42 in the process of embedding the polysilicon film 42, which is unsuitable for forming a field shield electrode, and crystal defects due to stress are likely to occur. On the other hand, when the angle θ of the inner wall of the V-shaped groove 33 is less than 30 °, the V-shaped groove 3 has a sufficient depth.
In order to form 3, the width of the upper part of the V-shaped groove 33 exceeds 2 μm, which is inappropriate for miniaturization. From these, the angle θ of the inner wall of the V-shaped groove 33 is preferably 30 ° to 60 °.

[0015]

As described above, according to the field shield element isolation forming method of the semiconductor device of the present invention, the field shield electrode is formed by being embedded in the semiconductor substrate.
It is possible to reduce the width of the element isolation region, eliminate the adverse effect of the field shield element isolation portion on element formation, and prevent a decrease in element isolation withstand voltage due to miniaturization. A high-density semiconductor device can be manufactured. In addition, a semiconductor device having higher reliability can be manufactured from the viewpoint of embedding a polysilicon film and crystal defects by setting the embedding groove to a V-shaped groove and setting the inner wall angle to 30 ° to 60 °.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a field shield element isolation forming method for a semiconductor device according to the present invention in the order of steps.

FIG. 2 is a sectional view showing the embodiment and showing a step following FIG. 1;

FIG. 3 is a cross-sectional view illustrating a main part of the semiconductor device obtained in the embodiment of the present invention;

FIG. 4 is a sectional view showing a state in which a polysilicon film is buried in a U-shaped groove or a vertically etched groove.

FIG. 5 is a sectional view showing a state in which a polysilicon film is embedded in a V-shaped groove.

FIG. 6 is a sectional view showing a conventional forming method in the order of steps.

FIG. 7 is a cross-sectional view showing the conventional forming method and showing a step following FIG. 6;

FIG. 8 is a cross-sectional view for explaining a problem of a conventional forming method.

FIG. 9 is a cross-sectional view for explaining a problem of the conventional forming method.

FIG. 10 is a cross-sectional view for explaining a problem of the conventional forming method.

[Explanation of symbols]

 31 silicon substrate 33 V-shaped groove 34 field shield gate oxide film 35 field shield electrode

Claims (2)

[Claims] A step of forming a V-shaped groove on a surface of an element isolation region of a semiconductor substrate; a step of forming a field shield gate insulating film on an inner wall of the V-shaped groove; and covering an inner wall with the field shield gate insulating film. Forming a field shield electrode by burying a conductive film in said V-shaped groove. 2. The method according to claim 1, wherein an inner wall of said V-shaped groove has an angle of 30 ° to 60 ° with respect to a surface of said semiconductor substrate. Field isolation element forming method for a semiconductor device.