JPH1097494A - Data transfer system between cpu systems - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data transfer system which efficiently transfers data between CPU systems. SOLUTION: The data transfer system which performs data transfer between CPU systems wherein CPUs and memories are connected by a bus is equipped with an elastic memory(EM) 1 which is interposed in the data transfer path between the CPU systems 10 and 20 and matches data transfer and an interface part(IF) 7 which is interposed between the data readout side of the EMI and the bus 26 of the opposite CPU system 20 and acquires the bus right with bus right acknowledgement ACK responding to a bus right request REQ to the CPU system 20 to outputs read data of the EM1 to the bus 26; and the IF part 7 outputs the bus right request REQ once the EM1 is stored with data of more than one data read unit of the IF 7 to shorten the idle time of the bus 26 and reduce burst use of the bus 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method between CPU systems, and more particularly, to a data transfer method between CPU systems which transfers data between a plurality of CPU systems in which a CPU and a memory are connected by a bus. .
Today, many function realizing devices (functional units) are realized by a CPU system in which a CPU and a memory are connected by a bus, and there are many cases where data is exchanged between such a plurality of CPU systems. For example, in an exchange system, a CP (control) device and an SP (communication path) device are respectively realized by their own CPU systems.
Data transfer related to call control and the like is frequently performed between the PU and the memory or between the memories. Therefore, not only within the CPU system but also between each CPU system,
It is desired to realize efficient data transfer matching the configuration of the U system.

[0002]

2. Description of the Related Art FIG. 8 shows a partial configuration of a conventional switching system. In FIG. 8, reference numeral 10 denotes a CP system unit (CP unit) for performing main control of the switching system, and 11 denotes a 64-bit processor (CC). ), 12 are main memory (MM),
Reference numeral 13 denotes an interface (I) for connecting to an SP system device.
F) section, 14 is the system bus (SB) of CC11, 20
Is an SP device (SP unit), 21 is an SP device 2
A 32-bit microprocessor (MPU) for performing main control of 0, a static RAM (SRAM) 22;
23 is a dynamic RAM (DRAM), 24 is a DRA
An M control unit (DMC) 50 is a buffer unit connected to the CP device 10 and having an elastic memory of a predetermined capacity, and 26 is an MPU bus (MB) of the MPU 21.

In general, the CP system device 10 and the SP system device 20 have different CPU operating clock frequencies, operate asynchronously with each other, and have a high data transfer speed (memory cycle, 64/32 bus lines, etc.). different. Buffer unit 5
The reference numeral 0 denotes an elastic memory (not shown) having a predetermined capacity and an interface A connected to the side of the IF unit 13, which are provided for coordinating data transfer between the CP system device 10 and the SP system device 20. And an interface B connected to the MPU bus 26 side.

In such a configuration, conventionally, a constant threshold value is provided for each data input / output function of the interfaces A and B,
The following threshold control has been performed in order to match the data transfer between the P system and the SP system. That is, assuming that the buffer full number of the elastic memory is “n”, the interface A
In, the data input from the CP system is stopped (FULLLA
= 1) is n, and data can be output to the CP system (R
The threshold value of DYA = 1) was set to n, n / 2, or n-α (α: a predetermined value). Interface B is the same, SP
The threshold for stopping data input from the system (FULLB = 1) was n, and the threshold for data output to the SP system (RDYB = 1) was n, n / 2, or n-α.

[0005]

However, assuming that the threshold value at which data can be output (RDYA = 1 / RDYB = 1) is n, n / 2 or n-α, the data read side satisfies the threshold condition. Until the data can not be retrieved from the elastic memory. Therefore, for example, when attention is paid to data transfer from the CP system 10 to the SP system 20, the use frequency of the MPU bus 26 is uneven in the SP system 20 on the data read side due to the accumulation of data in the elastic memory and the block releasing operation. As a result, play time was generated in the MPU bus 26.

Further, since other bus users (MPU 20, peripheral I / O devices not shown) exist on the MPU bus 26, even if the interface B requests the bus right, the bus right permission is returned in a timely manner. This is not always the case, and this is a factor of acceleration of non-uniform use frequency. Further, once the interface B acquires the bus right, the amount of data stored in the elastic memory is large, and thereafter the MPU bus 26 is used in a burst for a relatively long time.
21 and peripheral IO devices.
The same applies to the CP device 10.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the related art, and has as its object to provide a data transfer method between CPU systems which enables efficient data transfer between a plurality of CPU systems. It is in.

[0008]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, the CPU of the present invention (1)
The data transfer method between the systems includes a data transfer path between the plurality of CPU systems 10 and 20 in a data transfer method between CPU systems in which data transfer is performed between a plurality of CPU systems in which a CPU and a memory are connected by a bus. And an elastic memory 1 for coordinating data transfer, and between a data reading side of the elastic memory 1 and a bus 26 of the CPU system 20 opposed thereto, and An interface unit 7 for acquiring a bus right by a bus right grant ACK for the bus right request REQ and outputting read data of the elastic memory 1 to a bus 26; The bus right request REQ is issued by storing one or more units of read data. It is intended to.

Note that FIG.
Although a case where data is transferred to the U system 20 is schematically shown, a case where data is transferred from the CPU system 20 to the CPU system 10 is similarly considered. The present invention (1)
In the example, the data write unit to the elastic memory 1 is 32 bits parallel (that is, the bus 14 has a 32-bit configuration), and the data read unit of the interface unit 7 is 32 bits parallel (that is, the bus 26 has a 32-bit configuration). ), The interface unit 7 outputs a bus right request REQ to the bus 26 when one or more 32-bit parallel data is written to the elastic memory 1, and when the bus right permission ACK is obtained thereafter, the interface unit 7 outputs The data for each one is read out and read into the memory 22 (or the CPU 21).
Transfer to

Alternatively, for example, if the unit for writing data to the elastic memory 1 is 32 bits in parallel and the unit for reading data from the interface unit 7 is 64 bits in parallel, the interface unit 7 stores two 32-bit parallel data in the elastic memory 1. The bus right request REQ is output to the bus 26 at the time of writing the data, and when a bus right permission ACK is obtained thereafter, two pieces of data are read from the elastic memory 1 and transferred to the memory 22 (or the CPU 21). .

As described above, according to the present invention (1), the interface unit 7 outputs the bus right request REQ when the elastic memory 1 stores the data of one unit or more of the data readout of the interface unit 7, so that the elastic unit 1 The effects of data storage and block release by the memory 1 are mitigated, whereby data transfer from the CPU system 10 to the CPU system 20 is performed uniformly, and the frequency of use of the bus 26 by data transfer is made uniform and averaged. Be transformed into
Further, even if the interface unit 7 once acquires the bus right, since the amount of data stored in the elastic memory 1 is relatively small, the burst use of the bus 26 can be relatively short, and the CPU 21 and other peripheral IO devices (non- (Shown in the drawing).

Thus, according to the present invention (1), the bus 26 on the data reading side is used uniformly and fairly by the CPU 21, the interface unit 7, and other peripheral I / O devices (PIOs). Data can be efficiently transferred between the CPU systems 10 and 20 as well as within the CPU 20. Further, since the amount of data stored in the elastic memory 1 is small, the storage capacity of the elastic memory 1 can be reduced.

Preferably, in the present invention (2), in the above-mentioned present invention (1), each of the CPU systems 10 and 20 is used.
Have different data transfer rates. CPU systems 10, 20
For example, if each memory cycle is different, the data transfer rate is different. If the number of each bus line (data transfer bus line) is different, the data transfer speed is different. Even in such a case, if the present invention (1) is applied, the bus 26 on the data reading side is used uniformly and fairly, so that efficient data transfer can be performed not only within the CPU system 20 but also between the CPU systems 10 and 20. I can do it.

Preferably, according to the present invention (3), the elastic memory 1 according to the present invention (1) is used.
Data is DMA-transferred between the data reading side of the memory and the memory 22 in the CPU system opposed thereto. Therefore,
The data transfer efficiency is high, and the use efficiency of the bus 26 is high.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a diagram showing a partial configuration of the exchange system according to the embodiment. In the figure, reference numeral 10 denotes a CP system unit (CP unit), and 11 denotes, for example, a 64-bit processor (C
C), 12 is a main memory (MM), 13 is an interface (IF) unit, 14 is a system bus (SB) of CC11,
20 is an SP system device (SP unit), 21 is, for example, 3
2-bit microprocessor (MPU), 22 static RAM (SRAM), 23 dynamic R
AM (DRAM), 24 is a DRAM control unit (DMC),
24 is a buffer unit according to the embodiment, 26 is an MPU 21
MPU bus (MB).

The CP device 10 and the SP device 20 have different CPU operating clock frequencies, operate asynchronously with each other, and have different data transfer speeds (memory cycles, bus lines 64/32, etc.). . The buffer unit 25
Data DMA between CP device 10 and SP device 20
It is provided for transfer coordination, and includes therein an elastic memory (a FIFO memory described later), an interface A connected to the IF unit 13, and an interface B connected to the MPU bus 26. Interface A is 6
The interface B is connected to a 4-bit data transfer bus line, and the interface B is connected to a 32-bit MPU bus 26.

FIG. 3 shows the configuration of the buffer section 25. In the figure, 1 is a reception FIFO buffer (elastic memory), 2 is a reception DMA controller, 3 is a transmission FIFO buffer (elastic memory), 4 is a transmission DMA controller, 5
Is a status control unit, 6 is an interface A connected to the IF unit 13, 7 is an interface B connected to the MPU bus 26, and 8 is an interrupt unit for notifying the MPU 21 of the end of data DMA transfer and the like. Hereinafter, an outline of the operation will be described.

Data transfer between the CP system and the SP system is performed by DMA transfer, and is performed bidirectionally in a half-duplex mode. C
When data is transferred from the P system 10 to the SP system 20, the SP memory (SRAM 22 / D) is stored in advance in each control register in the reception DMA control unit 2 by the CC 11 (or MPU 21).
Information such as the data write address and the number of data transfers in the RAM 23) is set, and the DMA is started. Then, CP system 1
The received data of 64 bits from 0
, The data is divided into two pieces each having 32 bits, and sequentially written into the reception FIFO buffer 1 (WT). Then, when the receiving FIFO buffer 1 becomes buffer full, the buffer full signal FULL = 1 is output to the interface A. As a result, the CP system 10 temporarily suspends data transmission.

The reception FIFO buffer 1 has 32
When even one bit data is stored, a buffer empty signal EMP = 0 (data present) is output. The reception DMA controller 2 constantly monitors the buffer empty signal EMP, and outputs a bus request signal REQ to the MPU bus 26 when EMP = 0 (data is present).
Thereafter, when the bus right permission signal ACK is received, the bus right is held thereafter, and the read data of the reception FIFO buffer 1 (each 32 bits) until EMP = 1 (no data).
DMA transfer (write) to specified SP system memory 22/23
I do.

When data is transferred from the SP system to the CP system, the MPU 21 (or CC 11) transmits the data from the transmission DMA beforehand.
An SP memory (SRA) is stored in each control register in the control unit 4.
The information such as the data read address of the M22 / DRAM 23) and the number of data transfers are set, and the DMA is started. Thereafter, the transmission DMA control unit 4 sets the buffer full signal FULL of the transmission FIFO buffer 3 to 0, indicating that M
When the bus right request signal REQ is output to the PU bus 26 and the bus right permission signal ACK is received thereafter, the bus right is held thereafter, and the SP memories 22/23 until the buffer full signal FULL = 1 (data full). Is transferred (written) to the transmission FIFO buffer 3 by DMA. In parallel with this, the 32-bit accumulated data of the transmission FIFO buffer 3 is packed two by two at the interface A and sent out to the IF unit 13. Thus, the accumulated data of the transmission FIFO buffer 3 becomes the buffer empty signal EMP = 1. Read until (empty).

FIG. 4 shows an interface A according to the embodiment.
FIG. 4A shows a communication protocol when a command is written from the CP system 10 to the control registers of the DMA control units 2 and 4 and data is read from the status register. As shown, the register write operation includes a request REQ, a request response ACK,
This is performed by exchanging the write data DATA and the write response AW. On the other hand, in the read operation of the register, the read register is specified in the first half, and the corresponding read data (status data or the like) is transferred in the second half.

FIG. 4B shows a DMA data transfer procedure from the CP system 10 to the SP system memory (SRAM 22 / DRAM 23). In the command start phase, the interface A executes the command C from the CP system 10 in the first half.
When the MD is received and the writing to the command register is completed, a response RPT is returned in the latter half. In the subsequent DMA data transfer phase, the required number of 64-bit data is sequentially received from the IF unit 13, divided into 32-bit data, and sequentially written into the reception FIFO buffer 1.
Then, upon receiving the final data, it returns a completion notification RPT.

FIG. 4C shows an SP type memory (SRAM 22).
/ DRAM 23) to the CP system 10 is shown. In the command start phase, the interface A sends a command CMD to the CP system 10 in the first half.
And a command response RPT from the CP system 10 in the latter half.
Receive. In the following DMA data transfer phase,
Data is sequentially read from the transmission FIFO buffer 3 in units of 32 bits, and these are assembled into 64-bit transfer data, two by two, and transferred to the CP system 10. Then, when the final data is transmitted, the completion notice RPT is returned from the CP system 10.

FIG. 5 shows an interface B according to the embodiment.
FIG. 4 is a diagram for explaining the operation sequence of FIG. The interface B is directly connected to the MPU bus 26, and the other peripheral IOs
As in the case of a device or the like (not shown), the bus right is acquired and the bus 26 is temporarily occupied. Therefore, the specifications of the interface B basically follow the bus control specifications of the MPU 21. In the figure, the memory cycle of an example of this system is MPU 21
MP at a certain point in time
U21 performs data writing W to the SRAM 22 (or the DRAM 23). Thereafter, the bus right request signal REQ is transmitted from the interface B (the transmission DMA control unit 4 in the example in the figure).
(In the figure, the signal HOLD) is output, and when the MPU 21 receives the signal, the bus right permission signal ACK (the signal HO in the figure)
LDA) is returned and the interface B receives this signal HOL.
While holding DA, data is continuously read from the SRAM 22 at the subsequent timings of T1 and T2. Receive DM
The same applies to the A control unit 2. However, the flow of data is reversed.

FIG. 6 is a timing chart of data DMA transfer from the SP device 20 to the CP device 10 according to the embodiment. When the data transmission from the SP system 20 to the CP system 10 is started, the opposite device (I
An activation command CMD is transmitted to the F unit 13), and an activation response RPT is returned from the partner device. In this section, the transmission DMA control unit 4 acquires the bus right of the MPU bus 26 via the interface B, and the DRAM 23 (or the SRAM 2).
2) Read the data sequentially and send them
Write to buffer 3. Example transmission FIFO buffer 3
Has a storage capacity of 8 × 32 bits, and when the buffer full signal FULL = 1, the bus right is released and data writing is temporarily suspended.

On the other hand, the interface A has a transmission FIFO
As long as the data exists in the buffer 3 (EMP = 0), the data is sequentially read from the transmission FIFO buffer 3, and these are assembled into 64-bit transfer data to assemble the RE.
Data is transferred to the IF unit 13 according to a data transfer sequence of Q, ACK, DT, and AW. Incidentally, the transfer data is written into the main memory 12 by the IF unit 13 (or the CPU 11) of the CP system 10.

When the transmission FIFO buffer 3 becomes empty (FULL = 0), the transmission DMA control unit 4
The bus right of the bus 26 is acquired, and the DRAM 23 (or the SRA
M22) is DMA-transferred to the transmission FIFO buffer 3. Therefore, burst use of the MPU bus 26 is reduced, and the use frequency is averaged. Thus, transmission F
The data writing and data reading of the I / O buffer 3 are repeated, and when the number of DMA data transfers reaches the set value, the transmission DMA controller 4 stops the DMA data transfer. Also, when transmitting the final data, the interface A
Notify part 13. As a result, the completion response RPT is returned from the IF unit 13.

FIG. 7 is a timing chart of the data DMA transfer from the CP device 10 to the SP device 20 according to the embodiment. When data transmission from the CP system 10 to the SP system 20 is started, the interface A is connected to the interface A (IF).
The start command CMD from the unit 13) is received, and a start response RPT is returned to the opposing device. Next, when the first 64-bit data is received from the IF unit 13, the data is divided into two pieces of 32-bit data by the interface A and sequentially written into the reception FIFO buffer 1.

Upon detecting the data empty signal EMP = 0 (there is data) in the reception FIFO buffer 1, the reception DMA control unit 2 acquires the bus right of the MPU bus 26 and stores the data stored in the reception FIFO buffer 1 in the SP memory (S
DMA transfer to the RAM 22 / DRAM 23). Therefore, burst use of the MPU bus 26 is reduced, and the use frequency is averaged. In the illustrated example, the IF unit 13
The second and subsequent 64-bit data are continuously received, but since the MPU bus 26 is occupied in bursts by other peripheral IO devices, the reception FIFO buffer 1
Data transfer from is intermittent.

When the 64-bit data is continuously received from the IF unit 13 and the buffer full signal FULL of the reception FIFO buffer 1 becomes "1", the fact is notified to the IF unit 13 via the interface A.
Suspends data transmission temporarily. In the illustrated example, the buffer full signal FULL = 1 is immediately released, and thereafter, the IF unit 13 transmits the final data.

The reception DMA controller 2 controls the SP while the buffer empty signal EMP of the reception FIFO buffer 1 is 0.
When the data DMA transfer to the system memory is continued, and the set number of DMA transfers are performed,
It returns the reception completion result report RPT to the F unit 13. In addition,
In the above embodiment, the buffer unit 25 is provided in the SP device 20.
It may be provided in the interface unit 13 of the system device 10.

Further, in the above-described embodiment, the DMA transfer is performed in the SP device 20 on one side.
Alternatively, the DMA transfer may be performed in the 0 and SP related devices 20. In the above embodiment, an example of application to an exchange system has been described. However, the present invention is applicable to various other function realizing devices that perform data transfer between a plurality of CPU systems in which a CPU and a memory are connected by a bus. it can.

Although the preferred embodiments of the present invention have been described, it goes without saying that various changes in the configuration, control, and combinations thereof can be made without departing from the spirit of the present invention. There is no.

[0034]

As described above, according to the present invention, an elastic memory for coordinating data transfer interposed in a data transfer path between a plurality of CPU systems stores one or more data. Since the bus right of the data reading side system is acquired and data is transferred promptly,
In the PU system, data can be efficiently transferred from the CPU system to the CPU system.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a partial configuration of an exchange system according to the embodiment.

FIG. 3 is a diagram illustrating a configuration of a buffer unit according to the embodiment;

FIG. 4 is a diagram illustrating an operation sequence of the interface A according to the embodiment.

FIG. 5 is a diagram illustrating an operation sequence of the interface B according to the embodiment.

FIG. 6 is a block diagram showing SP-type devices 20 to C according to the embodiment;
5 is a timing chart of a data DMA transfer to the P-system device 10.

FIG. 7 is a block diagram showing a configuration of the CP device 10 according to the embodiment;
6 is a timing chart of a data DMA transfer to the P-system device 20.

FIG. 8 is a diagram showing a partial configuration of a conventional switching system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reception FIFO buffer 2 reception DMA control unit 3 transmission FIFO buffer 4 transmission DMA control unit 5 status control unit 6 interface A 7 interface B 8 interrupt unit 10 CP device 11 main processor 12 main memory 13 interface unit 14 system bus 20 SP Related devices 21 Microprocessor 22 Static RAM 23 Dynamic RAM 24 DRAM control unit 25 Buffer unit 26 MPU bus

Claims (3)

[Claims] 1. A data transfer method between CPU systems for performing data transfer between a plurality of CPU systems in which a CPU and a memory are connected by a bus, wherein the data transfer system is provided on a data transfer path between the plurality of CPU systems. An elastic memory for coordinating transfer, and a CPU interposed between a data reading side of the elastic memory and a bus of a CPU system facing the elastic memory;
An interface unit for acquiring a bus right by granting a bus right in response to a bus right request to the system, and outputting readout data of the elastic memory to the bus, wherein the interface unit is configured such that the elastic memory has at least one unit of data readout of the interface unit. CPU for outputting a bus right request by accumulating data.
Data transfer method between systems. 2. The data transfer method between CPU systems according to claim 1, wherein each CPU system has a different data transfer speed. 3. The CPU according to claim 1, wherein data is DMA-transferred between a data reading side of the elastic memory and a memory in the CPU system opposed thereto.
Data transfer method between systems.