JPH1097441A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor which enables a CPU to efficiently and speedily performs processes when data transfer, a counting of the number of signals, or debugging is requested from outside by decreasing circuits which are connected to outside the CPU. SOLUTION: This data processor is provided with a specific instruction request signal generation part which outputs a specific instruction request signal to a request latch 16 of the CPU with a request signal for transfer, the counting of the number of pulses, or debugging which is inputted from outside. If the request latch 16 is detecting the specific instruction request signal 24 when the CPU is to take out an instruction corresponding to a program counter 1, a specific execution instruction for an instruction code 15 is read in instead of reading in the instruction corresponding to the program counter 1 and the specific execution instruction is executed. While the specific execution instruction is executed, the increase of the counting-up operation of the program counter 1 and access to a memory are inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reading an instruction corresponding to a program counter by accessing a memory via an address bus and a data bus, executing the instruction based on the read instruction, and reading the instruction. A data processing device having a central processing unit that increases a program counter every time, and particularly processes data according to a specific request signal such as data transfer from outside the central processing unit, counting of signal pulses and debugging. The present invention relates to a data processing device that can perform the processing.

[0002]

2. Description of the Related Art Among conventional central processing units capable of high-speed processing, those equipped with a three-stage pipeline output the value of a program counter 101 to an address bus 120 as shown in FIG. The instruction (instruction) stored in the address is transferred to the data bus 12.
1 and read into the first instruction latch (Latch) 108. Now, at a certain clock timing, the first instruction latch 1
08 is decoded by the instruction decoding unit 111. At the next clock, the contents of the first instruction latch 108 are sent to the second instruction latch 107, and the contents decoded by the instruction decode unit 111 are sent to the instruction execution unit 110.
The bus control unit 109 and the read data latch 105 or the write data latch 106 are controlled, whereby data is read from or written to the memory, or the register 102, the selector 103, and the arithmetic unit (AL
U: Arithmetic and Logic Unit) 104 is controlled to perform calculations.

At this time, the program counter 10
The value of 1 is incremented by a predetermined value in the program counter incrementer 100 and written to the program counter 101, and then the next instruction is taken into the first instruction latch 108.

On the other hand, when the interrupt request signal 123 is input, the interrupt processing unit 112 controls the instruction execution unit 110 and the program counter 101, invalidates the instruction currently stored in the first instruction latch 108, and resets the program counter 101. By setting the value to a preset value, the process branches to an interrupt processing program.

Here, in the conventional data processing device, when it is desired to transfer data at a high speed in response to an external request,
As shown in FIG. 7, a DMA (Direct Memory Access) controller 140 was used. DMA controller 1
At 40, when a transfer request signal is input, arbitration (Arbitration) of the bus such as opening of the bus is performed, and the central processing unit (hereinafter, referred to as a “CPU (Central Processing Unit)”) 130 is stopped. DMA controller 1
40 performs memory access and address output.

Accordingly, as the processing speed of the CPU 130 increases, the timing of bus arbitration becomes more difficult when switching addresses and control signals.

Further, since the DMA controller 140 has the address counter 141 and the transfer counter 142 therein, the circuit scale of the data processing device becomes large.

On the other hand, recently, when data is transferred at a high speed in response to an external request, as shown in FIG.
Systems using MU (Memory Management Unit) 190 are increasing. The MMU 190 is a circuit for converting an address (virtual address) output by the CPU 130 into an address (physical address) where a memory device actually exists in order to effectively use a storage device, and the conversion method is programmable. .

However, the DMA controller 140
Since it is attached to the outside of the U130 and cannot know the address conversion method of the MMU 190, it can always be transferred only by specifying a physical address.

Therefore, the problem can be solved by integrating the CPU 130 and the DMA controller 140 and then connecting the MMU 190.
This method cannot be adopted when the DMA controller 140 is added to the memory 130 later.

On the other hand, as shown in FIG. 1, in a recent data processing device, a CP having a cache control circuit 180 is incorporated.
U130 is increasing. This cache control circuit 18
0 stores the address and contents of the memory recently accessed by the CPU 130 in a small-capacity high-speed memory, that is, a cache memory. When the CPU 130 needs data and instruction codes, it is first included in the cache memory. It is checked if there is any, and if it is included, it is read from the cache memory, and if not, it is read from the external memory. Note that, in addition to the content to be read, the content to be written can also be stored in the cache memory.

However, the cache control circuit 1 is provided from the DMA controller 140 attached to the outside.
80 cannot be seen, and the cache control circuit 180
The operation of the controller 140 is not known. Therefore, if the data at the address stored in the cache memory is D
Even if the data is rewritten by the transfer of the MA controller 140, old data in the cache memory is referred to without notice, which is a problem.

That is, when data in an external memory is accessed for the first time, it enters the cache memory, but after the data at the same address in the memory is subjected to DMA processing, it is rewritten to another data. Originally, the data in the memory should match the data in the cache memory, but when DMA processing is performed, inconsistency arises because the data is completely different.

Therefore, in order to solve these problems,
As shown in FIG. 8, data was transferred by interruption without performing DMA processing.

In data transfer by interruption, the CPU
When the interrupt request signal 123 is input to
U130 jumps to a predetermined address and executes the program. Therefore, by writing a program for data transfer at the jump destination, the CPU 1
Since the memory 30 accesses the memory via the cache control circuit 180 and the MMU 190, the above problem can be solved. That is, unlike the DMA processing, the CPU 130
Processes while monitoring data, so there is no problem.

[0016]

However, in the above-mentioned conventional data processing apparatus, an extra procedure is required for interrupt processing and many clock cycles are required.
There is a problem that it is not suitable for high-speed transfer.

In order to explain this problem in detail, a case where data is transferred from the memory 131 to the I / O 132 will be considered as a specific example.

First, the case where the DMA controller 140 is used will be described. As shown in FIGS. 7 and 9, for example, during execution of instruction data D1, D2,... Stored at addresses A1, A2,. When transferring the data DT to the I / O 132, a transfer request signal is input to the transfer control unit 143 of the DMA controller 140. As a result, the transfer control unit 143 outputs an acknowledge signal 127 to the I / O 132, and the I / O 132 captures the data DT based on the acknowledge signal 127. It should be noted that the instruction data DT at the address T is transmitted to the I / O1
32 during one clock while transferring to
130 is in a stopped state.

On the other hand, when data is transferred by interruption, as shown in FIG. 10, addresses A1, A2,.
··· stored in the instruction data DT in the memory at the address T during execution of the instruction data D1, D2,.
At the time of transfer to the memory 132, the data DT is fetched by the address T and the memory write signal so that the data DT can be processed as fast as possible.

Here, in order to compare the two, the CPU 130
9 shows that the DMA controller 140 shown in FIG.
In the data transfer using, the delay of the instruction execution due to the transfer is one clock, but in the case of the interrupt in FIG. 10, it takes nine clocks. This is because, in the case of an interrupt, it is necessary to read extra instruction data and read a return instruction from the interrupt in order to execute the interrupt processing program.

The above-mentioned interrupt example shows a case where the interrupt processing can be performed at the highest speed, and in some cases, more clocks may be applied than in this example.

Further, as disclosed in Japanese Patent Publication No. 59-6413, there is a method of transferring data at high speed by using only a CPU. However, an increase in dedicated registers for each instruction increases the amount of additional circuits. In addition, there is a limit to the transfer speed because processing is performed by interruption of a micro instruction.

On the other hand, in a data processing device, it may be desired to count the number of pulses of a specific signal. When it is desired to count the number of pulses of a specific signal, as shown in FIG.
In addition to U130, the signal counter 151 and the clock generator 1
It is necessary to provide a circuit such as a pulse counter 150 including the step 52, and it is necessary to take a long time to perform processing by an interrupt having the configuration shown in FIG.

Also, in order to notify the state of the CPU 130 to the outside or to set a value in a register or the like of the CPU 130 in order to debug a program in the data processing device, the interruption shown in FIG. 8 is often performed. Therefore, there is a problem that the load on the CPU 130 is large and the efficiency of the original processing of the CPU 130 is reduced.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to transfer data, count the number of signals, and externally output the state of a central processing unit for debugging. An object of the present invention is to provide a data processing device in which the number of externally connected circuits is reduced when output is desired, and the central processing unit can process the data efficiently and at high speed.

[0026]

According to a first aspect of the present invention, there is provided a data processing apparatus for reading an instruction corresponding to a program counter by accessing a memory via an address bus and a data bus. In a data processing device having a central processing unit that executes the instruction based on the read instruction and increments a program counter each time the instruction is read, a transfer and counting of the number of pulses input from outside the central processing unit Alternatively, receiving a request signal for executing a specific instruction for debugging, generating and outputting a specific instruction request signal corresponding to each of the request signals so as to notify the central processing unit that any of the request signals has been received. Command request signal generating means is provided, and the central processing unit is provided with a specific command for detecting the specific command request signal. Instruction request signal detecting means, execution instruction storage means for storing a specific execution instruction for processing a transfer, pulse count or debug specific instruction input from the outside, and the central processing unit is a program. When the specific instruction request signal detecting means detects the specific instruction request signal at the time when the instruction corresponding to the counter is to be fetched, instead of reading the instruction corresponding to the program counter, the execution instruction storage means Reads a specific execution instruction of any of the stored transfer, pulse count or debug, executes the specific execution instruction, and during execution of the specific execution instruction, increases the program counter and accesses the memory. And selecting means for selecting to prohibit.

According to the above-mentioned invention, when there is a request signal for executing a specific command for transfer, counting of the number of pulses or debugging, which is input from outside the central processing unit, the specific command request signal generating means sets A specific command request signal corresponding to the request signal is generated and output to the central processing unit.

The central processing unit detects the specific command request signal by the specific command request signal detecting means.

On the other hand, when the specific instruction request signal detecting means detects the specific instruction request signal at the time when the central processing unit tries to fetch the instruction corresponding to the program counter, the selecting means sets the specific instruction request signal in accordance with the program counter. In place of reading the read instruction, read a specific execution instruction of transfer, pulse count, or debugging stored in the execution instruction storage unit, execute the specific execution instruction, and execute the specific execution instruction. Is selected to prohibit the increase of the program counter and the access to the memory.

As described above, when there is a specific command of transfer, counting of the number of pulses, or debugging from the outside of the central processing unit, the data processing unit performs a process similar to an interrupt. However, instead of interrupting the processing of the central processing unit like an interrupt, branching to a certain address, and returning to the original address after the processing is completed and restarting the original processing, the program counter is increased and the memory is increased. A specific instruction for transferring, counting the number of pulses, and exchanging debug information is read and executed while prohibiting access to the program. After execution, the program counter is incremented as usual.

Therefore, the time required for the branching process can be saved, and the data transfer, the counting of the number of pulses, and the debugging process can be performed at a relatively high speed.

On the other hand, when processing the above specific instruction,
This is realized by causing a single central processing unit to perform various processes and effectively using a register and a memory access function built in the central processing unit.

For example, data can be transferred by storing an instruction for memory access to the central processing unit in the execution instruction storage means. In this case, since data transfer is performed using the function of the central processing unit, transfer using these functions can be performed even if an MMU, a cache, or the like is incorporated. Therefore, the overall circuit scale can be reduced, and bus adjustment is not required.

Similarly, the number of pulses can be counted by executing a specific instruction for increasing the value of a specific register. In this case, since counting is performed using a register inside the central processing unit, it can be externally realized only by a circuit for generating a request signal.

Further, by executing a specific instruction for writing the register value of the central processing unit into a memory or the like, information for debugging can be output to the outside. in this case,
It can be realized only by adding a circuit for generating a request signal and a circuit for extracting output information to the outside.

Therefore, when it is desired to transfer data, count the number of signals, or output the state of the central processing unit to the outside for debugging, the number of externally connected circuits is reduced, and the central processing unit is efficiently used. It is possible to provide a data processing device capable of performing good and high-speed processing.

According to a second aspect of the present invention, there is provided a data processing apparatus comprising:
In order to solve the above-mentioned problem, in the data processing device according to claim 1, the specific execution instruction of the execution instruction storage means is formed to be rewritable.

According to the above invention, the specific execution instruction of the execution instruction storage means is formed to be rewritable.
The two small-capacity execution instruction storage means can switch to a specific execution instruction corresponding to each specific instruction of transfer, counting of the number of pulses, or debugging from outside.

Therefore, the number of circuits can be reduced to prevent the data processing device from being enlarged.

According to a third aspect of the present invention, there is provided a data processing apparatus comprising:
In order to solve the above-mentioned problem, in the data processing device according to claim 1 or 2, the specific execution instruction of the execution instruction storage means, when the specific instruction indicates a debug, all the registers in the central processing unit. It is characterized by comprising an information external output command for outputting contents and flag values to the outside.

That is, in the prior art, when debugging a program, it was necessary to perform processing by an interrupt, so that it was difficult to perform high-speed processing.

However, according to the present invention, when the specific instruction indicates debugging, the specific execution instruction of the execution instruction storage means transmits the contents of all registers and flag values in the central processing unit to the outside. This is an information external output instruction for output.

Therefore, if an information external output instruction for writing the register value of the central processing unit into a memory or the like is executed, information for debugging can be output to the outside. In this case, it can be realized only by adding a circuit for generating a request signal and a circuit for extracting output information to the outside.

As a result, the number of circuits is reduced to prevent the data processing apparatus from becoming large, and the processing can be performed at high speed because it is not the conventional interrupt processing.

According to a fourth aspect of the present invention, there is provided a data processing apparatus comprising:
In order to solve the above-mentioned problem, in the data processing device according to claim 1 or 2, the central processing unit is provided with a pulse counting register for counting a specific number of pulses, and the selection unit is provided with an external device. If the request signal input from the device indicates a count of a specific number of pulses,
It is characterized in that the value of the pulse count register is increased by one.

That is, conventionally, when a count of a specific number of pulses is indicated, a dedicated pulse counter is required in addition to the central processing unit, which has led to an increase in the size of the data processing unit.

However, according to the above invention, when counting a specific number of pulses, the selection means selects
The value of the pulse count register of the central processing unit provided for counting a specific number of pulses can be increased by one. In this case, since the counting is performed using the pulse counting register inside the central processing unit, it can be realized only by a circuit for generating a request signal outside.

Therefore, the number of circuits can be reduced and the size of the data processing device can be reduced.

According to a fifth aspect of the present invention, there is provided a data processing apparatus comprising:
3. The data processing device according to claim 1, wherein the specific execution instruction of the execution instruction storage unit is a memory read for reading the contents of the memory when the specific instruction indicates transfer. It is characterized by comprising an instruction or a memory write instruction for writing to a memory.

According to the above invention, when the specific instruction indicates transfer, a memory read instruction for reading the contents of the memory or a memory write instruction for writing to the memory is used as the specific execution instruction of the execution instruction storage means. If either of these is selected, memory read or memory write can be executed. In this case, since data transfer is performed using the function of the central processing unit, transfer utilizing these functions can be performed even if an MMU, a cache memory, or the like is incorporated. Furthermore, no bus adjustment is required.

Therefore, at the time of data transfer, the number of circuits can be reduced and the data processing device can be prevented from being enlarged.

According to a sixth aspect of the present invention, there is provided a data processing apparatus comprising:
In order to solve the above-mentioned problem, in the data processing apparatus according to claim 5, when the execution instruction storage means executes a memory read instruction or a memory write instruction by a specific execution instruction, the selection means reads the memory read instruction by a memory read instruction. It is characterized in that the data bus is made to have a high impedance by a memory write instruction without writing a value to a register.

That is, when data is exchanged between the I / O and the memory, the data bus must be opened to prevent the data bus from colliding with data from the central processing unit.

Therefore, in the present invention, when the memory read instruction or the memory write instruction is executed by the specific execution instruction of the execution instruction storage means, the selecting means does not write the value read by the memory read instruction to the register. The data bus is made high impedance by a memory write instruction.

Therefore, even when data is exchanged between the I / O and the memory according to the specific execution instruction of the execution instruction storage means, it is possible to prevent the data from colliding with the data from the central processing unit on the data bus.

[0056]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the central processing unit in the data processing apparatus according to the present embodiment includes a program counter 1, a register 2, a selector 3, and an arithmetic unit (ALU: Arithm).
eticand Logic Unit) 4, Read data latch (Latch)
5, a write data latch 6, a first instruction latch 8, a second instruction latch 7, a bus control unit 9, an instruction execution unit 10, an instruction decoding unit 11, an interrupt processing unit 12, a program counter incrementer (hereinafter, “PC incrementer”). 13). Up to this point, this is the same as the conventional one, but in the present embodiment, the selector 14 as the selection means, the instruction code 15 as the execution instruction storage means, and the request latch 16 as the specific instruction request signal detection means are further provided. Is provided.

The above-mentioned central processing unit is provided with a three-stage pipeline, executes instructions in three steps, inputs the next instruction for each step, and executes the three instructions in parallel. To be processed. That is,
Instructions are fetched, decoded and executed simultaneously in parallel.

Here, the central processing unit performs exactly the same operation as the conventional one because the data bus 21 is selected by the selector 3 for normal operation and interrupt processing.

That is, in a normal operation, the value of the program counter 1 is output to the address bus 20, and the instruction (Instruction) stored at that address is output.
ction) is read from the data bus 21 and taken into the first instruction latch 8. Now, the value fetched into the first instruction latch 8 at a certain clock timing is decoded by the instruction decoding unit 11. Next, at the next clock, the first instruction latch 8
Is sent to the second instruction latch 7, while the contents decoded by the instruction decode unit 11 are sent to the instruction execution unit 10 to control the bus control unit 9 and the read data latch 5 or the write data latch 6, and Read from memory, write to memory or register 2, selector 3
And the arithmetic unit (ALU) 4 to perform calculations.

At the same time, the value of the program counter 1 is added by a predetermined value by the PC incrementer 13 and written into the program counter 1, and the next instruction is taken into the first instruction latch 8.

When the interrupt request signal 23 is input, the interrupt processing unit 12 controls the instruction execution unit 10 and the program counter 1, invalidates the instruction currently stored in the first instruction latch 8, and resets the program counter 1. By setting the value to a preset value, the process branches to an interrupt processing program.

On the other hand, in the central processing unit of the data processing apparatus according to the present embodiment, when data is transferred in response to an external request, a specific instruction request signal 24 is input to the request latch 16. Then, the selector 14 is switched at a timing by the request latch 16 so that the data representing the specific execution instruction stored in the instruction code 15 is taken into the first instruction latch 8.

The instruction code 15 is stored in the first instruction latch 8.
While the data is loaded, the bus control unit 9 prohibits the memory access, and prohibits the PC incrementer 13 from incrementing the program counter 1. Thereafter, the operation returns to the normal operation.

Further, it also outputs a registered instruction processing signal 26 so that the timing at which the instruction fetched by the first instruction latch 8 is executed by the instruction execution unit 10 can be known. That is, the registration command processing signal 26 outputs a signal corresponding to an acknowledge signal existing in the conventional DMA processing.

Further, the data processing device of the present embodiment
As shown in FIG. 2, the central processing unit (hereinafter referred to as “CPU (Ce
ntral Processing Unit) 30), a transfer control unit 71, a clock generation unit 72, a debug control circuit 73, a specific instruction request signal generation unit 70 as specific instruction request signal generation means, a transfer counter 42, and I / O3
2. Cache control circuit 80, MMU (Memory Managem
ent Unit) 90 and a memory 31.

In the data processing device having the above configuration,
It is assumed that, for example, data of the I / O 32 is transferred to the memory 31 by an external input.

In this case, the CPU 30 shown in FIG.
For example, a memory write instruction is inserted in advance as a specific execution instruction in the instruction code 15 of FIG. This instruction code 1
5 is preferably constituted by a register in terms of high-speed processing, but is not necessarily limited to this, and may be constituted by another storage device.

In this state, when a transfer request signal is input to the transfer control unit 71 as shown in FIG. 2, the specific command request signal generation unit 70 outputs a transfer request signal to the CPU 30 as the specific command request signal 24. You. This transfer request signal is
As shown in FIG. 1, the request is input to the request latch 16 of the CPU 30.

Next, the selector 14 is switched via the switching signal 25 at a timing according to the transfer request signal of the request latch 16, and the specific execution instruction of the instruction code 15 is input to the first instruction latch 8. As a result, the specific execution instruction is thereafter executed by the second instruction latch 7, the instruction decoding unit 11, the instruction execution unit 10, and the bus control unit 9, as in the normal operation described above.

At this time, upon execution of the specific execution instruction of the instruction code 15, the request latch 16 outputs a transfer processing signal as a registered instruction processing signal 26. The transfer processing signal is output from the CPU 30 and input to the transfer control unit 71 as shown in FIG.
An acknowledgment signal 27 is output to / O32. At this time, the data bus 21 becomes high impedance,
The data of O32 is written to the memory 31.
As a result, transfer from the I / O 32 to the memory 31 becomes possible.

However, when using this method, it is necessary to prohibit the transfer data from being cached. That is,
If you do not cache the transfer data like this,
As described in the related art, the data in the external memory enters the cache memory and is rewritten to another data when accessed for the first time, so that a mismatch occurs during normal processing.

The above operation will be described with reference to the timing chart shown in FIG.

When the transfer request signal, which is the specific instruction request signal 24, goes high during execution of the instruction data D1, D2,... Stored in the addresses A1, A2,. The transfer processing signal which is the registration command processing signal 26 becomes high. This allows the acknowledgment signal 2 in the next clock cycle.
7 is output. At this time, the data bus 2 of the CPU 30
If 1 is set to high impedance and the data of the I / O 32 is written to the memory 31, the transfer from the I / O 32 to the memory 31 becomes possible.

That is, when the instruction data D1, D2... Of the addresses A1, A2... Are executed, the instruction data D3 of the address A3, A4. Before D3, I / O3
2 causes a state in which a write instruction to the memory 31 is interrupted.

As a result, a write instruction is input to the first instruction latch 8 at the next clock of the instruction data D2, and the second instruction latch 7 and the instruction execution unit 1 are input at the next clock.
A write command is input to 0 and executed. At this time, if it is necessary to count the number of transfers, the transfer counter 42 of the transfer control unit 71 shown in FIG. 2 counts the second instruction latch 7 and the write instruction of the instruction execution unit 10 at the next clock. Is done. As a result of the above operation, the number of clocks required for transfer is two.

On the other hand, in the conventional method, the number of clocks required for transfer is one clock when the DMA controller is used (see FIG. 9) and nine clocks when the interrupt is used (see FIG. 10).

Therefore, when compared with the conventional product, in the present embodiment, although the speed is slightly reduced compared with the case where the DMA controller is used, the circuit configuration is simpler than the case where the DMA controller is used. Manages data, so that the MMU 90 can be utilized. That is, the portion of the conventional DMA controller can be reduced in hardware.

Next, in the above example, the memory write instruction is inserted in the instruction code 15, but this instruction code 15
If a memory read instruction, which is one specific execution instruction of the transfer instruction, is inserted in the memory 31, data transfer from the memory 31 to the I / O 32 is possible. Further, if an instruction to add 1 to the transfer counter 42 is inserted, the transfer pulse signal can be counted.

Furthermore, it is also possible to put, in the instruction code 15, an instruction to be written to an external memory as a specific execution instruction. Thus, by extracting the value output after the registration command processing signal 26 becomes high, debug information can be extracted.

Here, as a specific example of the instruction code 15,
For example, when using the instruction set of a 32-bit RISC processor ARM6 / 7 of ARM, UK, as shown in FIG. 4, an instruction to transfer from the address [Ry] indicated by the register Ry to the I / O 32 and an address from the I / O 32 The instruction to transfer to [Ry], the instruction to count the number of pulses, and the instruction to call the value of the register are respectively shown in the instruction column.

The instruction code 15 does not need to be a value fixed to the above contents, but may be rewritable by a program.

There may be two or more types of the specific command request signal 24 and the command code 15, and different specific execution commands may be selected depending on the type of the input request signal.

Further, as shown in FIG.
5, there is not only one specific execution instruction but also two or more specific execution instructions. These specific execution instructions are sequentially taken into the first instruction latch 8, and during that time, the access to the memory 31 and the addition of the program counter 1 are stopped. It is also possible.

FIG. 5 shows a case where data is transferred from address [Ry] indicated by register Ry to address [Rz] indicated by register Rz. The value of the register Rx does not change before and after the transfer. In the example shown in FIG. 5, the transfer can be performed by utilizing both the MMU 90 and the cache control circuit 80.

In the example shown in FIG. 4, the general-purpose register Rx and the register Ry cannot be used for data transfer or pulse counting, or the memory 31 is prohibited from being cached and the data bus 21 of the CPU 30 is set high. There is a problem that impedance must be set.

Therefore, in order to avoid this, the CPU 3
A dedicated register 15 such as a transfer dedicated register or a pulse count register for counting a specific number of pulses to 0
It is also possible to prepare a and use it for the instruction code 15 by reading / writing the memory using the dedicated register 15a or adding an instruction for performing addition.

Here, the memory read / write instruction is C
If the data bus 21 is set to a high impedance and an execution instruction that automatically performs an operation of prohibiting caching is performed without reading / writing the register 2 inside the PU 30, the transfer operation is in an appropriate state. For example, in the example of the LDR instruction (read instruction) shown in FIG. 4, the read value is written to the general-purpose register Rx, but it is understood from the effects that it is not necessary to write to the general-purpose register Rx. Therefore, there is no problem even in the case described above. Conversely, a change in the value of the general-purpose register Rx will adversely affect the use of the general-purpose register Rx in another program.

As described above, in the data processing apparatus of the present embodiment, when there is a request signal for executing a transfer, pulse count, or debug specific instruction input from outside the CPU 30, a specific instruction request signal The generation unit 70 generates the specific command request signal 24 corresponding to each of these request signals, and outputs it to the CPU 30.

The CPU 30 detects the specific command request signal 24 in the request latch 16.

On the other hand, when the CPU 30
At the point when the instruction corresponding to
6 detects the specific command request signal 24, the selector 14 selects one of the transfer, the counting of the number of pulses, and the debugging stored in the command code 15 instead of reading the command corresponding to the program counter 1. Is read, and the specific execution instruction is executed.
In addition, the selection of the selector 14 inhibits the increase of the program counter 1 and the access to the memory 31 during execution of the specific execution instruction.

As described above, transfer from outside the CPU 30
When there is a specific instruction for counting the number of pulses or for debugging, the data processing device processes the same operation as an interrupt. However, instead of interrupting the processing of the CPU 30 like an interrupt, branching to a predetermined address, and returning to the original address after the processing is completed and resuming the original processing, the program counter 1 is increased and the memory 31 is increased. A specific instruction for transferring, counting the number of pulses, and exchanging debug information is read and executed while prohibiting access to the program. After the execution, the program counter 1 is incremented as usual.

Therefore, the time required for the branching process can be omitted, and the data transfer, the counting of the number of pulses, and the debugging process can be performed at a relatively high speed.

On the other hand, when processing the above specific instruction,
Various processes are performed by one CPU 30 and the CPU 30
This is achieved by effectively utilizing the registers and memory access functions built into the LM.

For example, by storing an instruction for accessing the memory of the CPU 30 in the instruction code 15, data can be transferred. In this case, since the data is transferred using the function of the CPU 30, even if the MMU 90, the cache control circuit 80, and the like are built in, the transfer using these functions can be performed. Therefore, the overall circuit scale can be reduced, and bus adjustment is not required.

Similarly, the number of pulses can be counted by executing a specific instruction for increasing the value of the dedicated register 15a. In this case, the ALU inside the CPU 30
Since the count is performed using the register 4 and the dedicated register 15a, it can be realized only by a circuit for generating a request signal externally.

Further, each register 2.15 of the CPU 30
By executing a specific instruction to write a value such as a into the memory 31 or the like, information for debugging can be output to the outside. In this case, it can be realized only by adding a circuit for generating a request signal, that is, a debug control circuit 73 and a circuit for extracting output information to the outside.

Therefore, when it is desired to transfer data, count the number of signals, or output the state of the CPU 30 to the outside for debugging, the number of circuits connected to the outside is reduced and the CPU 30 can operate efficiently and at high speed. A data processing device capable of processing can be provided.

In the data processing device according to the present embodiment, the specific execution instruction of the instruction code 15 is rewritable. Therefore, it is possible to switch to a specific execution instruction corresponding to each specific instruction of transfer, counting of the number of pulses, or debugging from the outside with one small-capacity instruction code 15.

Therefore, the number of circuits can be reduced and the data processing device can be prevented from being enlarged.

On the other hand, in the prior art, when debugging a program, it was necessary to perform processing by interruption, so that it was difficult to perform high-speed processing.

However, in the data processing device of the present embodiment, when the specific instruction indicates debugging, the instruction code 1
The fifth specific execution instruction is an information external output instruction for outputting the contents of all the registers in the CPU 30 and the flag values to the outside.

Therefore, if an information external output instruction for writing the register value of the CPU 30 to the memory 31 or the like is executed, information for debugging can be output to the outside. In this case, it can be realized only by adding a circuit for generating a request signal and a circuit for extracting output information to the outside.

As a result, the number of circuits can be reduced to prevent the data processing apparatus from becoming large, and the processing can be performed at high speed because it is not the conventional interrupt processing.

Conventionally, when indicating the count of the number of pulses, a dedicated pulse counter is required outside the CPU 30, which has led to an increase in the size of the data processing apparatus.

However, in the data processing device of the present embodiment, when counting a specific number of pulses, the selector 14 selects the dedicated register 15a of the CPU 30 provided for counting the specific number of pulses when the selector 14 is selected. Can be increased by one. In this case, the CPU 3
Since counting is performed using the ALU 4 inside the 0 and the dedicated register 15a, it can be realized only by a circuit for generating a request signal externally.

Therefore, the number of circuits can be reduced and the size of the data processing device can be reduced.

Further, in the data processing apparatus of the present embodiment, when the specific instruction indicates transfer, a memory read instruction for reading the contents of the memory 31 or writing to the memory 31 is performed as the specific execution instruction of the instruction code 15. Memory read or memory write can be executed by selecting any one of the memory write instructions. In this case, since the data is transferred using the function of the CPU 30, even if the MMU 90, the cache control circuit 80, and the like are built in, the transfer using these functions can be performed. Furthermore, no bus adjustment is required.

Therefore, at the time of data transfer, it is possible to reduce the number of circuits and prevent the data processing apparatus from becoming large.

On the other hand, when exchanging data between the I / O 32 and the memory 31, the CPU 3
Data bus 2 to prevent collision with data from 0
1 must be released.

Thus, in the present embodiment, the selector 14
When the memory read instruction or the memory write instruction is executed by the specific execution instruction of the instruction code 15, the data bus 21 is made high impedance by the memory write instruction without writing the value read by the memory read instruction to the register 2.

Therefore, even when data is exchanged between the I / O 32 and the memory 31 according to the specific execution instruction of the instruction code 15, the CPU 30
Can be prevented from colliding with data from.

[0113]

According to the first aspect of the present invention, as described above, the request signal for executing the transfer, pulse count, or debug specific instruction input from outside the central processing unit is provided. And a specific command request signal generating means for generating and outputting a specific command request signal corresponding to each of the request signals so as to notify the central processing unit that the request signal has been received. The apparatus includes a specific command request signal detecting means for detecting the specific command request signal, a transfer externally input,
Execution instruction storage means for storing a specific execution instruction for processing a pulse count or debug specific instruction; and when the central processing unit attempts to fetch an instruction corresponding to a program counter, When the instruction request signal detecting means detects the specific instruction request signal, instead of reading the instruction corresponding to the program counter, any of transfer, pulse count or debug stored in the execution instruction storage means is performed. Selecting means for reading the specific execution instruction, executing the specific execution instruction, and selecting to inhibit the increase of the program counter and the access to the memory during the execution of the specific execution instruction. Things.

Therefore, transfer from outside the central processing unit,
When there is a specific instruction for counting the number of pulses or for debugging, the data processing device processes the same operation as an interrupt. However, instead of interrupting the processing of the central processing unit like an interrupt, branching to a certain address, and returning to the original address after the processing is completed and restarting the original processing, the program counter is increased and the memory is increased. A specific instruction for transferring, counting the number of pulses, and exchanging debug information is read and executed while prohibiting access to the program. After execution, the program counter is incremented as usual.

As a result, the time required for the branching process can be omitted, and the data transfer, the counting of the number of pulses, and the debugging process can be performed at a relatively high speed.

On the other hand, when processing the above specific instruction,
This is realized by causing a single central processing unit to perform various processes and effectively using a register and a memory access function built in the central processing unit.

Therefore, when it is desired to transfer data, count the number of signals, or output the state of the central processing unit to the outside for debugging, the number of externally connected circuits is reduced, and the efficiency of the central processing unit is reduced. There is an effect that a data processing device capable of performing good and high-speed processing can be provided.

The data processing device according to the second aspect of the present invention
As described above, in the data processing device according to the first aspect, the specific execution instruction of the execution instruction storage unit is formed to be rewritable.

Therefore, it is possible to switch to a specific execution instruction corresponding to each specific instruction of transfer, counting of the number of pulses or debugging from outside by one small-capacity execution instruction storage means.

Therefore, an effect is obtained that the number of circuits can be reduced to prevent the data processing device from being enlarged.

The data processing device according to the third aspect of the present invention
As described above, in the data processing device according to claim 1 or 2, when the specific instruction indicates debugging, the specific execution instruction of the execution instruction storage means is the contents or flags of all registers in the central processing unit. Is an information external output instruction for outputting the value of the information to the outside.

Therefore, if an information external output instruction for writing the register value of the central processing unit to a memory or the like is executed, information for debugging can be output to the outside. In this case, it can be realized only by adding a circuit for generating a request signal and a circuit for extracting output information to the outside.

As a result, the number of circuits can be reduced to prevent the data processing device from increasing in size, and it is possible to perform high-speed processing because it is not the conventional interrupt processing.

The data processing apparatus according to the fourth aspect of the present invention
As described above, in the data processing device according to claim 1 or 2, the central processing unit is provided with a pulse count register for counting a specific number of pulses, and the selection unit is externally input. If the request signal indicates a count of a specific number of pulses, the value of the pulse count register is incremented by one.

Therefore, when counting a specific number of pulses, the number of pulses is counted using a pulse counting register inside the central processing unit, so that it can be externally realized only by a circuit for generating a request signal.

Therefore, there is an effect that the number of circuits can be reduced and the size of the data processing device can be reduced.

The data processing device according to the fifth aspect of the present invention
As described above, in the data processing apparatus according to claim 1 or 2, the specific execution instruction of the execution instruction storage means is a memory read instruction or a memory for reading the contents of the memory when the specific instruction indicates transfer. Consists of a memory write instruction for writing to

Therefore, when the specific instruction indicates transfer, either the memory read instruction for reading the contents of the memory or the memory write instruction for writing to the memory is used as the specific execution instruction of the execution instruction storage means. If selected, memory read or memory write can be executed. In this case, since data transfer is performed using the function of the central processing unit, transfer utilizing these functions can be performed even if an MMU, a cache memory, or the like is incorporated. Furthermore, no bus adjustment is required.

Therefore, in data transfer, there is an effect that the number of circuits can be reduced to prevent the data processing device from being enlarged.

[0130] The data processing device of the invention according to claim 6 is characterized in that:
As described above, in the data processing device according to claim 5, when the memory read instruction or the memory write instruction is executed by the specific execution instruction of the execution instruction storage unit, the selection unit reads the value read by the memory read instruction. The data bus is made high impedance by a memory write instruction without writing to a register.

Therefore, even when data is exchanged between the I / O and the memory according to the specific execution instruction of the execution instruction storage means, it is possible to prevent the data from colliding with the data from the central processing unit on the data bus. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a data processing device according to the present invention and illustrating a configuration of a central processing unit.

FIG. 2 is a block diagram showing an overall configuration of the data processing device.

FIG. 3 is a timing chart showing an operation of the data processing device.

FIG. 4 is an explanatory diagram showing specific instructions and operations of the data processing device.

FIG. 5 is an explanatory diagram showing specific instructions and operations when the data processing apparatus includes a plurality of instruction codes.

FIG. 6 is a block diagram showing a configuration of a central processing unit in a conventional data processing device.

FIG. 7 is a block diagram showing an overall configuration of the data processing device.

FIG. 8 is a block diagram showing a configuration in a case where an interrupt process is performed in the data processing device.

FIG. 9 is a timing chart showing an operation when data transfer is performed in the processing by the DMA controller shown in FIG. 7;

FIG. 10 is a timing chart showing an operation when data transfer is performed in interrupt processing.

[Explanation of symbols]

1 Program Counter 14 Selector (Selection Means) 15 Instruction Code (Execution Instruction Storage Means) 15a Dedicated Register (Pulse Count Register) 16 Request Latch (Specific Instruction Request Signal Detection Means) 20 Address Bus 21 Data Bus 24 Specific Instruction Request Signal 30 Central processing unit [CPU] 31 Memory 70 Specific instruction request signal generation unit (specific instruction request signal generation means)

Claims (6)

[Claims] An instruction corresponding to a program counter is read by accessing a memory via an address bus and a data bus. The instruction is executed based on the read instruction, and the program counter is incremented each time the instruction is read. In a data processing device provided with a central processing unit, a request signal for executing a specific instruction of transfer, counting of the number of pulses, or debugging input from outside the central processing unit, and any of these request signals was received. In order to notify the central processing unit of this, a specific instruction request signal generating means for generating and outputting a specific instruction request signal corresponding to each of the request signals is provided, and the central processing unit detects the specific instruction request signal. Specific instruction request signal detecting means to transfer, pulse count or debug input from outside An execution instruction storage unit for storing a specific execution instruction for processing the specific instruction; and the specific instruction request signal detection unit, when the central processing unit attempts to fetch the instruction corresponding to the program counter, When detecting the instruction request signal, instead of reading the instruction corresponding to the program counter, read a specific execution instruction of any of transfer, pulse count or debug stored in the execution instruction storage means, Data processing means for executing the specific execution instruction and selecting the execution of the specific execution instruction so as to increase the program counter and inhibit access to the memory. apparatus. 2. The specific execution instruction of the execution instruction storage means,
2. The device according to claim 1, wherein the rewritable portion is formed.
The data processing device according to claim 1. 3. The specific execution instruction of the execution instruction storage means,
3. The information external output instruction for outputting the contents of all registers and flag values in the central processing unit to the outside when the specific instruction indicates debugging. Data processing equipment. 4. The central processing unit is provided with a pulse counting register for counting a specific number of pulses, and the selecting means indicates that the request signal input from the outside indicates the counting of the specific number of pulses. 3. The data processing device according to claim 1, wherein the value of the pulse count register is increased by one in each case. 5. The specific execution instruction of the execution instruction storage means,
3. The data processing apparatus according to claim 1, wherein when the specific instruction indicates transfer, the data processing apparatus comprises a memory read instruction for reading the contents of the memory or a memory write instruction for writing to the memory. 6. When the memory read instruction or the memory write instruction is executed by the specific execution instruction of the execution instruction storage means, the selecting means does not write the value read by the memory read instruction to the register, but executes the memory write instruction. 6. The data processing device according to claim 5, wherein the data bus is set to a high impedance.