JPH1093430A - Synchronization detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an output accuracy by increasing an operation limit frequency of a synchronization detection circuit configured on an integrated circuit. SOLUTION: An inverting amplifier circuit 12 to generate an inverting signal being an inverse of an input signal Sin is provided to one path in two systems of signal paths from an input terminal Tim reaching an output terminal Tout, and a buffer circuit 14 providing an output of a noninverting signal in phase to the Sin is provided to the other path. Moreover, CMOS analog switches 16, 18 are provided to outputs of each of the circuits 12, 14. Then each of the analog switches 16, 18 is alternately turned on/off by control signals ϕ1, ϕ1 generated from a reference signal Sc and when the Sc is higher than a zero cross point voltage Vt1, a noninverting signal is outputted from the output terminal Tout and when not, an inverting signal is outputted from the output terminal Tout. In the case of switching noninverting/inverting outputs, each of the analog switches 16, 18 is simultaneously and tentatively turned on. As a result, an output signal Sout is switched at a high speed in the noninvertingly or invertingly without causing distortion or noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous detection circuit which is formed on an integrated circuit and extracts a signal component synchronized with a reference signal from an input signal.

[0002]

2. Description of the Related Art Conventionally, a synchronous detection circuit has been used when, for example, it is desired to separate a desired signal component from an input signal having a poor S / N ratio, or to detect a phase difference between an input signal and a reference signal. Is done. Such a synchronous detection circuit may be configured on a single circuit or on an integrated circuit together with other functional circuits in order to reduce the size and weight of the circuit and improve convenience and reliability.

FIG. 6 shows a conventional synchronous detection circuit thus constructed on an integrated circuit. As shown in FIG. 6, a conventional synchronous detection circuit formed on an integrated circuit includes an operational amplifier OPa, an input terminal Tin to which an input signal Sin to be subjected to synchronous detection is input, an inverting input terminal of the operational amplifier OPa, and a non-inverting input terminal. Resistors Ra and Rc respectively connecting to the inverting input terminal
A resistor Rb connecting the inverting input terminal and the output terminal of the operational amplifier OPa; and a non-inverting input terminal of the operational amplifier OPa, a reference voltage V which is a zero crossing point voltage of the input signal Sin.
an analog switch including NPN transistors TR1 and TR2 for switching whether or not to apply tb; a reference signal Sc input to a reference signal input terminal Tc and a determination voltage Vta (Vta: zero-cross point voltage of the reference signal) And when the reference signal Sc is lower than the determination voltage Vta, a high-level drive signal is generated, and the analog switch (NP
And a comparator 32 for turning on the N transistors TR1 and TR2). The output from the operational amplifier OPa is output from the output terminal Tout as an output signal Sout after synchronous detection.

In the conventional synchronous detection circuit configured as described above, if the reference signal Sc is equal to or higher than the determination voltage Vta, an analog switch (NPN transistors TR1 and TPN) is used.
R2) is turned off, and a signal (positive-phase signal) having the same phase as the input signal Sin is output from the operational amplifier OPa.
If the reference signal Sc is lower than the determination voltage Vta, the reference voltage Vtb is applied to the non-inverting input terminal of the operational amplifier OPa, and the operational amplifier OPa changes the phase of the input signal Sin by 180.
An inverted phase signal is output.

As a result, the output signal Sout becomes the input signal S
When the phase of in matches the reference signal Sc, the input signal Sin has a full-wave rectified signal waveform. When the phase of the input signal Sin is inverted by 180 degrees with respect to the reference signal Sc, the input signal Sin Is a signal waveform obtained by inverting the signal waveform obtained by performing full-wave rectification. Therefore, for example, if the output signal Sout is integrated using a low-pass filter or the like, the signal level changes in accordance with the phase difference between the input signal Sin and the reference signal Sc (the smaller the phase difference, the higher the signal level). A signal can be obtained.

[0006]

However, in the above-mentioned conventional synchronous detection circuit, the analog switches (NPN transistors TR1 and TR2) are turned on / off in accordance with the polarity of the reference signal Sc, and the non-inverting input terminal of the operational amplifier OPa is turned on. By switching whether or not to apply the reference voltage Vtb to the input signal Sin, the output signal Sout is switched between the same phase (positive phase) and the opposite phase with the input signal Sin, so that the phase characteristic of the operational amplifier OPa ( The switching speed of the output signal Sout from the normal phase to the negative phase and from the negative phase to the normal phase is limited by the operation delay due to the change of the input signal), and the frequency (operating limit frequency) of the signal capable of synchronous detection is increased. There was a problem that can not be.

When the reference signal Sc is lower than the judgment voltage Vta and the analog switch (NPN transistor T
When turning on (R1, TR2), a voltage obtained by adding the saturation voltage of the NPN transistors TR1, TR2 to the reference voltage Vtb is applied to the non-inverting input terminal of the operational amplifier OPa. The negative phase signal is offset by this saturation voltage, and the output signal S
There is also a problem that the accuracy of out decreases.

The present invention has been made in view of the above problems, and has as its object to increase the operating limit frequency of a synchronous detection circuit formed on an integrated circuit and improve the accuracy of an output signal.

[0009]

According to the first aspect of the present invention, there is provided a synchronous detection circuit having two signal paths from an input terminal of an input signal to an output terminal. On the first signal path of
A phase inversion circuit for inverting the phase of the input signal by 180 degrees;
A first analog switch for conducting / cutting off a path from the phase inversion circuit to the output terminal is provided. On the second signal path of the two signal paths, a second analog switch for conducting / cutting off this path is provided.

[0010] Then, the rectangular wave generating circuit generates a rectangular wave in phase with the reference signal, and the drive circuit generates the first and second analog signals in accordance with the switching of the signal level of the generated rectangular wave. The on / off states of the switches are alternately switched so as to be different from each other. That is, in the present invention, the first
A phase inversion circuit provided in the signal path of the above always generates an inverted phase signal in which the phase of the input signal is inverted by 180 degrees, so that the input signal is transmitted from the first signal path and the second signal path to the output terminal. The inverted inverted phase signal and the in-phase signal having the same phase as the input signal can be output at any time, and one of the two analog switches provided in each signal path is set to a rectangular wave phase-synchronized with the reference signal. By alternately turning on according to the signal level, it is possible to switch between outputting a normal-phase signal and a reverse-phase signal from the output terminal.

The first and second analog switches for this switching include an n-channel MOSFET.
And a p-channel MOSFET. Therefore, according to the present invention, switching between the two outputs of the normal phase and the negative phase synchronized with the reference signal can be performed at high speed by using two analog switches composed of CMOS analog switches. Is not greatly distorted, so that the operating limit frequency can be greatly increased as compared with the conventional circuit shown in FIG. In addition, the CMOS analog switch merely conducts and cuts off the signal path, and unlike the analog switch of the conventional circuit shown in FIG. 6, does not offset the reverse phase signal due to its saturation voltage. Signal accuracy can be ensured, and a highly accurate synchronous detection circuit can be configured on an integrated circuit.

Here, the phase inversion circuit only needs to be able to invert the phase of the input signal by 180 degrees, and various circuits conventionally used for phase inversion, such as a phase shifter, can be used. Since the level of the inverted signal after the phase inversion needs to be the same as that of the input signal, the phase inversion circuit is configured by an inverting amplifier circuit including an operational amplifier as described in claim 2. Is desirable.

That is, in the inverting amplifier circuit composed of the operational amplifier, the amplification factor is determined only by the resistance ratio of the resistor connected to the operational amplifier. In order to make the signal level after the phase inversion correspond to the input signal, the amplification factor must be adjusted. It is only necessary to set the resistance ratio of the resistor connected to the operational amplifier so that it becomes “1”. Therefore, if the phase inverting circuit is configured by an inverting amplifying circuit including the operational amplifier, an ideal antiphase signal can be extremely reduced. It can be easily generated.

When the phase inverting circuit is constituted by an inverting amplifying circuit comprising an operational amplifier, the inverted phase signal after the phase inversion is delayed with respect to the input signal due to the phase characteristic of the operational amplifier. In order to use at a higher frequency, a voltage follower circuit including an operational amplifier is provided on a path closer to the input terminal than the second analog switch in the second signal path, and It is desirable that the phase signal is also delayed with respect to the input signal due to the phase characteristics of the operational amplifier. By doing so, the phases of the opposite-phase signal and the in-phase signal, which are switched in synchronization with the reference signal, completely match, and the operation limit frequency of the synchronous detection circuit can be further increased.

Next, in the present invention, the phase of the output signal with respect to the input signal is switched using a CMOS analog switch. However, n-channel and p-channel MOSFETs constituting the CMOS analog switch are used.
Has a parasitic capacitance between the gate and the source (drain) because of its structure. Therefore, when the first and second analog switches are turned on and off, the differential waveform of the control signal from the drive circuit is included in the output signal. It may be superimposed as noise.

In order to suppress such noise,
According to a fourth aspect of the present invention, the drive circuit is configured to simultaneously turn on the analog switches for a predetermined period when the signal level of the rectangular wave is inverted to switch the on / off state of each analog switch. It is desirable.

That is, a signal processing circuit such as a low-pass filter is normally connected to the output terminal of the synchronous detection circuit for integrating the output signal after the synchronous detection. The input impedance of the signal processing circuit is generally , Set higher. In the case where two CMOS analog switches are provided on the output terminal side to switch between a normal phase signal and a negative phase signal and are turned on alternately as in the present invention, the CMOS analog switch A differential waveform of a control signal input to the gate of each MOSFET is generated according to the parasitic capacitance of the n-channel and p-channel MOSFETs and the impedance at the output terminal side, and this is superimposed on the output signal as noise. Can be considered. However, this noise can be suppressed by lowering the impedance on the output terminal side. As described above, when the analog switches are turned on and off, if the analog switches are simultaneously turned on for a predetermined period, the impedance of the output terminal can be reduced, and the noise superimposed on the output signal can be reduced. It becomes possible to suppress.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a configuration of a synchronous detection circuit according to an embodiment to which the present invention is applied. The synchronous detection circuit according to the present embodiment processes, for example, a detection signal from an angular velocity sensor used for detecting a yaw rate of an automobile, a camera shake of a video camera, and the like to detect the magnitude of the angular velocity. A BiCMOS type IC which is used together with a control circuit for controlling a control target in accordance with the detected angular velocity.
Alternatively, it is incorporated in a MOS type IC.

As shown in FIG. 1, in the synchronous detection circuit of the present embodiment, an input terminal Tin to which an input signal Sin to be subjected to synchronous detection is input is connected to an output terminal Tout for outputting an output signal Sout after synchronous detection. The leading signal path is separated into two systems. On one signal path, the inverting input terminal is connected to the input terminal Tin via the resistor R1.
An inverting amplifier circuit 12 comprising an operational amplifier OP1 having an inverting input terminal and an output terminal connected via a resistor R2 and a non-inverting input terminal applied with a reference voltage Vt2, which is a zero-cross point voltage of the input signal Sin, is provided. On the other signal path, an inverting input terminal is connected to an input terminal Tin via a resistor R3 for input protection, and a voltage follower circuit (hereinafter referred to as a voltage follower circuit) including an operational amplifier OP2 in which a non-inverting input terminal and an output terminal are directly connected. , Simply referred to as a buffer circuit) 14.

The inverting amplifier circuit 12 is for inverting the phase of the input signal Sin by 180 degrees (that is, a phase inverting circuit), and has a resistance ratio between the resistors R1 and R2 for determining the amplification factor. Are set one-to-one so that the amplification factor is “1”. Also, on each of these signal paths,
Inverting amplifier circuit 12, buffer circuit 14, and output terminal Tou
Analog switches 16 and 18 are provided to turn on and off the paths between the switches t and t, respectively. Each of the analog switches 16 and 18 is a p-channel MOSFET.
T: Q11, Q21 and n-channel MOSFET: Q12, Q
22 CMOS analog switches.

The analog switches 16 and 18 invert control signals φ1 and φ2 input to the gates of the p-channel MOSFETs Q11 and Q21 with respect to the gates of the n-channel MOSFETs Q12 and Q22. Inverters INV1 and INV2 are provided for inputting the analog switches 16 and 18, and when the control signals φ1 and φ2 are at a low level, the analog switches 16 and 18 are turned on (ON).

Next, the synchronous detection circuit of the present embodiment includes:
A rectangular wave phase-synchronized with a reference signal Sc input from an input terminal Tc for inputting a reference signal (hereinafter referred to as a reference pulse).
A comparator 2 as a rectangular wave generating circuit for generating Pc, and a reference pulse P output from the comparator 2
When c is at the low level, the control signal φ1 is set to the low level, the control signal φ2 is set to the high level, the analog switch 16 is turned on and the analog switch 18 is turned off, and the reference pulse Pc is set at the high level. At one time, there is provided a waveform shaping circuit 10 for controlling the analog switch 16 to an off state and the analog switch 18 to an on state by setting the control signal φ1 to a high level and the control signal φ2 to a low level.

The comparator 2 compares the reference signal Sc with a judgment voltage Vt1 which is a zero-crossing point voltage of the reference signal Sc. When the reference signal Sc has a positive polarity equal to or higher than the judgment voltage Vt1, the comparator 2 outputs a reference pulse. Pc is set to a high level, and the reference pulse Pc is set to a low level when the reference signal Sc has a negative polarity lower than the determination voltage Vt1.

The waveform shaping circuit 10 corresponds to a driving circuit according to the present invention. In the present embodiment, as shown in FIG. 2, for example, control for changes in the reference pulse Pc output from the comparator 2 is performed. By delaying the rising timing of the signals φ1 and φ2 by a predetermined time Δt, the reference pulse Pc changes and each analog switch 1
When the on / off states of the switches 6 and 18 are switched, the control signals φ1 and φ2 are simultaneously temporarily set to the low level, and the analog switches 16 and 18 are simultaneously turned on for a predetermined time Δt.

In the synchronous detection circuit according to the present embodiment having the above-described configuration, as shown in FIG. 3, an inversion signal in which the phase of the input signal Sin is inverted is output from the inverting amplifier circuit 12 to the analog switch 16 side. And the buffer circuit 14
Outputs the same positive-phase signal as the input signal Sin to the analog switch 18 side. If the reference signal Sc has a positive polarity and the reference pulse Pc is at a high level, the analog switch 18 is turned on and the analog switch 16 is turned off, and a positive-phase signal is output from the output terminal Tout.
If the reference signal Sc has a negative polarity and the reference pulse Pc has a low level, the analog switch 16
Is turned on, the analog switch 18 is turned off, and an inverted-phase signal is output as an output signal Sout from the output terminal Tout.

As a result, as in the conventional synchronous detection circuit shown in FIG. 6, the output signal Sout is output when the phase difference between the input signal Sin and the reference signal Sc is "0 °" as shown in FIG. Is a signal waveform obtained by full-wave rectifying the input signal Sin, and the phase difference between the input signal Sin and the reference signal Sc is “1”.
80 ° ”, the input signal Sin becomes a signal waveform obtained by inverting the signal waveform obtained by full-wave rectification. If the phase difference of the input signal Sin with respect to the reference signal Sc is“ 90 ° ”, the input signal Sin Are cut at the peak position every 180 degrees and arranged in order. That is, the output signal S
out changes according to the phase difference between the input signal Sin and the reference signal Sc. If the output signal Sout is integrated using a low-pass filter or the like, the phase difference (extension) of the input signal Sin with respect to the reference signal Sc is increased. Thus, a detection signal whose signal level changes in accordance with the angular velocity detected by the angular velocity sensor) can be obtained.

In the present embodiment, in order to obtain such an output signal Sout, an inverting amplifier circuit 12 and a buffer circuit 14 use an inverting signal obtained by inverting the input signal Sin and a positive-phase signal having the same phase as the input signal. Are always generated, and the switching of the output of these two signals is performed individually using the two analog switches 16 and 18 composed of CMOS analog switches. Can be switched at high speed. The inverted signal generated by the inverting amplifier circuit 12 is delayed with respect to the input signal Sin by the phase characteristics of the operational amplifier OP1 included in the inverting amplifier circuit 12. To pass
The phase of the negative phase signal and the phase of the normal phase signal do not shift. As a result, when the output signal Sout is switched from the normal phase to the negative phase and from the negative phase to the normal phase, no error occurs in the output signal Sout, and the operation limit frequency is greatly increased as compared with the conventional synchronous detection circuit. Can be improved (enhanced). The level of the inverted signal generated by the inverting amplifier circuit 12 is
The output signal S is determined by only the resistance ratio between the resistor R1 and the resistor R2 and can be made to correspond to the input signal Sin.
Out accuracy can be ensured, and a highly accurate synchronous detection circuit can be configured on the integrated circuit.

In this embodiment, the analog switch 1
When the on / off states of the switches 6 and 18 are switched, the control signals φ1 and φ2 output from the waveform shaping circuit 10 go low at the same time for a predetermined time Δt, and the analog switches 16 and 18 are turned on for a predetermined time Δ At the time of this switching, the impedance of the output terminal Tout is reduced, and the MOSFETs Q11, Q12, Q
Noise caused by the parasitic capacitance between each gate of the transistors 21 and Q22 and the output terminal can be reduced.

That is, the output terminal Tout of the synchronous detection circuit
Is usually connected to a low-pass filter. In general, the input impedance of the low-pass filter is set high. On the other hand, p constituting the analog switches 16 and 18
Since the channel and n-channel MOSFETs have a parasitic capacitance between the gate and the source and between the gate and the drain due to the structure, the MOSFETs Q11, Q12, Q21, and Q22 are caused by the parasitic capacitance as shown by the dotted line in FIG. And a capacitor C is connected between each gate and the output terminal. As a result, when the control signals φ1 and φ2 are simultaneously changed, the capacitor C due to the parasitic capacitance and the output terminal T
Due to the impedance on the out side, a differential waveform of the control signals φ1 and φ2 appears on the output terminal Tout side, which becomes noise and is output from the output terminal Tout.

Therefore, in this embodiment, the control signals φ1, φ
2, when the control signals φ1 and φ2 are both at a low level and the analog switches 16 and 18 are simultaneously turned on to create an area (time Δt), the output terminal Tou
The impedance on the t side is changed by the two operational amplifiers OP1 and OP
The output impedance of P2 is reduced to a value connected in parallel, so that the peak value of the differential waveform of the control signal output as noise is kept low. Therefore, according to the synchronous detection circuit of this embodiment, the noise output from the output terminal Tout can be reduced, and the accuracy of the output signal Sout can be improved.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various embodiments can be adopted. For example, in the above embodiment, in order to ensure that the phase difference between the positive-phase signal input to the analog switch 18 and the negative-phase signal input from the inverting amplifier circuit 12 to the analog switch 16 is 180 degrees, Although the buffer circuit 14 is provided on the signal path for inputting the positive-phase signal to the analog switch 18, the synchronous detection circuit can ignore the phase shift between the negative-phase signal generated by the inverting amplifier circuit 12 and the input signal Sin. When used in the frequency domain, as shown in FIG.
4, the input terminal Tin may be directly connected to the analog switch 18 for outputting the positive-phase signal via the input protection resistor R3.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram illustrating a configuration of a synchronous detection circuit according to an embodiment.

FIG. 2 shows control signals φ1, output from a waveform shaping circuit.
FIG. 4 is an explanatory diagram illustrating φ2.

FIG. 3 is an explanatory diagram illustrating a relationship between an input signal and an output signal and a signal waveform generated in a synchronous detection circuit according to an embodiment.

FIG. 4 is an explanatory diagram illustrating parasitic capacitance of a CMOS analog switch and noise generated by the parasitic capacitance.

FIG. 5 is an electric circuit diagram illustrating another configuration example of the synchronous detection circuit according to the embodiment.

FIG. 6 is an electric circuit diagram showing a configuration of a conventional synchronous detection circuit.

[Explanation of symbols]

2 Comparator (rectangular wave generation circuit) 10 Waveform shaping circuit 12 Inverting amplifier circuit (phase inverting circuit) OP1 Operational amplifier 14 Buffer circuit (voltage follower circuit) O
P2: operational amplifier 16, 18, analog switch (CMOS analog switch) Q11, Q21, Q12, Q22: MOSFET R1 to R3
... Resistor INV1, INV2 ... Inverter

Claims (4)

[Claims] 1. A synchronous detection circuit configured on an integrated circuit for extracting a signal component synchronized with a reference signal from an input signal, comprising two signal paths from an input terminal to an output terminal of the input signal. A phase inverting circuit for inverting the phase of the input signal by 180 degrees on a first signal path, and a first inverting circuit for conducting and blocking a path from the phase inverting circuit to the output terminal.
, And on the second signal path,
A second analog switch for conducting / cutting off the path, wherein the first and second analog switches are respectively connected to n
A rectangular wave generating circuit configured to generate a rectangular wave in phase with the reference signal, and configured by a CMOS analog switch including a channel MOSFET and a p-channel MOSFET; According to the switching of the signal level of the rectangular wave, the on / off states of the first and second analog switches are alternately switched so as to be different from each other, and the signal is output from one of the first and second analog switches. A synchronous detection circuit, comprising: a driving circuit that outputs a signal; 2. The synchronous detection circuit according to claim 1, wherein said phase inversion circuit is constituted by an inversion amplification circuit comprising an operational amplifier. 3. The synchronization according to claim 2, wherein a voltage follower circuit comprising an operational amplifier is provided on a path of the second signal path on the input terminal side of the second analog switch with respect to the second analog switch. Detection circuit. 4. The drive circuit according to claim 1, wherein when the signal level of the rectangular wave is inverted and the on / off state of each of the analog switches is switched, each of the analog switches is simultaneously turned on for a predetermined period. The synchronous detection circuit according to claim 1.