JPH0865113A - Signal synchronization circuit and signal synchronization method - Google Patents

Abstract

PURPOSE: To obtain synchronization of two signals by providing 1st and 2nd delay circuits delaying two signals, detecting a phase difference of both signals so as to correct the phase and a duty ratio. CONSTITUTION: When a phase of a BI signal is delayed more than an AI signal being an object of synchronization even if the frequency of the signals is the same and when the signal AI and the other signal BI with an optional duty ratio are given to a phase detection circuit 12, the circuit 12 detects a phase difference ϕ. When the signals AI, BI are both at an L or an H level, a phase detection signal S1 at an L level is outputted to a phase correction circuit 14. When either of the signals AI, BI is at an H level, the phase detection signal S1 at an H level is outputted to the phase correction circuit 14. On the other hand, a delay signal S2 to correct the signal delay in the phase detection circuit 12 is outputted from the phase correction circuit 14 based on the phase detection signal S1. The duty ratio of the delay signal S2 is in matching with the duty ratio of the signal AI by the phase detection signal S1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synchronizing circuit, and more particularly to a circuit for correcting a phase difference between two signals having the same frequency but different phases and different duty ratios to align signal waveforms. It is a thing. In recent years, data communication is performed by connecting information processing devices via a communication line. At this time, when the reception signal from the communication line is taken in, it is necessary to synchronize the signal coming from the outside with the reference signal of the reception circuit inside the device.

According to this, a signal synchronizing circuit is used which corrects the phase difference between two signals having the same frequency and different phases to synchronize one signal with the other signal. But,
If the phase difference between the two signals changes with time or the duty ratio of the two signals fluctuates, synchronization becomes difficult. Therefore, even when the duty ratios of the two signals are different, there is a demand for a circuit that can correct the phase of one of the duty ratio signals and make it equal to the other of the duty ratio signals.

[0003]

2. Description of the Related Art FIG. 13 is an explanatory diagram related to a conventional example.
13A is a configuration diagram of a signal synchronizing circuit according to a conventional example, and FIG. 13B is an operation waveform diagram for explaining the problem. For example, an incoming signal BI from the outside
As shown in FIG. 13 (A), the signal synchronizing circuit for synchronizing the input signal BI with the reference signal AI of the receiving circuit comprises a non-inverter 1 for synchronizing the incoming signal BI with the reference signal AI.

The function of the signal synchronization circuit is, for example, as shown in FIG.
As shown in 13 (B), the reference signal A with a duty ratio of 6: 4
When the incoming signal BI having a duty ratio of 8: 2 is synchronized with I, and the signal BI is delayed from the signal AI by the phase difference φ, the optimum number of delay stages of the non-inverter 1 is obtained, It is fixed to the optimum value where the phase difference φ = 0.

As a result, the rising edge of the reference signal AI = AO and the rising edge of the output signal BO obtained by phase-correcting the incoming signal BI are synchronized. The signal AI = AO has a duty ratio of 6: 4, and the output signal BO has a duty ratio of 8: 2.

[0006]

By the way, according to the conventional example, the signal synchronizing circuit is constituted by the non-inverter 1 and the number of delay stages is variable with respect to the two signals AI and BI whose duty ratios are fixed. By doing so, the phase is corrected. Therefore, if the phase difference φ is always constant, the duty ratios do not match, but a request for synchronizing both signals AI and BI is made by a signal synchronizing circuit using a non-inverter as shown in FIG. 13 (A). Can deal with enough. However, if the phase difference φ between the two signals AI and BI changes with time or the duty ratio of both signals AI and BI fluctuates, the method of varying the number of delay stages of the non-inverter 1 can be sufficiently dealt with. Can not. Phase correction must be performed each time.

As a result, the signal B of unknown duty ratio
When there is a request for signal synchronization in which I is aligned with the reference signal AI having an arbitrary duty ratio, there is a problem that the phase correction method that varies the number of delay stages of the non-inverter 1 as in the conventional example cannot sufficiently cope with it. The present invention was created in view of the problems of the conventional example, and even when the duty ratios of two signals are different, the signal of one duty ratio is phase-corrected and the duty of the other signal is corrected. An object of the present invention is to provide a signal synchronization circuit that can be matched to a ratio signal.

[0008]

FIG. 1 shows a principle diagram of a signal synchronizing circuit according to the present invention. As shown in FIG. 1, a first signal synchronizing circuit of the present invention synchronizes with a first delay circuit 11 for delaying one signal AI as a synchronization target, the one signal AI and the one signal AI. The phase detection circuit 12 for detecting the phase difference φ from the other signal BI, the second delay circuit 13 for delaying the other signal BI, and the phase detection signal S1 from the phase detection circuit 12 A phase correction circuit 14 for correcting the phase of the delay signal S2 from the second delay circuit 13 and for correcting the duty ratio of the delay signal S2 based on the rising or falling of the phase detection signal S1. Is characterized by.

In the first signal synchronization circuit of the present invention,
The first delay circuit 11 and the second delay circuit 12 are composed of non-inverters. The second signal synchronization circuit of the present invention is characterized in that the first delay circuit 11 and the second delay circuit 12 are formed by an exclusive OR circuit for supplying a low potential to one input.

The third signal synchronizing circuit according to the present invention comprises one output signal A delayed by the first delay circuit 11.
A first adjusting element 15 for adjusting the timing of O and a second adjusting element 16 for adjusting the timing of the output signal BO from the phase correction circuit 14 are provided.
In the third signal synchronization circuit of the present invention, the first adjusting element 15 and the second adjusting element 16 are connected to the output of the first delay circuit 11 and the output of the phase correcting circuit 14, respectively. It is characterized by comprising a capacitor C.

In a fourth signal synchronizing circuit of the present invention, the first adjusting element 15 and the second adjusting element 16 are the first adjusting element 15 and the second adjusting element 16.
Of the delay circuit 11 and the output of the phase correction circuit 14 in the opposite direction. In the first to fourth signal synchronization circuits of the present invention, the phase detection circuit 12 and the phase correction circuit 14 are constituted by an exclusive OR circuit.

In the signal synchronization method of the present invention, the first exclusive OR of one signal AI having an arbitrary duty ratio as a synchronization target and the other signal BI synchronized with the one signal AI is taken, A second exclusive OR of the output signal S1 obtained by the first exclusive OR and the signal S2 obtained by delaying the other signal BI is used. In the signal synchronization method of the present invention, the duty ratio of the one signal AI is variable, and the above object is achieved.

[0013]

[Operation] FIG. 1 shows the operation of the first signal synchronization circuit of the present invention.
Will be described with reference to. For example, when the frequencies of the signals are the same and the phase of the BI signal lags behind the synchronization target AI signal, the signal AI having an arbitrary duty ratio and the other signal BI are input to the phase detection circuit 12. , The phase difference φ is detected by the circuit 12. This phase difference φ
Is the difference between the signal rising edges of the signal AI and the signal BI, for example, and is the “H” level period of the phase detection signal S1.

The phase detection signal S1 detected here is when the signals AI and BI are both at the "L" level, and when both are at the "H" level, the signal S1 = "L" level is the phase correction circuit. It is output to 14. Further, when one of the signals AI or BI is at the “H” level, the signal S1
= “H” level is output to the phase correction circuit 14. On the other hand, in order to correct the signal delay in the phase detection circuit 12,
For example, when the other signal BI is delayed by the second delay circuit 13 including a non-inverter, this delayed signal S2
Is corrected by the phase correction circuit 14 based on the phase detection signal S1 from the phase detection circuit 12. The duty ratio of the delay signal S2 is adjusted to the duty ratio of the signal AI by the rising or falling of the phase detection signal S1. As a result, the output (exclusive OR) signal BO is obtained from the phase correction circuit 14.

This output signal BO becomes signal BO = “L” level when both signals S1 and S2 are at “L” level, and when both are at “H” level. Also,
When either one of the signals S1 and S2 is at "H" level, the signal BO becomes "H" level. Therefore, the output signal BO from the phase correction circuit 14 can be synchronized with the output signal AO from the first delay circuit 11. The first delay circuit 11 aligns the signal delay amount due to the phase detection and correction of the signal BI and the delay amount of the signal AI.

As a result, even when the phase difference φ between the two signals AI and BI changes with time or the duty ratio of both signals AI and BI changes, compared to the conventional example.
Both signals AI and BI can be easily synchronized, and it becomes possible to sufficiently cope with the synchronization of the received signals. According to the second signal synchronization circuit of the present invention, "L" is applied to one input.
A first delay circuit 11 and a second delay circuit 12 which are exclusive OR circuits to which levels are supplied are provided.

Therefore, even if the phase difference φ between the two signals AI and BI changes with time or the duty ratio of the two signals AI and BI changes, the second delay formed by the exclusive OR circuit is used. When the other signal BI is delayed by the circuit 13, this delay signal S2 is phase-corrected by the phase correction circuit 14 based on the phase detection signal S1 from the phase detection circuit 12.

As a result, the first circuit composed of the exclusive OR circuit
Output signal AO from the delay circuit 11 of the phase correction circuit 1
The output signal BO from 4 can be synchronized. According to the third signal synchronizing circuit of the present invention, the first adjusting element 15 and the output signal BO for adjusting the timing of the output signal AO are provided.
A second adjusting element 16 for adjusting the timing is provided.

Therefore, the output signal BO from the phase correction circuit 14 is supplied to the second adjusting element 16 such as the capacitor C.
By adjusting the rising and falling edges (timing adjustment) of the waveform, glitches and noise can be suppressed (blunted). By adjusting the timing of the delay signal AO delayed by the first delay circuit 11 by the first adjusting element 15 such as the capacitor C, the load characteristics of the signal BO and the signal AO can be made uniform.

According to the fourth signal synchronization circuit of the present invention,
Each of the first adjusting element 15 and the second adjusting element 16 is composed of a diode D connected in the opposite direction to the output of the first delay circuit 11 and the output of the phase correction circuit 14.
Therefore, by adjusting the timing of the output signal BO from the phase correction circuit 14 with the diode D, glitches, noises, etc. can be suppressed (blunted).
By adjusting the timing of the delay signal AO with the diode D, the load characteristics of the signal BO and the signal AO can be made uniform.

According to the signal synchronization method of the present invention, when the first exclusive OR of the signal AI having an arbitrary duty ratio and the other signal BI is taken, the output signal S1 and the signal BI obtained by the first exclusive OR are obtained. A second exclusive OR is taken with the delayed signal S2. Therefore, even when the duty ratios of the two signals AI and BI are different, the phase difference between the output signal AO delayed from the signal AI and the output signal BO obtained by the second exclusive OR is calculated. Can be zero,
It is possible to forcibly match the duty ratio of the other signal with the signal of one duty ratio.

As a result, the signal B of unknown duty ratio
It is possible to match I with the signal AI having an arbitrary duty ratio. For example, even when the duty ratio of the signal AI as the synchronization target is changed, the signal BI having an unknown duty ratio can be forcibly aligned with the duty ratio of the signal AI.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, each embodiment of the present invention will be described with reference to the drawings. 2 to 12 are diagrams illustrating a signal synchronization circuit according to each embodiment of the present invention. (1) Description of First Embodiment FIG. 2 is a configuration diagram of a signal synchronization circuit according to a first embodiment of the present invention, and FIG. 3 is an internal configuration diagram of an EXOR circuit according to each embodiment. is there. 4 to 9 are operation waveform diagrams (No. 1)
6) are respectively shown.

For example, the signal synchronizing circuit for synchronizing the incoming signal BI from the outside with the reference signal AI of the receiving circuit is shown in FIG.
As shown in FIG. 3, delay gates 21A, 21B and 23, two-input exclusive OR circuits (hereinafter referred to as EXOR circuits) 22 and 24 are provided. That is, the delay gates 21A and 21B are an example of the first delay circuit 11 in FIG. 1, and delay one signal as a synchronization target, for example, the reference signal AI of the receiving circuit in the communication device or the like. Non-inverters are used for the delay gates 21A and 21B. The delay gates 21A and 21B
The gate delay amount of 1 is made equal to the signal delay amount by the phase detection and correction of the signal BI. This causes the signal BI
And the delay amount of the signal AI becomes equal.

The EXOR circuit 22 is the phase detection circuit 1 of FIG.
2 is an example, and the phase difference between the reference signal AI and the incoming signal BI synchronized with the reference signal AI is detected. For example, E
As shown in FIG. 3, the XOR circuit 22 includes 14 bipolar transistors (hereinafter simply referred to as transistors) Q1 to Q1.
It consists of Q14 and six bias resistors R1 to R6. Q1
Q14 are npn type transistors.

In FIG. 3, the collector of the transistor Q1 is connected to the power supply line Vcc, and the signal BI is input to its base. Its emitter is grounded through the resistor R1 to VEE
, And it is also connected to the base of transistor Q4. The signal AI is input to the bases of the transistors Q2 and Q6. Transistors Q2 to Q8 form a differential amplifier circuit, and collectors of transistors Q2 and Q3 are connected to power supply line Vcc through resistors R2 and R3, respectively. The emitters of the transistors Q2 and Q3 are connected to the collector of the transistor Q4. Transistors Q5, Q
Each emitter of 6 is connected to the collector of transistor Q7.

The collector of the transistor Q5 is connected to the collectors of the transistors Q2 and Q9, and the collector of the transistor Q6 is the collector of the transistor Q3.
Each is connected to the base of Q12. Transistor Q
The emitters of 4 and Q7 are connected to the collector of the transistor Q8. The emitter of Q8 is connected to the ground line VEE via the resistor R4.

The collectors of the transistors Q9 and Q12 are connected to the power supply line VCC, and the emitter of Q9 is the transistor Q10.
Is connected to the base and collector of Q12, and the emitter of Q12 is connected to the base and collector of transistor Q13. The emitters of the transistors Q10 and Q13 are transistors Q11 and Q, respectively.
The collectors of 14 are respectively connected, and the emitters of Q11 and Q14 are respectively connected to the ground line VEE via resistors R5 and R6. The bias voltage VBB is supplied to the bases of the transistors Q8, Q11, and Q14, and the reference voltage VREF is supplied to the base of the transistor Q7.

The delay gate 23 is the second delay circuit 1 of FIG.
3 is an example of delaying the incoming signal BI. In the present embodiment, the delay gate 23 uses a non-inverter like the delay gates 21A and 21B. The delay amount of the delay gate 23 is E
The signal delay amount by the XOR circuit 22 should be the same.
As a result, the delay amounts of the signal BI and the incoming delay signal S2 become equal.

The EXOR circuit 24 is the phase correction circuit 1 of FIG.
4 is an example of the delay arrival signal S2 from the delay gate 23 based on the phase detection signal S1 from the EXOR circuit 22.
And the duty ratio of the signal S2 is corrected based on the rising or falling of the phase detection signal S1. The EXOR circuit 24 uses the same circuit as the EXOR circuit 22.

Next, the operation of the signal synchronizing circuit according to the first embodiment of the present invention will be described. For example, as shown in FIG. 4, when an incoming signal (hereinafter referred to as BI signal) is synchronized with a reference signal (hereinafter referred to as AI signal) having the same frequency, the phase of the BI signal is delayed from that of the AI signal ( The case of the phase difference φ) will be described. The duty ratios of the two signals may be variable, and the two signals may be input via different transmission paths or transmission systems.

In this case, for example, when the signal AI with the duty ratio of 5: 5 and the incoming signal BI are input to the EXOR circuit 22, the phase difference φ between them is detected by the circuit 22. This phase difference φ is, for example, the difference between the rising edges of the signal AI and the signal BI, and is “H” of the phase detection signal S1.
It is the level period. Phase detection signal S detected here
1 is the signal S1 = when both the signals AI and BI are at the “L” level and when both are at the “H” level.
The “L” level is output to the EXOR circuit 24. Also,
When either the signal AI or BI is at the “H” level, the signal S1 = “H” level is output to the EXOR circuit 24.

On the other hand, when the incoming signal BI is delayed by the delay gate 23 in order to correct the signal delay in the EXOR circuit 22, the delayed incoming signal S2 becomes the EXOR circuit 2
The EXOR circuit 24 based on the phase detection signal S1 from 2
The phase is corrected by. As a result, the output (exclusive OR) signal BO is obtained from the EXOR circuit 24. This output signal BO is the signal B when the signals S1 and S2 are both at the “L” level and when both are at the “H” level.
O = “L” level. Further, when either one of the signals S1 and S2 is at "H" level, the signal BO becomes "H" level.

As a result, the output signal BO from the EXOR circuit 24 is synchronized with the output signal AO from the delay gate 21B. The delay gates 21A and 21B enable the signal B
The signal delay amount due to the phase detection and correction of I and the delay amount of the signal AI are made uniform. Next, as shown in FIG. 5, in the case where the BI signal is synchronized with the AI signal having the same frequency and the phase of the BI signal is ahead of the AI signal (phase difference φ), both signals are The case where the duty ratio of AI and BI is 5: 5 will be described.

In this case, the signal AI and the incoming signal BI are E
When input to the XOR circuit 22, the phase difference φ is detected by the circuit 22. The phase detection signal S1 detected here is output to the EXOR circuit 24. On the other hand, the delayed arrival signal S2 from the delay gate 23 is transferred to the EXOR circuit 22.
The phase is corrected by the EXOR circuit 24 based on the phase detection signal S1 from the signal A1 and the duty ratio of the signal AI is 5:
It is adjusted to 5. Thus, the output signal AO from the delay gate 21B is added to the output signal BO from the EXOR circuit 24.
Are synchronized.

As shown in FIG. 6, when the BI signal is synchronized with the AI signal having the same frequency and the BI signal and the AI signal are in phase (phase difference φ = 0), EX
The phase detection signal S1 from the OR circuit 22 becomes "L" level. Further, as shown in FIG. 7, when the BI signal is synchronized with the AI signal having the same frequency,
180 ° out of phase with the I signal (phase difference φ =
180 °), the phase detection signal S1 from the EXOR circuit 22 becomes "H" level.

Next, as shown in FIG. 8, when the phase of the BI signal lags behind the AI signal (phase difference φ), and the duty ratio of the signal AI is 8: 4, When the duty ratio of the signal BI is 3: 9,
A case where the BI signal is synchronized with the AI signal will be described. In this case, the signal AI and the incoming signal BI are the EXOR circuit 22.
Is input to the circuit 22, the phase difference φ is detected by the circuit 22. The phase detection signal S1 detected here is EXO
It is output to the R circuit 24. Further, the duty ratio 3: 9 of the delayed arrival signal S2 is forcibly adjusted to the duty ratio 8: 4 of the signal AI by the second rising from the first rising of the phase detection signal S1.

On the other hand, the delayed arrival signal S2 from the delay gate 23 is phase-corrected by the EXOR circuit 24 based on the phase detection signal S1 from the EXOR circuit 22, and is also adjusted to the duty ratio 8: 4 of the signal AI. . As a result, the duty ratio 8: 4 from the EXOR circuit 24 is added to the output signal AO with the duty ratio 8: 4 from the delay gate 21B.
Output signals BO of are synchronized.

Further, as shown in FIG. 9, when the phase of the BI signal lags behind the AI signal (phase difference φ), and the duty ratio of the signal AI is 8: 4, When the BI duty ratio is 10: 2,
A case where the BI signal is synchronized with the AI signal will be described. In this case, the signal AI and the incoming signal BI are the EXOR circuit 22.
Is input to the circuit 22, the phase difference φ is detected by the circuit 22. The phase detection signal S1 detected here is EXO
It is output to the R circuit 24. The duty ratio 10: 2 of the delayed arrival signal S2 is forcibly adjusted to the duty ratio 8: 4 of the signal AI from the first rising of the phase detection signal S1 to the second rising thereof.

On the other hand, the delayed arrival signal S2 from the delay gate 23 is phase-corrected by the EXOR circuit 24 based on the phase detection signal S1 from the EXOR circuit 22, and is also adjusted to the duty ratio 8: 4 of the signal AI. . As a result, the duty ratio 8: 4 from the EXOR circuit 24 is added to the output signal AO with the duty ratio 8: 4 from the delay gate 21B.
Output signals BO of are synchronized.

As described above, the signal synchronizing circuit according to the first embodiment of the present invention includes the delay gates 21A, 21B, 23 and the EXOR circuits 22 and 24, as shown in FIG. Therefore, the output signal AO from the delay gate 21B
The output signal BO from the EXOR circuit 24 can be synchronized with. At this time, by the delay gates 21A and 21B,
The signal delay amount due to the phase detection and correction of the signal BI and the delay amount of the signal AI are made uniform.

As a result, even if the phase difference φ between the two signals AI and BI changes with time or the duty ratio of the two signals AI and BI changes, both signals A and BI can be easily changed.
I and BI phase correction and duty ratio correction can be performed at the same time, and it becomes possible to sufficiently cope with synchronization of received signals. Further, according to the signal synchronization method according to the embodiment of the present invention, when the first exclusive OR of the signal AI with the arbitrary duty ratio and the incoming signal BI is taken, the output signal S1 obtained thereby, Signal S delayed from signal BI
A second exclusive OR with 2 is taken.

Therefore, even when the duty ratios of the two signals AI and BI are different, the output signal AO obtained by delaying the signal AI and the output signal BO obtained by the second exclusive OR are obtained. It is possible to synchronize, and moreover, it is possible to correct the phase of the signal BI having one duty ratio so that the signal BI having the other duty ratio can be aligned. This makes it possible to match the signal BI having an unknown duty ratio with the signal AI having an arbitrary duty ratio. For example,
Even if the duty ratio of the synchronization target signal AI is varied, the signal BI having an unknown duty ratio is forced to the signal A.
The duty ratio can be set to I.

(2) Description of Second Embodiment FIG. 10 shows a block diagram of a signal synchronization circuit according to a second embodiment of the present invention. Unlike the first embodiment, the second embodiment is provided with a two-input exclusive OR circuit (hereinafter simply referred to as an EXOR circuit) in which the “L” level is supplied to the reference input. That is, as shown in FIG. 10, the signal synchronizing circuit according to the second embodiment includes five EXOR circuits 31A, 31B, 3
2, 33 and 34. EXOR circuits 31A and 31B
1 is another example of the first delay circuit 11 shown in FIG. 1. The reference signal AI is input to one input of the circuit 31A, and the “L” level is supplied to the reference input.

The logical output signal from the circuit 31A is input to one input of the EXOR circuit 31B, and the "L" level is supplied to its reference input. As a result, the output signal AO obtained by delaying the signal AI is obtained from the circuit 31B. EXO
The R circuit 33 is another example of the second delay circuit 13 shown in FIG. 1, and the incoming signal BI is input to one input of the circuit 33 and the “L” level is supplied to its reference input. As a result, the delayed arrival signal S2 is output from the circuit 33 to the EXOR circuit 34. The EXOR circuit 32 constitutes a phase detection circuit, and the EXOR circuit 34 constitutes a phase correction circuit. The operation waveforms are the same as those in the first embodiment, so the description thereof will be omitted.

In this way, according to the signal synchronizing circuit of the second embodiment of the present invention, as shown in FIG. 10, the EXOR circuits 31A, 31 having the "L" level supplied to the reference input are supplied.
A delay circuit including B and EXOR circuits 33 is provided.
Therefore, the signal delay amount due to the phase detection and correction of the signal BI can be made equal to the gate delay amount of the EXOR circuits 31A and 31B, and the delay amounts of the signal BI and the signal AI become equal.
Further, the signal delay amount by the EXOR circuit 32 can be made uniform by the gate delay amount of the EXOR circuit 33, and the signal B
The delay amounts of I and the arrival delay signal S2 become equal.

As a result, the EXO is the same as in the first embodiment.
The output signal BO from the EXOR circuit 34 can be synchronized with the output signal AO from the R circuit 31B. Also, the phase difference φ between the two signals AI and BI changes with time,
Even when the duty ratio of both signals AI and BI changes, when the arrival signal BI is delayed by the EXOR circuit 33, the delayed arrival signal S2 is EXORed based on the phase detection signal S1 from the EXOR circuit 32. The phase is corrected by the circuit 34.

As a result, both signals AI and BI can be easily synchronized as in the first embodiment. Further, since the EXOR circuit forming the signal synchronization circuit is manufactured by the same process step, the signal delay amount can be adjusted in a self-aligned manner. (3) Description of Third Embodiment FIGS. 11A and 11B are block diagrams of a signal synchronization circuit according to a third embodiment of the present invention. In the third embodiment, unlike the first and second embodiments, the capacitance C is connected to the output of the delay gate 21B and the output of the EXOR circuit 24.

FIG. 11A shows a circuit in which a capacitor is connected to the output of the signal synchronizing circuit according to the first embodiment. Figure 11
In (A), the capacitor C11 is an example of the first adjustment element 15 and is an element for adjusting the timing of the output signal AO delayed by the delay gates 21A and 21B. Capacity C11
Is connected between the output of the delay gate 21B and the ground line GND so as to be balanced with C12. The capacity C12 is the second
Is an example of the adjustment element 16 of FIG. 1 and is an element for adjusting the timing of the output signal BO from the EXOR circuit 24. The capacitor C12 is connected between the output of the EXOR circuit 24 and the ground line GND.

FIG. 11B shows a circuit in which a capacitor is connected to the output of the signal synchronizing circuit according to the second embodiment. Figure 11
In (B), the capacitor C21 is an element that adjusts the timing of the output signal AO from the EXOR circuit 31B. Capacity C
Reference numeral 22 is an element for adjusting the timing of the output signal BO from the EXOR circuit 34. Since the operation waveform diagram is the same as that of the first embodiment, its explanation is omitted.

In this way, according to the signal synchronizing circuit of the third embodiment of the present invention, as shown in FIGS. 11A and 11B, the capacitance C11 for adjusting the timing of the output signal AO is used.
C12 and a capacitor C12 for adjusting the timing of the output signal BO
And C22 are provided. Therefore, the EXOR circuits 24 and 3
By adjusting the rising and falling (timing adjustment) of the waveform of the output signal BO from 4 with the capacitors C12 and C22, it is possible to suppress (blunt) glitches and noise. By adjusting the timing of the output signal AO from the delay gate 21B and the EXOR circuit 31B with the capacitors C11 and C21, the load characteristics of the signal BO and the signal AO can be made uniform.

As a result, compared with the first and second embodiments, the duty ratio can be made uniform (synchronization) at the same time as the phase correction of both signals AI and BI is performed with higher accuracy. (4) Description of Fourth Embodiment FIGS. 12A and 12B are block diagrams of a signal synchronization circuit according to a fourth embodiment of the present invention. In the fourth embodiment, unlike the third embodiment, a diode is connected to the output of the delay gate 21B and the output of the EXOR circuit 24.

FIG. 12A shows a circuit in which a diode is connected to the output of the signal synchronizing circuit according to the first embodiment. In FIG. 12A, the diode D11 is another example of the first adjusting element 15, and is an element for adjusting the timing of the output signal AO delayed by the delay gates 21A and 21B. The diode D11 is connected in the reverse direction between the output of the delay gate 21B and the ground line GND so as to balance with the diode D12. As a result, a function similar to that of the capacitor C of the third embodiment can be obtained.

In the embodiment of the present invention, the diode D11 is composed of a bipolar transistor. For example, collector
Apply the transistor by connecting the base connected transistor and the base-emitter. In both cases, the emitter is connected to each gate output and the collector is connected to the ground line VEE, respectively. The diode D12 is another example of the second adjustment element 16, and is an element for adjusting the timing of the output signal BO from the EXOR circuit 24.

FIG. 12B shows a circuit in which a diode is connected to the output of the signal synchronizing circuit according to the second embodiment. In FIG. 12B, the diode D21 is an element for adjusting the timing of the output signal AO from the EXOR circuit 31B. The diode D22 is an element for adjusting the timing of the output signal BO from the EXOR circuit 34. Since the operation waveform diagram is the same as that of the first embodiment, its explanation is omitted.

As described above, according to the signal synchronization circuit of the fourth embodiment of the present invention, as shown in FIGS. 12A and 12B, the diode D11 for adjusting the timing of the output signal AO and D21 and diodes D12 and D22 for adjusting the timing of the output signal BO are provided, and are connected in the opposite directions to the output of the delay gate 21B and the outputs of the EXOR circuits 24, 31B and 34, respectively.

Therefore, by adjusting the rising and falling edges (timing adjustment) of the waveform of the output signal BO from the EXOR circuits 24 and 34 by the diodes D12 and D22, glitches and noises are suppressed (blunted).
be able to. The delay gate 21B and the EXOR circuit 31
By adjusting the timing of the output signal AO from B with the diodes D11 and D21, the load characteristics of the signal BO and the signal AO can be made uniform as in the third embodiment.

As a result, similarly to the third embodiment, it is possible to accurately correct the phases of both signals AI and BI and simultaneously align the duty ratios (synchronize).

[0059]

As described above, according to the signal synchronizing circuit of the present invention, the first and second delay circuits for delaying both signals, and the phase detecting circuit for detecting the phase difference between both signals, A phase correction circuit that corrects the phase correction and the duty ratio. Therefore, even if the phase difference between the two signals changes with time or the duty ratio of both signals changes, the delay signal from the second delay circuit is output by the phase correction circuit based on the phase detection signal. By correcting the phase,
The output signal from the phase correction circuit can be synchronized with the output signal from the delay circuit. Further, compared to the conventional example, both signals can be easily synchronized, and it becomes possible to sufficiently cope with the synchronization of the received signals.

According to another signal synchronizing circuit of the present invention, the first adjusting element for adjusting the timing of the output signal and the second adjusting element for adjusting the timing of the output signal are provided.
Therefore, the output signal from the phase correction circuit is adjusted (dulled) by adjusting the rising and falling of the waveform by the second adjusting element.
be able to. Further, the load characteristics of both signals can be made uniform by the first adjusting element.

According to the signal synchronization method of the present invention, when the first exclusive OR of the signal having an arbitrary duty ratio and the other signal is taken, the output signal obtained as a result and the other signal are delayed. The second exclusive OR with the signal is taken. Therefore, even when the duty ratios of the two signals are different, the phase difference between the output signal obtained by delaying one signal and the output signal obtained by the second exclusive OR is set to zero. Therefore, the duty ratio of one signal can be forcibly matched with the duty ratio of the other signal.

As a result, a signal synchronization circuit for adjusting a signal whose communication conditions are strict and whose duty ratio varies to a signal having an arbitrary duty ratio is provided. Further, it greatly contributes to the improvement of reliability of a communication device or the like to which the signal synchronization circuit is applied.

[Brief description of drawings]

FIG. 1 is a principle diagram of a signal synchronization circuit according to the present invention.

FIG. 2 is a configuration diagram of a signal synchronization circuit according to the first embodiment of the present invention.

FIG. 3 is an internal configuration diagram of an EXOR circuit according to each embodiment of the present invention.

FIG. 4 is an operation waveform diagram (1) of the signal synchronization circuit according to each embodiment of the present invention.

FIG. 5 is an operation waveform diagram (No. 2) of the signal synchronization circuit according to each embodiment of the present invention.

FIG. 6 is an operation waveform diagram (No. 3) of the signal synchronization circuit according to each embodiment of the present invention.

FIG. 7 is an operation waveform diagram (No. 4) of the signal synchronization circuit according to each example of the present invention.

FIG. 8 is an operation waveform diagram (No. 5) of the signal synchronization circuit according to each embodiment of the present invention.

FIG. 9 is an operation waveform diagram (6) of the signal synchronization circuit according to each example of the present invention.

FIG. 10 is a configuration diagram of a signal synchronization circuit according to a second embodiment of the present invention.

FIG. 11 is a configuration diagram of a signal synchronization circuit according to a third embodiment of the present invention.

FIG. 12 is a configuration diagram of a signal synchronization circuit according to a fourth embodiment of the present invention.

FIG. 13 is an explanatory diagram of a signal synchronization circuit according to a conventional example.

[Explanation of symbols]

 11, 13 ... First and second delay circuits, 12 ... Phase detection circuit, 14 ... Phase correction circuit, 15, 16 ... First and second adjusting elements, C ... Capacitance, D ... Diode, AI ... One of Signal (reference signal), BI ... Other signal (arrival signal) AO ... Output signal, BO ... Output signal, S1 ... Phase detection signal, S2 ... Delay signal (delayed arrival signal).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location // H03L 7/00 B

Claims (9)

[Claims] 1. A first delay circuit for delaying one signal to be a synchronization target; a phase detection circuit for detecting a phase difference between the one signal and the other signal synchronized with the one signal; A second delay circuit that delays the other signal, and a phase of the delay signal from the second delay circuit is corrected based on the phase detection signal from the phase detection circuit, and a rising edge of the phase detection signal or And a phase correction circuit that corrects the duty ratio of the delay signal based on the falling edge. 2. The signal synchronizing circuit according to claim 1, wherein the first delay circuit and the second delay circuit are non-inverters. 3. The signal synchronization circuit according to claim 1, wherein each of the first delay circuit and the second delay circuit comprises an exclusive OR circuit in which a low potential is supplied to one input. 4. A first adjusting element for adjusting the timing of the delay signal from the first delay circuit and a second adjusting element for adjusting the timing of the output signal from the phase correction circuit are provided. The signal synchronization circuit according to claim 1. 5. The first adjustment element and the second adjustment element each include a capacitor connected to an output of the first delay circuit and an output of the phase correction circuit, respectively. The signal synchronization circuit described. 6. The first adjusting element and the second adjusting element each include a diode connected in the opposite direction to the output of the first delay circuit and the output of the phase correction circuit. The signal synchronization circuit according to claim 4. 7. The signal synchronization circuit according to claim 1, wherein the phase detection circuit and the phase correction circuit are formed of an exclusive OR circuit. 8. An output obtained by taking a first exclusive OR of one signal having an arbitrary duty ratio as a synchronization target and the other signal synchronized with the one signal, and obtaining the first exclusive OR. A signal synchronization method, wherein a second exclusive OR of a signal and a signal obtained by delaying the other signal is used. 9. The signal synchronization method according to claim 8, wherein the duty ratio of the signal as the synchronization target is variable.