JPH1092836A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce base width, realize a necessary current amplification factor, and enable high speed performance and high withstand voltage characteristics. SOLUTION: By wet etching, a thermal oxidation film 104 is partly eliminated, and undercut is performed. Silicon is selectively grown, and a polycrystalline silicon film 105 is brought into contact with a top silicon film 103. After aluminum material is formed by a sputtering method, the respective electrodes 111a, 111b, 111c of emitter base collector are formed by photolithography etching. Thereby base width can be remarkably reduced. By this method, an emitter base junction is formed as a high concentration junction, a base collector junction is formed as a low concentration junction, and a high concentration layer for reducing a collector resistance can be formed at the same time. Thus, profile control is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of manufacturing a lateral structure bipolar transistor.

[0002]

2. Description of the Related Art One of the advantages of a bipolar LSI over a MOS-LSI is its high speed. This is due to the high speed of the element itself and the high current driving capability. However, the disadvantage is that power consumption is large. In this regard, the MOS device has been able to drastically reduce power consumption by adopting a complementary structure from a simple structure such as a conventional N-MOS or P-MOS.

At present, it is known that the power consumption of a bipolar device can be greatly reduced while maintaining its high-speed performance by using a PNP and NPN transistor as its basic circuit. I have. However, it has been difficult to form high-performance PNP and NPN simultaneously in the process. However, in recent years SIMOX (Separation by)
IMplanted Oxygen) or SOI (Silicon On Insulat)
or) The quality of a wafer having a structure has been improved, and it has become possible to realize a high-performance complementary bipolar device.

Hereinafter, an example of a method of manufacturing the complementary bipolar device will be described. FIG. 3 is a manufacturing process diagram of a conventional bipolar transistor having a lateral structure. (1) First, as shown in FIG.
High-resistance silicon wafer substrate 30 of × 10 ¹⁵ / cm ³ or less
First, oxygen ion implantation is performed at ¹⁸⁰ keV and 0.4 × 10 ¹⁸ / cm ² .

Thereafter, an SOI structure is realized by heat treatment at 1300 ° C. for about 6 hours. Here, 302 is an oxide film layer, 303 is a top silicon film, and its film thickness is about 0.3 μm. (2) Then, as shown in FIG. 3B, the region where the NPN transistor is formed has a phosphorus concentration of 1 × 10 ¹⁶ / cm.
Ion implantation is performed to about ³ and heat treatment is performed.
Next, a CVD oxide film 304 is formed on the entire surface at about 5000 °
Open the windows.

(3) Next, as shown in FIG. 3C, boron ion implantation is performed at about 30 keV to form a base region 305. (4) Next, as shown in FIG. 3D, the oxide film 304 on the surface of the wafer is partially etched to open collector and emitter electrode formation portions. (5) Next, as shown in FIG. 3 (e), arsenic ion implantation and heat treatment are performed on the emitter electrode using a known photolithography technique, and the carrier concentration in the emitter is set to 1 × 10 ²⁰ / c.
to about m ^3. Next, after polycrystalline silicon is selectively formed only on the exposed silicon portion, boron and arsenic are ion-implanted into the N-type electrode and the P-type electrode, respectively, and further heat-treated to reduce the resistance of the polycrystalline silicon. . Here, 306
a is an emitter electrode, 306b is a base electrode, and 306c is a collector electrode.

FIG. 3 (e) 'shows a schematic sectional view of the NPN transistor formed by this step, and FIG. 3 (e) "shows a schematic plan view of the NPN transistor. Here, E is an emitter, B is a base, and C is a collector, and by the above steps, a lateral NPN transistor can be formed on an SOI wafer.

[0008]

As described above, S
By using a substrate having an OI structure, it has become possible to form a lateral bipolar transistor having a new structure. However, the above-mentioned lateral bipolar transistor has a wider base width than conventional vertical transistors, and has characteristics such as cut-off frequency and the like, which are insufficient in speed performance.

The present invention eliminates the above-mentioned problems, and provides a semiconductor device which can greatly reduce the base width, has a required current amplification factor, has both high-speed performance and breakdown voltage characteristics, and a method of manufacturing the same. The purpose is to:

[0010]

According to the present invention, there is provided a semiconductor device comprising: (1) a semiconductor device having a window formed on a silicon oxide film on a surface of a semiconductor wafer having an SOI structure; A cut thermal oxide film, a polycrystalline silicon film, an island region in which a nitride film is stacked, a sidewall formed on a side of a window of the island region, and the island region. A second conductivity type base region formed in the top silicon film of the SOI structure using the sidewalls as a mask, and connected to the polycrystalline silicon film and formed on one side of the base region. A first conductivity type emitter region, a first conductivity type low concentration impurity region joined to the other side of the base region, and the first conductivity type emitter region. A first junction to a side of the low-concentration impurity region
A conductive type collector region is provided.

(2) A method for manufacturing a semiconductor device, comprising:
In a semiconductor wafer having an OI structure, a silicon oxide film on the surface is of a first conductivity type, and a semiconductor thin film containing a first insulating film and an impurity of a second conductivity type at a high concentration is formed on the entire surface. Forming a film in an island shape and leaving it;
Forming the window reaching the surface of the wafer by removing the insulating film, the polycrystalline silicon film and the first insulating film, and forming a third insulating film on the entire surface. Forming a side wall by performing anisotropic etching to form a sidewall, diffusing impurities through an opening window, and setting the portion to a second conductivity type;
Opening a window serving as an emitter or a collector in the insulating film / polycrystalline silicon film / first insulating film, etching a part of the exposed first insulating film to undercut, A semiconductor film is selectively grown only on the exposed silicon portion, and a step of forming a first conductivity type region in the emitter and collector regions by diffusion of impurities from the semiconductor film. .

Therefore, the base width can be greatly reduced, and the same performance as that of the conventional vertical structure can be obtained. In addition, various transistor parasitic capacitances can be reduced to the utmost. Furthermore, the emitter-base junction can be formed as a high-concentration junction, the base-collector junction can be a low-concentration junction, and a high-concentration layer that lowers the collector resistance can be formed at the same time.

As a result, it is possible to realize an ideal transistor having a required current amplification factor and having both high-speed performance and withstand voltage characteristics. (3) In a semiconductor device, an island having a window formed on a silicon oxide film on a surface of a semiconductor wafer having an SOI structure, an undercut thermal oxide film, a polycrystalline silicon film, and a nitride film are laminated. Region, a sidewall formed on a side of a window of the island region, and a second conductivity type formed in the top silicon film of the SOI structure using the island region and the sidewall as a mask. A base region, a first conductivity type emitter region connected to the polycrystalline silicon film and formed on one side of the base region, and a second side of the base region. A first conductive type low-concentration impurity region, a first conductive type low-concentration impurity region connected to the polycrystalline silicon film, and a first conductive-type low-concentration impurity region bonded to a side portion of the first conductive type low-concentration impurity region;
An NPN transistor having a conductive type collector region, a window formed on a silicon oxide film on a surface of a semiconductor wafer having an SOI structure, an undercut thermal oxide film, a polycrystalline silicon film, and a nitride film Are formed in the top silicon film of the SOI structure using the island-shaped region and the side wall as a mask. A first conductivity type base region, a second conductivity type emitter region connected to the polycrystalline silicon film and formed on one side of the base region, and a second conductivity type emitter region. A second joined to one side
A PNP transistor having a conductive type low-concentration impurity region and a second conductive type collector region connected to the polycrystalline silicon film and joined to a side of the second conductive type low-concentration impurity region; Is provided.

(4) A method of manufacturing a semiconductor device, comprising:
In a semiconductor wafer having an OI structure, after dividing the outermost semiconductor layer into a plurality of island regions, an N-type impurity is diffused in an NPN transistor formation region, and a P-type impurity is diffused in a PNP transistor formation region. A step of diffusing, forming a first insulating film on the surface, forming a first semiconductor thin film, dividing the region into regions, and diffusing a P-type impurity into the semiconductor thin film in the NPN portion. Forming a second insulating film on the entire surface after diffusing an N-type impurity into the semiconductor thin film in the PNP portion; and extracting a base electrode reaching the outermost surface semiconductor in a part of the island region. Opening a window to be a part, further forming a third insulating film on the entire surface, and then etching the third insulating film by anisotropic etching to leave only the opening in a sidewall shape;
From the window, a step of diffusing a P-type impurity in the NPN transistor forming portion and diffusing an N-type impurity in the PNP transistor forming portion, and opening a window reaching the outermost semiconductor in a portion serving as a collector and an emitter electrode; A step of precisely etching the first insulating film from the exposed portion to undercut; and selectively growing a second semiconductor thin film only on the silicon exposed portion, embedding the undercut portion, and performing self-alignment. A contact between the outermost surface semiconductor and the first semiconductor thin film is realized. At this time, in the NPN transistor portion, the emitter region and the collector high concentration region are formed by impurity diffusion from the first semiconductor thin film containing N-type impurities. Formed in the PNP transistor portion, the impurity is diffused from the first semiconductor thin film containing a P-type impurity by the impurity diffusion. A step region and the high concentration collector region is formed at the same time, the emitter, base, is obtained by so applying and forming a metal electrode to the collector units.

Therefore, the basic effect is the above (1)
However, NPN and PNP can be formed completely complementarily, and an IC with low power consumption can be manufactured. In addition, various self-alignment techniques and impurity diffusion techniques are frequently used, so that the process is extremely simple.

In this process, the NPN and the PNP are formed completely evenly.
The adjustment can be easily performed by adjusting the mask dimensions and the like.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view of a manufacturing process of a bipolar transistor showing a first embodiment of the present invention (part 1), and FIG. 2 is a sectional view of a manufacturing process of a bipolar transistor showing a first embodiment of the present invention (part 2).

(1) First, as shown in FIG. 1A, a high-resistance silicon wafer substrate 101 having an impurity concentration of 1 × 10 ¹⁵ / cm ³ or less is applied with 180 keV and 0.4 × 10 ¹⁸ / c.
Perform ion implantation of oxygen at m ² . Then, at 1300 ° C,
The SOI structure is realized by the heat treatment for about 6 hours.
Here, 102 is an oxide film and 103 is a top silicon film, which is about 0.3 μm.

Thereafter, the N of the top silicon film 103 is
The region where the PN transistor is formed has a phosphorus concentration of 1 ×
Ion implantation is performed at about 10 ¹⁶ / cm ³ and heat treatment is performed. Then, a thermal oxide film 10 is formed on the entire surface by thermal oxidation.
4 is formed, a polycrystalline silicon film 105 is
The polycrystalline silicon film 105 is doped with phosphorus at a high concentration.

(2) Further, as shown in FIG. 1B, a nitride film 106 is formed by a CVD method. Next, a window of 0.3 μm is opened by a known photolithographic etching technique. (3) Next, as shown in FIG.
After a nitride film is formed to a thickness of about 0.2 μm, the nitride film is etched back by anisotropic dry etching to form a sidewall 107.
a and 107b are formed.

(4) Next, as shown in FIG. 1D, boron ions are implanted at about 30 keV to form a base region 108. (5) Next, as shown in FIG. 1E, the nitride film 106, the polycrystalline silicon film 105, and the thermal oxide film 10
4 is partially etched to open collector and emitter electrode formation portions.

(6) Next, as shown in FIG. 2A, the thermal oxide film 104 is partially removed by wet etching, and an undercut is performed. (7) Next, as shown in FIG. 2B, the silicon films 109a and 109b are selectively grown, and a contact is made between the polycrystalline silicon film 105 and the top silicon film 103.
At this time, the wafer is heated at about 700 ° C. to SiH ₂ Cl ₂ + HC
By treating l in a hydrogen base, the silicon film 109b is grown only on the exposed surface of the top silicon film 103, and no silicon film is grown on the insulating film. Thereafter, by performing a heat treatment, the polycrystalline silicon film 10 is formed.
5 is diffused to form an intrinsic emitter region 110a and a low-resistance collector region 110b.

(8) Thereafter, as shown in FIG.
After the aluminum material is generated by the sputtering method, the respective electrodes of the emitter electrode 111a, the base electrode 111b, and the collector electrode 111c are formed by a known photolithographic etching technique. As described above, according to the first embodiment, it is possible to greatly reduce the base width as compared with the conventional method. That is, it was impossible to reduce the width to less than the base width limited by the photolithography technique by the conventional method.
A base width of m or less can be sufficiently realized, and a performance equivalent to that of a conventional vertical structure can be obtained. In addition, various transistor parasitic capacitances can be reduced to the utmost.

Further, according to this method, the emitter-base junction can be formed as a high-concentration junction, the base-collector junction can be a low-concentration junction, and a high-concentration layer that lowers the collector resistance can be formed simultaneously. That is, profile control can be performed. This makes it possible to realize an ideal transistor having a required current amplification factor and having both high-speed performance and withstand voltage characteristics.

Next, a second embodiment of the present invention will be described. FIG. 4 is a sectional view of a bipolar transistor showing a second embodiment of the present invention (part 1), and FIG. 5 is a sectional view of a bipolar transistor showing a second embodiment of the present invention (part 2). The manufacturing method of this embodiment is a method in which the first embodiment is expanded to the simultaneous formation of NPN and PNP. The manufacturing method will be described below.

(1) First, as shown in FIG. 4A, the substrate wafer 201 is a high-resistance substrate having an impurity concentration of 5 × 10 ¹⁵ / cm ³ or less. 180 keV, 0.
Oxygen ion implantation is performed at 4 × 10 ¹⁸ / cm ² . Thereafter, an SOI structure is realized by heat treatment at 1300 ° C. for about 6 hours. Here, 202 is an oxide film, 203 is a top silicon film, and its film thickness is about 0.3 μm.

(2) Next, as shown in FIG. 4B, the top silicon film 203 is divided into a plurality of regions by a known photolithographic etching technique. In this figure, two parts are typically displayed. The first region is a region where the NPN transistor 203a is formed, and the second region is a region where the PNP transistor 203b is formed. An N-type region containing approximately 1 × 10 ¹⁶ / cm ³ of phosphorus is formed in the formation region of the NPN transistor 203a by a known photolithography technique and ion implantation + heat treatment.
In the formation region of boron, 1 × 10 ¹⁶
/ Cm ³ is formed.

Next, the surface of the exposed silicon portion is set to 1000 °
After thermal oxidation to a degree to form a thermal oxide film 204,
Non-doped CVD of polycrystalline silicon film of about 2,000Å
Generated by Further, the polycrystalline silicon film is divided for each transistor region by a known photolithographic etching technique, and polycrystalline silicon films 205a and 205b are formed.

(3) Thereafter, as shown in FIG.
After thermally oxidizing the surface by about 100 °, boron is applied to the polycrystalline silicon film 205a in the region where the NPN transistor 203a is formed, phosphorus is applied to the polycrystalline silicon film 205b in the region where the PNP transistor 203b is formed, and 5 × 10 ^{16 at} 20 keV. / Cm ² . Further, a CVD nitride film 206 is formed on the entire surface at about 1500 °.

(4) Next, as shown in FIG. 4 (d), a 0.3 μm window is opened in the upper portion of a portion serving as a base region of each transistor by a known photolithographic etching technique. (5) Next, as shown in FIG. 4E, a CVD nitride film is formed on the entire surface to a thickness of about 0.2 μm, and then etched back by anisotropic dry etching to form a sidewall 207.
a, 207b, 207c and 207d are formed. next,
The NPN transistor 203 is formed by a known photolithography technique.
Boron is ion-implanted into the formation region of a at 60 keV,
Base region 20 having a peak concentration of about 2 × 10 ¹⁸ / cm ³
8a is formed. Similarly, in the region where the PNP transistor 203b is formed, arsenic is ion-implanted into the base region 208 having a peak concentration of about 2 × 10 ¹⁸ / cm ³ .
b is formed.

(6) Next, as shown in FIG. 5A, an emitter-base electrode forming portion of each transistor is opened by about 1 μm by a known photolithographic etching technique. At this time, the distance from the base region is set to 0.5 μm on the emitter side and 1 μm on the collector side. (7) Next, as shown in FIG. 5B, the thermal oxide film 204 is etched by about 0.4 μm with hydrofluoric nitric acid to perform undercut.

(8) Next, as shown in FIG. 5C, silicon is selectively grown and the polycrystalline silicon film 205 is formed.
a, 205b and silicon are contacted. That is,
Silicon films 209a to 209f are formed. At this time,
By treating the wafer with SiH ₂ Cl ₂ + HCl in a hydrogen base at about 700 ° C., a silicon film is grown only on the exposed surface of silicon, and no silicon film is grown on the insulating film. Thereafter, by performing a heat treatment, the polycrystalline silicon film 2 is formed in the NPN transistor forming portion.
Phosphorus diffuses from the intrinsic emitter region 210a
And a low-resistance collector region 210b.

At the same time, in the PNP transistor formation region, boron diffuses from the polycrystalline silicon film 205b, thereby simultaneously forming the intrinsic emitter region 210c and the low-resistance collector region 210d. (9) Finally, as shown in FIG. 5D, aluminum is sputtered on the entire surface, and the aluminum is sputtered by a known photolithographic etching technique to form an emitter electrode 211a, a base electrode 211b, and a collector electrode 211c in an NPN transistor.
And the emitter electrode 2 of the PNP transistor.
11d, a base electrode 211e, and a collector electrode 211f are respectively formed.

As described above, according to this embodiment, the basic effects are the same as those of the first embodiment. However, in the second embodiment, it is possible to form NPN and PNP completely complementarily. Thus, an IC with low power consumption can be manufactured. In addition, various self-alignment techniques and impurity diffusion techniques are frequently used, so that the process is extremely simple. In this process, the NPN and the PNP are formed completely equally, and the characteristics of each transistor can be easily adjusted by adjusting the mask dimensions and the like.

It should be noted that the present invention is not limited to the above-described embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0036]

As described above, according to the present invention, the following effects can be obtained. (1) According to the first or second aspect of the present invention, the base width can be significantly reduced, and the same performance as that of the conventional vertical structure can be obtained. In addition, various transistor parasitic capacitances can be reduced to the utmost.

Further, the emitter-base junction can be formed as a high-concentration junction, the base-collector junction can be a low-concentration junction, and a high-concentration layer that lowers the collector resistance can be formed at the same time. This makes it possible to realize an ideal transistor having a required current amplification factor and having both high-speed performance and withstand voltage characteristics.

(2) According to the third or fourth aspect of the invention, the basic effects are the same as those of the above (1), but it is possible to form NPN and PNP completely complementarily. Thus, an IC with low power consumption can be manufactured. In addition, various self-alignment techniques and impurity diffusion techniques are frequently used, so that the process is extremely simple.

In this process, the NPN and the PNP are formed completely equally, and the characteristics of each transistor are adjusted by:
The adjustment can be easily performed by adjusting the mask dimensions and the like.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (No. 1) of a manufacturing process of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of a bipolar transistor showing a first embodiment of the present invention in a manufacturing process.

FIG. 3 is a manufacturing process diagram of a conventional bipolar transistor having a lateral structure.

FIG. 4 is a sectional view (1) of a bipolar transistor showing a manufacturing process according to a second embodiment of the present invention.

FIG. 5 is a sectional view (part 2) of a bipolar transistor showing a second embodiment of the present invention in the manufacturing process.

[Explanation of symbols]

101 High-resistance silicon wafer substrate 102, 202 Oxide film 103, 203 Top silicon film 104, 204 Thermal oxide film 105, 205, 205a, 205b Polycrystalline silicon film 106 Nitride film 107a, 107b, 207a-207d Side walls 108, 208a, 208b Base region 109a, 109b, 209a to 209f Silicon film 110a, 210a, 210c Intrinsic emitter region 110b, 210b, 210d Low resistance collector region 111a to 111c, 211a to 211f Electrode 201 Substrate wafer 203a NPN transistor 203b PNP transistor 206 CVD Nitride film

Claims (4)

[Claims] (A) an undercut thermal oxide film having a window formed on a silicon oxide film on a surface of a semiconductor wafer having an SOI structure; a polycrystalline silicon film;
An island-shaped region in which a nitride film is stacked; (b) a sidewall formed on a side of a window of the island-shaped region; and (c) the SO using the island-shaped region and the sidewall as a mask.
A second conductivity type base region formed in the top silicon film having the I structure; and (d) a second conductivity type base region connected to the polycrystalline silicon film and formed on one side of the base region. An emitter region of one conductivity type; (e) a low-concentration impurity region of the first conductivity type joined to the other side of the base region; and (f) connected to the polycrystalline silicon film. A semiconductor device comprising: a first conductivity type collector region joined to a side of a first conductivity type low concentration impurity region. (A) In a semiconductor wafer having an SOI structure, a silicon oxide film on the surface is of a first conductivity type, and further, a first insulating film and a second conductivity type impurity are included in the entire surface at a high concentration. Forming a thin film and leaving a polycrystalline silicon film in an island shape; and (b) forming a second insulating film on the entire surface, and then forming the insulating film, the polycrystalline silicon film, and the first insulating film. Forming a window reaching the wafer surface, and (c) forming a third insulating film on the entire surface and etching the third insulating film by anisotropic etching to form a sidewall. Performing an impurity diffusion through an opening window to make the portion a second conductivity type; and (d) a window serving as an emitter or collector in the second insulating film / polycrystalline silicon film / first insulating film. And (e) removing the exposed first insulating film. (C) etching a portion to undercut; (f) selectively growing a semiconductor film only on the silicon exposed portion on the entire surface, and forming an emitter and a collector region of the first conductive layer by diffusion of impurities from the semiconductor film. Forming a mold region. 3. A thermal oxide film having a window formed on a silicon oxide film on a surface of a semiconductor wafer having an SOI structure and undercut, a polycrystalline silicon film,
An island-shaped region in which a nitride film is stacked; (b) a sidewall formed on a side of a window of the island-shaped region; and (c) the SO using the island-shaped region and the sidewall as a mask.
A second conductivity type base region formed in the top silicon film having the I structure; and (d) a second conductivity type base region connected to the polycrystalline silicon film and formed on one side of the base region. An emitter region of one conductivity type; (e) a low-concentration impurity region of the first conductivity type joined to the other side of the base region; and (f) connected to the polycrystalline silicon film. A first conductivity type collector region joined to a side of the first conductivity type low concentration impurity region.
An island in which a PN transistor and (g) a window formed on a silicon oxide film on a surface of a semiconductor wafer having an SOI structure, and an undercut thermal oxide film, a polycrystalline silicon film, and a nitride film are laminated; (H) a sidewall formed on a side of a window of the island-shaped region;
(I) a first layer formed in the top silicon film of the SOI structure using the island-shaped region and the sidewall as a mask;
A conductive type base region; (j) a second conductive type emitter region connected to the polycrystalline silicon film and formed on one side of the base region; and (k)
A second conductivity type low-concentration impurity region joined to the other side of the base region; and (1) a side of the second conductivity type low-concentration impurity region connected to the polycrystalline silicon film. And a PNP transistor having a collector region of the second conductivity type joined to the portion. (A) In a semiconductor wafer having an SOI structure, after a semiconductor layer on the outermost surface is divided into a plurality of island regions,
A step of diffusing an N-type impurity in a formation region of the NPN transistor and a diffusion of a P-type impurity in a formation region of the PNP transistor; (b) forming a first insulating film on the surface; After a semiconductor thin film is formed, the semiconductor thin film is divided into the above regions, a P-type impurity is diffused in the semiconductor thin film in the NPN portion, and N-type impurity is diffused in the semiconductor thin film in the PNP portion.
Forming a second insulating film over the entire surface after diffusing the impurity of the mold, and (c) opening a window serving as a base electrode extraction portion reaching the outermost surface semiconductor in a part of the island region; Further, after a third insulating film is formed on the entire surface, the third insulating film is etched by anisotropic etching so that the third insulating film is left only in the opening in a sidewall shape.
The NPN transistor forming portion diffuses P-type impurities,
A step of diffusing an N-type impurity into the NP transistor forming portion; and (e) opening a window reaching the outermost surface semiconductor in a portion to be a collector and an emitter electrode, and then accurately etching the first insulating film from the exposed portion. Performing an undercut; and (f) selectively growing a second semiconductor thin film only on the exposed silicon portion, embedding the undercut portion, and forming a self-aligned top surface semiconductor and a first semiconductor thin film. At this time, in the NPN transistor portion, an emitter region and a collector high-concentration region are formed by impurity diffusion from the first semiconductor thin film containing an N-type impurity. Further, in the PNP transistor portion, A step of simultaneously forming an emitter region and a high-concentration collector region by impurity diffusion from a first semiconductor thin film containing a P-type impurity; (G) the emitter, base, method of manufacturing a semiconductor device characterized by performing the step of forming the metal electrode to the collector units.