JPH1091568A5 - - Google Patents

Info

Publication number
JPH1091568A5
JPH1091568A5 JP1997090124A JP9012497A JPH1091568A5 JP H1091568 A5 JPH1091568 A5 JP H1091568A5 JP 1997090124 A JP1997090124 A JP 1997090124A JP 9012497 A JP9012497 A JP 9012497A JP H1091568 A5 JPH1091568 A5 JP H1091568A5
Authority
JP
Japan
Prior art keywords
external
bus
signal
data processor
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997090124A
Other languages
English (en)
Japanese (ja)
Other versions
JP3817327B2 (ja
JPH1091568A (ja
Filing date
Publication date
Priority claimed from US08/623,482 external-priority patent/US5740382A/en
Application filed filed Critical
Publication of JPH1091568A publication Critical patent/JPH1091568A/ja
Publication of JPH1091568A5 publication Critical patent/JPH1091568A5/ja
Application granted granted Critical
Publication of JP3817327B2 publication Critical patent/JP3817327B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP09012497A 1996-03-28 1997-03-24 データ処理システムにおいてチップ選択可能な装置をアクセスする方法および装置 Expired - Fee Related JP3817327B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/623,482 US5740382A (en) 1996-03-28 1996-03-28 Method and apparatus for accessing a chip-selectable device in a data processing system
US08/623,482 1996-03-28

Publications (3)

Publication Number Publication Date
JPH1091568A JPH1091568A (ja) 1998-04-10
JPH1091568A5 true JPH1091568A5 (enExample) 2005-02-24
JP3817327B2 JP3817327B2 (ja) 2006-09-06

Family

ID=24498247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09012497A Expired - Fee Related JP3817327B2 (ja) 1996-03-28 1997-03-24 データ処理システムにおいてチップ選択可能な装置をアクセスする方法および装置

Country Status (5)

Country Link
US (1) US5740382A (enExample)
EP (1) EP0798644A3 (enExample)
JP (1) JP3817327B2 (enExample)
KR (1) KR100436098B1 (enExample)
CN (1) CN1118028C (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854944A (en) * 1996-05-09 1998-12-29 Motorola, Inc. Method and apparatus for determining wait states on a per cycle basis in a data processing system
GB2362482A (en) 2000-05-15 2001-11-21 Ridgeway Systems & Software Lt Direct slave addressing to indirect slave addressing
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
JP2005038230A (ja) * 2003-07-16 2005-02-10 Oki Electric Ind Co Ltd システムｌｓｉ
KR100746646B1 (ko) * 2006-07-11 2007-08-06 삼성전자주식회사 디스플레이 구동 회로 및 이를 갖는 액정 표시 장치
CN115529275B (zh) * 2022-11-28 2023-04-07 中国人民解放军国防科技大学 一种报文处理系统及方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4615017A (en) * 1983-09-19 1986-09-30 International Business Machines Corporation Memory controller with synchronous or asynchronous interface
US4617624A (en) * 1984-04-16 1986-10-14 Goodman James B Multiple configuration memory circuit
US4745407A (en) * 1985-10-30 1988-05-17 Sun Microsystems, Inc. Memory organization apparatus and method
US5151986A (en) * 1987-08-27 1992-09-29 Motorola, Inc. Microcomputer with on-board chip selects and programmable bus stretching
US5448744A (en) * 1989-11-06 1995-09-05 Motorola, Inc. Integrated circuit microprocessor with programmable chip select logic
JP2762138B2 (ja) * 1989-11-06 1998-06-04 三菱電機株式会社 メモリコントロールユニット
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
US5418924A (en) * 1992-08-31 1995-05-23 Hewlett-Packard Company Memory controller with programmable timing
US5511182A (en) * 1994-08-31 1996-04-23 Motorola, Inc. Programmable pin configuration logic circuit for providing a chip select signal and related method

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