JPH1083176A - Bold processing device, printer and bold processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor, printer and image processing method which make it possible to variably set the processing range of the bold processing in a simple circuit configulation and to realize the setting of character presentation in accordance with character size. SOLUTION: The processing range, in which the bold processing corresponding to character size is executed, is previously set and the bold processing is executed by the bit unit in a bold processing means 12 to picture data successively outputted by the bit unit in accordance with this processing range. The picture data subjected to this bold processing and to be outputted by the bit unit are successively stored in a specified address of a memory means 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bold processing apparatus and a bold processing method for performing bold processing on image data. Furthermore, the present invention relates to a printing apparatus that performs printing using an apparatus that performs such bold processing.

[0002]

2. Description of the Related Art Conventionally, in a printer which expresses characters and image data in a dot pattern and performs printing, when performing bold (BOLD) processing, a pattern in which image data is shifted by one dot in a dot unit or a pattern in which a plurality of dots are shifted. For example, bold processing is realized by adding image data shifted in dot units to the original image data.

FIG. 4 shows an example of the configuration of a circuit for performing bold processing for two dots on image data by editing in units of one word as an example.

In FIG. 4, reference numeral 20 denotes a source address SADR of a transfer source, reference numeral 21 denotes each bit (Sb0 to Sb15) in one word of image source data in the source address SADR, and Sb0 denotes the bit. Indicates the first bit. 22 is the destination of the transfer destination
An address DADR is shown, and 23 is each bit (Db0 to Db15) in one word of image destination data at the destination address DADR.
And Db0 indicates the first bit. Image data 2
Between the 0 and the image data 22, a 3-input OR gate 24
The bolding process is performed by outputting the data of each bit by 2 dots (2 bits) redundantly by the AND gate 25 with two inputs. In this case, for example, the Sb0 bit is output to the Db0 bit via the OR gate 25 and the OR gates 24 and 24 '.
Are also output to the Db1 bit and Db2 bit.
26a and 26b are D flip-flop circuits for storing the bold processing value for the next word. When the next word data is read, a process of adding the data stored in the D flip-flop circuits 26a and 26b to the leading bit data is performed. Thus, in editing in units of one word, bold processing for two dots can be applied to image data.

[0005]

However, in the above-described conventional example, since the output control of data is performed using the OR gates 24 and 25, the bold processing width is fixed, and the editing of the bold processing is variable. Was not. For this reason, when preparing two or three types of setting frames for the bold processing width, it is necessary to prepare two or three types of circuits correspondingly, and the number of gates is required accordingly, making the circuit complicated and large. Cost increases.

When the bold processing width is fixed as described above, the bold processing width is the same both when the character size in the image data is large and when the character size is small. Comes out.

An object of the present invention is to provide a bold processing apparatus and a bold processing apparatus capable of variably setting a processing width of bold processing with a simple circuit configuration and realizing setting of a character expression suitable for a character size. A method and a printing device are provided.

[0008]

According to the present invention, there is provided processing width setting means for setting a processing width for performing bold processing on data in the form of a dot pattern in accordance with a character size, and based on the set processing width of the bold processing. Bold processing means for performing bold processing on the data in bit units;
A bold processing device is constituted by addressing means for designating a bit address of the bold-processed data in bit units, and storage means for storing the bold-processed data bit by bit in accordance with the specified bit address. can do.

In the above bold processing apparatus, the following components may be added. The bold processing means includes a calculating means for setting the number of times of bold processing, and a determining means for determining whether or not the data is to be subjected to bold processing based on the set number of calculations and outputting data in bit units Configuration. The calculating means includes a counter circuit for counting the number of calculations for bold processing. The storage means has a configuration including a flip-flop circuit. Further, the data may be composed of data in units of bytes, data in units of words, or data in units of long words.

Further, according to the present invention, a printing apparatus can be constituted by the above-described bold processing apparatus and means for printing the bold-processed data output from the bold processing apparatus.

Further, the present invention sets a processing width for performing bold processing on data in the form of a dot pattern in accordance with a character size, and based on the set processing width of bold processing, sets a processing width for the data. Performing bold processing on a bit-by-bit basis and storing the bold-processed data one bit at a time in a state where the data generated by the bold processing on a bit basis and the addressing of the data are synchronized. Thus, a bold processing method can be provided.

In the above bold processing method, the number of operations of the bold processing is set, and based on the set number of operations, it is determined whether or not the data is to be subjected to the bold processing, and the data is output in bit units. Is also good. Further, the arithmetic circuit for the bold processing may be counted using a counter circuit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of the present invention will be described with reference to FIGS. Hereinafter, the present invention will be described for a case where image data is read in a word unit for a certain image area and bold processing is performed.

FIG. 1 shows the configuration of a bold processing unit in the apparatus of the present invention. The bold processing unit includes a bold operation unit 12 that performs bold processing on the input word-unit image data 4, a D flip-flop circuit group 17 that stores a bold-processed bit unit signal 9 (COUT), and And an address setting unit 13 for designating the bit address of the bold-processed signal 9 in bit units.

First, the bold operation unit 12 is shown in FIG.
It can be configured as follows.

That is, as shown in FIG. 2, the bold operation unit 12 includes a selection circuit 1 for receiving image data 4 in word units and outputting data in bit units, and a 1-bit data output from the selection circuit 1. 7, an arithmetic circuit 2 for outputting an n-bit signal 8 (CDEC), and an n-bit signal 8 output from the arithmetic circuit 2 for receiving 1
The determination circuit 3 outputs a bit signal 9 (COUT). The arithmetic circuit 2 has a counter circuit 2a for counting the number of bold processes, and a bold process width setting unit 2b for setting the width of the bold process. The initial value of the bold processing width setting unit 2b can be set from outside (user).

FIG. 3 shows the CDEC signal 8 in the arithmetic circuit 2.
Here is an example of a truth table for calculating. Here, signal 10
(CORG) is a value representing the processing width for bold processing in bit units, and is initially set by the user. The CDEC signal 8 is a value for counting the number of processing widths for bold processing. The COUT signal 9 is a signal obtained by changing the value of the CDEC signal 8 to binary (“0” or “1”) of “0” or “0” or more, and indicates the actual image data, that is, the presence or absence of printing. ing.

In FIG. 2, the selection circuit 1 reads the image data 4 for one word, and sends the data 7 to the arithmetic circuit 2 one bit at a time from the leftmost bit of one word in synchronization with the clock signal 5. Here, the read data is in word units, but the present invention is not limited to this, and the bold processing can be similarly performed when the read data is in byte units, long word units, or more.

Next, in the arithmetic circuit 2, the value of the CDEC signal 8 is calculated by the internal counter circuit 2a. When the 1-bit data 7 sent to the arithmetic circuit 2 is “1”, the CORG signal 10 which is a set value of the processing width for bold processing is substituted into the CDEC signal 8 and returned. As a result, the bold processing can be performed even if data “0” continues for the number of times of the bold processing width. Also,
When the 1-bit data 7 sent to the arithmetic circuit 2 is “0” and the value of the COUT signal 9 is “1”,
A value obtained by subtracting 1 from the CDEC signal 8 is shown in the CDEC signal 8 from the truth table of FIG. When the 1-bit data 7 sent to the arithmetic circuit 2 is "0" and the value of the COUT signal 9 is "0", the processing for the number of times of bolding has been completed, so that the CDEC signal Returns 8 = 0.

Next, the decision circuit 3 returns the COUT signal 9 = 1 when the data (CDEC signal 8) sent from the arithmetic circuit 2 is not "0", and returns the COUT signal 9 when the data "0" is sent. It is determined that the signal 9 = 0 is returned. However, in the last word of the row of the image data, the reset signal 6 is sent to the arithmetic circuit 2 at the end of the processing, and the CDE
The C signal 8 is cleared.

In this manner, the COUT signal 9 output as a result of the bold processing in the bold operation unit 12 is output to the D flip-flop circuit 17 in FIG. At this time, the address setting unit 13 is a block for designating a bit address 14 of the COUT signal 9 generated by the counter circuit 2a in FIG. 2, and sets a clock from A0 to A15 in order. Thus, the bit address 14 set by the address setting unit 13 and the CO generated by the counter circuit 2a are output.
In synchronization with the UT signal 9, the data is input and stored bit by bit to the D flip-flop circuit 17, and the bits 18 of Db0 to Db15 are output. When the processing for one word is completed, a reset signal is sent to the D flip-flop circuit 17 to clear the inside of the memory. By performing a series of these operations for all words, it is possible to realize bold processing in which the setting of the processing width can be arbitrarily changed.

Here, the overall flow of the bold processing in which the setting of the processing width described above can be arbitrarily varied will be summarized.
When data is read in the right and left direction in bit units in order from the upper leftmost bit of the image data represented by the dot pattern, if the read 1-bit data is “1”, bold processing is performed from that bit. It is sufficient to return "1" to the number of bits corresponding to the number of set values, and the set value is stored in the counter circuit 2a to count the number of times.
The data "1" of the bit is returned, and the next bit is read.

If the next bit data is "0", the counter circuit 2a decrements 1 from the current count value, and if the count value becomes "0" as a result, data "0" is set. If not, "1" is returned and the next bit data is read.

However, if the count value is "0" and the read data is "0", the data "0" is returned without performing the above processing. By performing these processes up to the last bit of the image data, the processing width of the bold process can be set.

Since the set value of the processing width of the bold processing depends on the counter circuit 2a, the set value of the processing width can be made to correspond to a considerable width by increasing the counter circuit 2a.

[0027]

As described above, according to the present invention,
The processing width of bold processing can be set variably,
Also, if the range of the variable processing width can be counted by the counter circuit configured in the arithmetic circuit,
The processing width of the bold processing can correspond to the maximum value of the counter circuit. Therefore, according to the present invention, it is possible to provide a printer capable of realizing a low-cost character processing device with a simple circuit configuration and realizing a character expression suitable for a character size.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a bold processing unit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed example of a configuration of a bold operation unit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a truth table of CDEC counts by a counter circuit;

FIG. 4 is a block diagram illustrating a schematic configuration of a conventional bold processing unit.

[Explanation of symbols]

 Reference Signs List 1 output means 2 calculation means 2a counter circuit 2b processing width setting means 3 determination means 12 bold processing means 13 address designation means 17 storage means

Claims (14)

[Claims] 1. A processing width setting means for setting a processing width for performing bold processing on data in the form of a dot pattern in accordance with a character size, and a bit width for the data based on the set processing width of the bold processing. Bold processing means for performing bold processing on a bit-by-bit basis; address specifying means for specifying a bit address of data bold-processed on a bit-by-bit basis; and storing one bit of the bold-processed data in accordance with the specified bit address A bold processing device, comprising: 2. The bold processing means sets an operation number of bold processing, and determines whether or not data is to be subjected to bold processing based on the set operation number, and outputs data in bit units. 2. The bold processing apparatus according to claim 1, further comprising a determination unit. 3. The bold processing apparatus according to claim 2, wherein said calculation means includes a counter circuit for counting the number of calculations for bold processing. 4. The bold processing apparatus according to claim 1, wherein said storage means includes a flip-flop circuit. 5. The bold processing apparatus according to claim 1, wherein the data is composed of data in byte units. 6. The bold processing apparatus according to claim 1, wherein the data comprises data in word units. 7. The bold processing apparatus according to claim 1, wherein said data is composed of long word data. 8. A printing apparatus comprising: the bold processing apparatus according to claim 1; and means for printing bold-processed data output from the bold processing apparatus. apparatus. 9. A processing width for performing bold processing on data in the form of a dot pattern is set in accordance with a character size, and bold processing is performed on the data in bit units based on the set processing width of bold processing. Performing the processing, and storing the bold-processed data bit by bit in a storage unit in a state where the data generated by the bold processing in the bit unit and the address designation of the data are synchronized. Bold processing method. 10. The bold processing includes setting the number of operations of the bold processing, determining whether or not the data is to be subjected to the bold processing based on the set number of operations, and outputting data in bit units. The bold processing method according to claim 9, characterized in that: 11. The bold processing method according to claim 10, wherein the calculation circuit for the bold processing is counted using a counter circuit. 12. The bold processing method according to claim 9, wherein said data is composed of data in byte units. 13. The bold processing method according to claim 9, wherein said data comprises data in word units. 14. The bold processing method according to claim 9, wherein said data comprises data in units of long words.