JPH10333879A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor that can supply only necessary bit information from plural bit data stored in one word in a memory to an arithmetic unit at a high speed. SOLUTION: This processor is provided with a memory 2, which inputs an (m) bit physical address 1, and outputs (s) bit data stored in the physical address, data selecting means 3, which inputs an (n) bit control input 5 as the first input, inputs the output of the memory 2 as the second input, and selects and outputs one bit from the (s) bits of the second input according to the first input, and binary arithmetic means 4, which inputs the output of the data selecting means 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus for performing a logical operation only on necessary bits for a plurality of bits stored in a certain address of a memory in digital data processing.

[0002]

2. Description of the Related Art A conventional data processing apparatus will be described with reference to the drawings. FIG. 16 is an explanatory diagram showing the concept of conventional data processing. First, one word data is read from the memory M, and then mask processing based on mask data is performed on bits other than necessary bits. Only the information of the desired bit position is extracted, and the data is output to the logical operation circuit to perform data processing.

[0003]

However, in the above-mentioned conventional device, in order to perform a logical operation on data stored in the memory in units of bits, first, an address of the memory is inputted, and then, The necessary 1-bit data must be extracted by shift processing or mask processing and then output to the logical operation circuit. Further, in order to access a rectangular area, the above operation must be repeated several times. Therefore, there are problems such as an increase in the number of processing cycles and an increase in the operation time.

[0004] The present invention solves the above-mentioned conventional problems and provides a data processing system capable of supplying only necessary bit information from a plurality of bits of data stored in one word in a memory to an arithmetic unit at high speed. It is intended to provide a device.

[0005]

A data processing apparatus according to the present invention includes a memory for receiving an m-bit physical address and outputting s-bit data stored in the physical address, and an n-bit control input. A data selecting means for selecting one bit from s bits of the second input according to the first input and outputting the selected data according to the first input; It is provided with a binary operation means for performing the above.

According to the present invention, only necessary bit information can be supplied to an arithmetic unit at high speed from a plurality of bits of data stored in one word in a memory.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same reference numerals are used for parts common to the embodiments.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a data processing apparatus according to a first embodiment of the present invention. In FIG. 1, 1 is an m-bit physical address input, 2 is a memory, and 3 is a memory. The data selection means 4 is a binary operation means for accessing an arbitrary rectangular area at a high speed when the bit arrangement on the memory is regarded as two-dimensional, and the reference numeral 5 is an n-bit control input. When the m-bit physical address input 1 is input, the memory 2 outputs s-bit data stored at the designated address. The n-bit control input 5 and the s-bit data output from the memory 2 are input to the data selection means 3. The data selection means 3 processes the s-bit memory output data into 1-bit data according to the n-bit control input and outputs the processed data. The 1-bit data is input to the binary operation means 4 and data processing is performed.

FIG. 2 is a block diagram showing an example of a memory.
As an example of access, a case will be described in which it is desired to access data of the fifth bit counting from the address value 3 and lower data in such a memory 2A. Physical address input 1 is 3 bits and n-bit control input 5 is 8 bits. In this case, the physical address input 1 is 011 because it is desired to access the address value 3 in the memory 2A and the data value of the fifth bit counted from the lower data. The control input 5 is 00010000. As a result, the data of address value 3 in the memory 2A and 00010000 are input to the data selection means 3. The data selection means 3 stores the data 00 of the control input 5
The data at the bit position that is 1 in 010000 is stored in memory 2A.
From the output 8-bit data. That is,
In this example, counting from the lower output of the memory 2A, 5
The data of the bit is selected and output to the binary data calculation means 4. By changing the control input, it is possible to extract any bit from the 8-bit output of the memory in the same manner, and the same processing can be performed regardless of the number of output bits of the memory.

As described above, according to the present embodiment, by using the data selection means controlled by the control input, only the necessary bits of an arbitrary address in the memory are reduced to 2 bits.
It can be supplied to the value calculation means at high speed.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of a data processing apparatus according to Embodiment 2 of the present invention. In FIG. 3, 1A denotes a k-bit logical address input, 2 denotes a memory, and 3 denotes a memory. Data selection means 4 are binary operation means for accessing an arbitrary rectangular area at high speed when the bit arrangement on the memory is regarded as two-dimensional, and 6 is control data generation means.
m bits of the k-bit input data 1A are physical addresses of the memory 2. When the physical address is input, the memory 2 outputs s-bit data stored at the specified address. Of the k-bit logical address input 1A, km bits are input to the control data generating means 6.
The control data generating means 6 generates and outputs control data corresponding to the input value. The control data and s-bit output data of the memory 2 are input to the data selecting means 3. The data selecting means 3 extracts 1-bit data from the s-bit data of the memory 2 according to the input control signal and outputs it. This one-bit data is input to the binary operation means 4 and data processing is performed. As an example of the access, as an example of the access, in a memory as shown in FIG. A case where data access is desired will be described.

FIG. 5 is a diagram showing the logical address of the memory shown in FIG. 2. If the logical address of the memory 2A is as shown in FIG. 5, the logical address input is 01.
Since there are 6 1100 bits and the physical address value of the memory is 3, the upper 3 bits of the 6-bit logical address input become the physical address input of the memory 2A. The memory 2A outputs 8-bit data stored in the input physical address value. It is assumed that the remaining lower 3 bits of the 6-bit logical address input are input to the control data generating means. FIG. 4 is a diagram showing an example of input / output values of the control data generating means.

When 100 is input to the control data generating means 6, the data selecting means 3 outputs the 8-bit data stored in the physical address value 3 from the memory 2A and the output of the control data generating means 6. The value 00010000 is entered. The data selection means 3 outputs the output value 0001 of the control data generation means 6
From the 8-bit data output from the memory based on 0000, the fifth bit data counted from the lower order is selected and output to the binary operation means 4. In addition, according to the input of the k-bit logical address, any one bit of the s-bit data of the memory stored in the m-bit physical address value can be similarly extracted.

As described above, according to the present embodiment, control data is generated based on input data, and data stored at an arbitrary address in the memory is extracted by extracting 1-bit data by the data selecting means. It is possible to supply the data to the arithmetic unit at high speed in units.

(Embodiment 3) FIG. 6 is a block diagram showing a configuration of a data processing apparatus according to Embodiment 3 of the present invention. In FIG. 6, 1A denotes a k-bit logical address input, 2 denotes a memory, and 3 denotes a memory. Data selection means 4, binary operation means for accessing an arbitrary rectangular area at a high speed when the bit arrangement on the memory is two-dimensional, 5A an n-bit control input, and 6A a control data generation means. Of the k-bit logical address input 1A, m bits are the physical address of the memory 2. The memory 2 outputs s-bit data stored in the input physical address value. In addition, of the k-bit logical address input 1A, km bits and control input n bits are input to the control data generating means 6A. The control data generating means 6A generates control data using km bits of the logical address input, makes the control data generated using n-bit control input data variable, and sequentially outputs a plurality of control data. . The data selection means 3 has a memory 2
S-bit data output and the output of the control data generating means 6A are input, and 1-bit data is extracted from the s-bit data output of the memory 2 and output using the output of the control data generating means 6A. The data selecting means 3 sequentially outputs the extracted 1-bit data to the binary calculating means 4 in accordance with the control data sequentially output from the control data generating means 6A.

FIG. 7 is a block diagram showing an example of a memory according to the present embodiment. As an example of access, in such a memory 2A, the 5th and 8th bits of the address value 3 counted from the lower data are read. The case where the user wants to access the two data will be described. The logical address input and control input at this time are as shown in FIG. The logical addresses are as shown in FIG. In the present embodiment, the logical address represents the bit of the memory to be accessed first. Therefore, the logical address input is 6 bits of 011100, and the upper 3 bits SA (hereinafter referred to as SA) of the 6-bit logical address input are the physical address inputs of the memory. Lower 3 bits SB (hereinafter referred to as SB)
Is input to the control data generating means 6A. The control input is the total number T of bits accessed by the upper three bits T
BN (hereinafter referred to as TBN), and the remaining three bits indicating the bit interval BI (hereinafter referred to as BI) for accessing 6
This is a bit input.

Now, the TBN of the bit to be accessed is 2,
Since the BI between the bits to be accessed is 3, the input data of 6 bits is 010011. A physical address value 3 is input to the memory, and 8-bit data stored at that address is output to the data selection means 3. Further, the control data generating means 6A first sets SB (100) in the logical address input.
Is generated and output to the data selection means. As a result, the data selecting means 3 first outputs the data value of the fifth bit counted from the lower bit of the input data of the address value 3 of the memory to the binary calculating means 4. Next, the control data generating means 6A adds an offset of BI (011) to SB (100) to obtain SB + BI (111).
00000 is generated and output to the data selection means 3.

Therefore, the data selecting means 3 selects the eighth bit data counted from the lower order among the 8-bit data of the input address value 3 of the memory and outputs it to the binary calculating means 4. The control data generation means 6A then proceeds to SB + 2
The control data is generated as × BI. In the present embodiment, the upper limit of the number of generations is limited to less than TBN. The two data at the fifth and eighth bits counted from the data can be accessed at high speed. FIG. 9 shows a calculation flow according to the present embodiment.
In addition, according to the input of the k-bit logical address, any one bit of the s-bit data of the memory stored in the m-bit physical address value can be similarly extracted.

As described above, according to the present embodiment, control data is generated based on input data, and 1-bit data is extracted by the data selection means, so that data stored at an arbitrary address in the memory can be obtained. It can be supplied to the arithmetic unit in bit units. In addition, by using this configuration and repeating the same work, data stored in an arbitrary rectangular area as in the other example of the memory shown in FIG. Is also possible.

(Embodiment 4) FIG. 11 is a block diagram showing a configuration of a data processing apparatus according to Embodiment 4 of the present invention. In FIG. 11, 1A denotes a k-bit logical address input, 2 denotes a memory, and 3 denotes a memory. Data selection means, 4 are binary operation means for accessing an arbitrary rectangular area at high speed when the bit arrangement on the memory is regarded as two-dimensional, 5B is an n-bit control input, 6B is control data generation means, and 7 is This is a memory physical address generation unit. The m-bit out of the k-bit logical address input 1A and the p-bit out of the n-bit control input 5B are input to the physical address generation means 7 of the memory. Of the two inputs, m bits of the k-bit logical address input indicate the head address to be accessed by the memory, and p-bit input of the control input indicates the total number of addresses to be accessed.
From these, a plurality of physical addresses of the memory 2 are generated and sequentially output.

When a physical address is input, the memory 2 outputs s-bit data stored at the input address. km of logical address input 1A of k bits
Of the bit and n-bit control inputs 5B, np bits are input to the control data generating means 6B. The control data generating means 6B outputs k-m of the k-bit logical address input 1A.
The control data is generated using the bits. Then, using the n-p bit control input of the n-bit control input 5B, which is another input, the generated control data is made variable and sequentially output. The data selection means 3 has the memory
The bit output and the output of the control data generating means 6B are input, and one bit data of the 8-bit output of the memory 2 is extracted and output using the output of the control data generating means 6B. A plurality of data are sequentially output from the control data generating means 6B and the memory 2, and the data selecting means 3 extracts a plurality of 1-bit data in accordance with these inputs,
Output to the binary operation means 4.

FIG. 12 is a block diagram showing an example of a memory according to the present embodiment. As an example of access, a case where a rectangular area is accessed in such a memory 2A will be described. FIG. 13 shows the logical address input and the control input at this time. The logical addresses are as shown in FIG. In the present embodiment, the logical address represents the bit of the memory to be accessed first. Therefore, the logical address input is 6 bits of 010100, SA of the 6-bit logical address input is input to the physical address generating means, and SB is input to the control data generating means 6B.

In this embodiment, the control input is
Since the total number of addresses to be accessed and the total number of bits to be accessed per address are represented, the upper three bits indicate the TBN of bits to be accessed per address, and the remaining three bits are the total number of addresses to be accessed TA
N (hereinafter referred to as TAN). Of these control inputs, the lower 3 bits TAN are input to the physical address generator 7 and the upper 3 bits TBN are the control data generator 6.
B input. Since the TAN of the physical address of the memory to be accessed is 3, and the TBN to access one physical address is 3, the control input is 011011.

First, the physical address generation means 7 outputs SA. As a result, the memory 2 outputs the content stored in the address value 2 to the data selection means 3. The control data generation means 6B first determines whether the control data 00
001000 is generated and output to the data selection means 3. The data selecting means 3 outputs the data of the fourth bit counted from the lower part of the data of the physical address value 3 of the memory inputted by the control data 00001000 to the binary calculating means 4. Next, the control data generation means 6B increments the value of SB (100) by 1 to generate control data 00010000 and outputs it to the data selection means 3. The control data generating means 6B changes the mask data by incrementing the value of SB in this way. In this increment work, the number of increments is TBN (0
Repeat as long as 11) is not exceeded. That is, the control data generating means 6B outputs 00010000, 0010000 as control data.
0, 00001000 are output.

After these three control data are output from the control data generating means 6B, the physical address generating means 7
The value of A is incremented by 1 and the output of the memory is converted into 8-bit data of the physical address value 3, and the control data generation means 6
From the three control data 00010000, 00100000, and 00001000 output in order from B, the contents of one bit at bit positions 3, 4, and 5 are output. The increment of the address value SA in the physical address generation means 7 is repeated while the number of increments is smaller than TAN. Therefore, the address value output from the physical address generation means 7 is 2,
There are three values of 3 and 4. FIG. 14 shows an operation flow according to the present embodiment.

As described above, according to the present embodiment, FIG.
The data stored in a rectangular area such as the memory shown in (1) can be output to the arithmetic unit at high speed in bit units. The same effect can be obtained by using the final value of the physical address of the memory to be accessed instead of the total number TAN of physical addresses to be accessed as a control input. Also, in response to the k-bit logical address input, any one bit of the s-bit data of the memory stored in the m-bit physical address value can be similarly extracted. In addition, it is possible to similarly extract an arbitrary bit from the 8-bit output of the memory according to the logical address.

(Embodiment 5) FIG. 15 is a block diagram showing a configuration of a binary arithmetic unit according to a fifth embodiment of the data processing apparatus of the present invention. In FIG. 15, reference numeral 1 denotes an m-bit physical address input; Is a memory, 3A is a data selection means, 4 is a binary operation means for accessing an arbitrary rectangular area at a high speed when the bit arrangement on the memory is regarded as two-dimensional, and 5 is an n-bit control input. Memory 2 has m-bit physical address input 1
Is input, s stored at the specified address
Outputs bit data. The n-bit control input 5 and the s-bit data output from the memory 2 are input to the data selection means 3, and s-bit data obtained by subjecting the s-bit memory output data to mask processing is output according to the n-bit control input. .

As an example of access, a case will be described in which a memory as shown in FIG. 2 is to be subjected to a masking process on the data of the fifth bit counted from the address value 3 and the lower-order data and to output the data to the binary operation means. Physical address input 1 is 3
Bits and the n-bit control input is 8 bits. Now, address value 3 in the memory, 5 counting from the lower data
Since it is desired to perform a mask process on the data value of the bit, the physical address input 1 is 011. Control input 5 is 0001000
It becomes 0. As a result, the data of the address value 3 of the memory 2 and 00010000 are input to the data selection means 3A.

The data selection means 3A performs an AND operation of the data 00010000 of the control input 5 and the 8-bit data of the output of the memory 2, performs a mask process, and outputs the result. That is, in the present embodiment, 8-bit data is output to the binary operation means 4 after the data values other than the fifth bit counted from the lower order of the output of the memory 2 are set to 0. By changing the control input, it is possible to similarly perform mask processing on an arbitrary bit of the 8-bit output of the memory.
The same processing can be performed regardless of the number of bits output from the memory.

As described above, according to the present embodiment, the data stored at an arbitrary address in the memory is masked and supplied to the binary operation means at high speed by using the data selection means. It becomes possible.

[0031]

As described above, according to the present invention, arbitrary 1-bit data stored in a memory or data stored in an arbitrary rectangular area is supplied to an arithmetic unit at high speed in bit units. An advantageous effect that data processing can be performed is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data processing device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an example of a memory according to each embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a data processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of input / output values of a control data generation unit according to a second embodiment of the data processing device of the present invention.

FIG. 5 is a diagram showing logical addresses of the memory shown in FIG. 2;

FIG. 6 is a block diagram illustrating a configuration of a data processing device according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a memory according to a third embodiment of the data processing device of the present invention.

FIG. 8 is a diagram illustrating an example of a logical address input and a control input according to a third embodiment of the data processing device of the present invention.

FIG. 9 is a diagram showing an operation flow in a third embodiment of the data processing device of the present invention.

FIG. 10 is a diagram showing another example of the memory in the third embodiment of the data processing device of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a data processing device according to a fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a memory according to a fourth embodiment of the data processing device of the present invention.

FIG. 13 is a diagram illustrating an example of a logical address input and a control input according to a fourth embodiment of the data processing device of the present invention.

FIG. 14 is a diagram illustrating a calculation flow in a data processing device according to a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a data processing device according to a fifth embodiment of the present invention.

FIG. 16 is an explanatory diagram showing the concept of conventional data processing.

[Explanation of symbols]

1, 1A, 1A1, 1A2 ... physical address input, 2, 2A
... Memory, 3,3A ... Data selection means, 4: Binary operation means, 5,5A, 5A1,5B, 5B1 ... Control input,
6, 6A, 6B: control data generating means, 7: physical address generating means.

Claims (5)

[Claims] 1. A memory for receiving an m-bit physical address and outputting s-bit data stored in the physical address, a n-bit control input as a first input, and an output of the memory as a second input. Data input means for selecting and outputting one bit from s bits of the second input in accordance with the first input as input, and binary calculating means for inputting an output of the data selection means. Data processing device. 2. Among the k-bit logical address inputs, m
A memory in which bits become a physical address input and output s-bit data stored in the physical address, and control data in which km-m bits of the k-bit logical address input become input and output s-bit control data Generating means, an output of the control data generating means as a first input, an output of the memory as a second input, and selecting and outputting 1-bit data from s bits of the second input according to the first input. A data processing device, comprising: a data selection unit for performing the operation; and a binary operation unit that receives an output of the data selection unit as an input. 3. A memory in which m bits of a k-bit logical address input become a physical address input and output s-bit data stored in the physical address, and k-m of the k-bit logical address input. Bit first
Control data generating means for converting the first input according to the second input to generate a plurality of control data and sequentially outputting the plurality of control data; A data input for selecting the output of the control data generation means as a first input, selecting the output of the memory as a second input, and selecting and outputting 1-bit data from s bits of the second input according to the first input; A data processing device comprising: a binary calculating means that receives an output of the data selecting means as an input. 4. A method according to claim 1, wherein m bits of the k-bit logical address input are the first input, and p bits of the n-bit control signal are the second input, and the first input is converted in accordance with the second input. Address generating means for generating a plurality of physical addresses of a memory and sequentially outputting the physical addresses; a memory for receiving an output of the address generating means as a physical address input and outputting s-bit data stored in the physical address; KM bits of the logical address input are the first
Control data generating means for converting the first input according to the second input, generating a plurality of control data and sequentially outputting the plurality of control data, wherein n-p bits of the n-bit control input become a second input Data which outputs the control data generating means as a first input, outputs the memory as a second input, selects and outputs 1-bit data from s bits of the second input according to the first input, A data processing apparatus comprising: a selection unit; and a binary operation unit that receives an output of the data selection unit as an input. 5. The data selection means according to claim 1, wherein the data input means performs a mask process on the second input according to the first input, and outputs s-bit data. The data processing device according to claim 1.