JPH07120254B2 - Shifter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shifter, and more particularly to a shift count register that controls the shift number of the shifter.

2. Description of the Related Art Conventionally, only one shift count register has been provided for a shifter to control the shifter by giving the shift number to the shifter.

Therefore, in the conventional shifter, when the bit length of the data to be shifted is longer than the bit length of the shifter, the data to be shifted is divided by the bit length of the shifter before shifting. However, at this time, when it is attempted to alternately shift two data having two different shift numbers, it is necessary to repeatedly generate the shift number and set the shift count register for each shift operation.

Therefore, there is a drawback that the control of the shifter becomes complicated and the performance is deteriorated when the circuit for calculating the shift number is also used.

The present invention has been made in view of the above circumstances,
Therefore, an object of the present invention is to provide a novel shifter capable of solving the above-mentioned drawbacks inherent in the conventional technique.

Means for Solving the Problems In order to achieve the above object, the shifter according to the present invention has an n-th (n ≧ 2 integer) first to n-th holding shift number.
Up to the second shift count register and the selected shift number or the value of the first shift count register
To the n-th shift count register, and a selecting means for selecting the number of shifts given to any shift count register or the value of the second to n-th shift count registers and giving it to the first shift count register. It is configured to perform the shift according to the value of the count register.

Example Next, the present invention will be described in detail based on a preferred example thereof.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, it is assumed that one word is an i-bit, and the information processing apparatus that performs reading / writing and operation with the storage device in i-bit units, that is, in 1-word units includes the shifter of the present invention.

Referring to FIG. 1, reference numerals 100, 200, 300 and 400 are data registers, each of which stores one word of data. 500 is a 2i bit input i bit output shifter,
The data in the data registers 100 and 200 is received and shifted, and the result is given to the data register 300 or 400. 700 and 800 are shift count registers, and the selection means 600 causes the shift count register 700 to select and receive the given shift number or the shift number stored in the shift count register 800, and the shift count register 800 receives the given shift number. The number of shifts or the number of shifts stored in the shift count register 700 is selected and received. Further, the shift count register 700 gives the shift number to the shifter 500.

Next, the operation of this embodiment having the above configuration will be described. Here, as the operation of the present embodiment, when two operand data starting from the middle of one word and composed of a plurality of words are taken out and the operation is carried out word by word, the two operands are taken out alternately as operand data of each word. Consider the action of taking out.

Here, the two operands are as shown in FIG.
Operand 1 starts at the j + 1th bit and operand 2 starts at the k + 1th bit.
As shown in 1, the first and second words of the operand 1 are set in the data registers 100 and 200, and the shift count register 700 is selected and set by the selecting means 600 by the given shift number j. Next, as shown in Step 2, the values of the data registers 100 and 200 are shifted left by j by the shifter 500 and set in the data register 300.
The first word of operand 1 is fetched. In parallel with the operation, the first and second words of the operand 2 are set in the data registers 100 and 200, and the shift number k given to the shift count register 700 is stored in the shift count register 800 as the shift number j of the shift count register 700.
Are selected and set by the selection means 600. Then, as in Step 2, as in Step 3, the values in the data registers 100 and 200 are left-shifted by k bits in the shifter 500, set in the data register 400, and the operand 2
The first word of is taken. In parallel with the operation, the second and third words of operand 1 are data registers.
The number of shifts j of the shift count register 800 is set in the shift count register 700, and the number of shifts k of the shift count register 700 is selected in the shift count register 800 by the selecting means 600. Here, the first one word of the operand 1 and the operand 2 is fetched into the data registers 300 and 400, respectively, and sent to the next operation. Then, in step 4, as in step 3, the data register 100,
The value of 200 is shifted to the left by j bits by the shifter 500 and set in the data register 300, the second word of the operand 1 is taken out, and the second and third words of the operand 2 are set in the data registers 100 and 200. The shift count register 700 selects the shift number k of the shift count register 800, and the shift count register 800 selects the shift number j of the shift count register 700 by the selecting means 600 to be set.

After that, operand 1 and operand 2 are shifted by 1 word each, and they are alternately set in the data registers 100 and 200, and the operations of steps 3 and 4 are repeated. However, the same operation can be performed.

EFFECTS OF THE INVENTION As described above, according to the present invention, the control in the case where a plurality of shift count registers are set to the required number of shifts first and the plurality of data are alternately shifted is simple. The effect of becoming.

Further, in the present embodiment, the shift numbers of the two operands are sequentially set in step 1 and step 2, but it is possible to set these two shift numbers before the first shift operation, and the shift number is not generated. When the calculation means for generating the shift number must also be used as the calculation means for other control and calculation because the degree of freedom of timing is increased and the calculation can be performed only once, the shift number is generated. It is clear that is unlikely to cause performance degradation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 and FIG. 3 are diagrams for explaining the operation of this embodiment. 100,200,300,400 …… Data register, 500 …… Shifter,
600 …… Selection means, 700,800 …… Shift count register

Claims (1)

[Claims] 1. A shifter for shifting data consisting of a plurality of bits, wherein n (integers of n ≧ 2) first to nth shift count registers for holding the number of shifts and a given number of shifts or The value of the first shift count register is selected and stored in an arbitrary shift count register of the second to nth shift count registers, and the given shift number or the value of the second to nth shift count register is selected. And a selecting means for storing it in the first shift count register, and shifts according to the value of the first shift count register.