JPH1082839A - Diagnostic system for electronic device using fpga - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a device utilizing high integration and increase its reliability by reading the composition information of a program area, and judging its normality in a field programmable gate array(FPGA). SOLUTION: This FPGA 10 contains a program are a 101 for wring circuit composition information, a read controller 102, a write controller 103, and a composition information diagnosis section 104 judging the normality of the read composition information. A composition information storage ROM 11 storing the written data and a peripheral circuit 12 outputting the composition information read signal 12a to it are connected to the FPGA 10. The read controller 102 receives the read signal 104a and the read clock 104b from the composition information diagnosis section 104, reads the composition information from the program area 101 even during the operation of the EPGA10, and feeds it to the composition information diagnosis section 104 to diagnose its normality. The high integration of the EPGA10 is utilized to miniaturize a device, and reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an FPGA (Fie).
ld Programmable Gate Arra
y), a method of diagnosing an electronic device, particularly FPG
The present invention relates to a method of diagnosing an electronic device using an FPGA that enables failure detection of A to be performed by spontaneous operation of a wiring element.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a diagnostic circuit of an electronic device using a conventional FPGA. In the figure, a FPGA 93 has a data storage PROM 94 for storing data to be written therein, a write control unit 95 for controlling the writing of the data, a comparison for comparing the configuration information read from the cells of the FPGA 93 with the comparison data. Circuits 96 are respectively connected. The comparison data is stored in the comparison data storage PROM 97.
The comparison circuit 98 is connected to a holding unit 99 for holding a pass / fail result as a comparison result.
3 is connected to a configuration information read control unit 100.

In this configuration, the FPGA 93 takes out configuration information data from a data storage PROM 94 to be written by a control signal from a write control unit 95 when power is turned on or the like.
An arbitrary circuit is configured inside the GA 93. After the writing is completed, the operation starts in an arbitrary circuit.

The diagnosis of the FPGA 93 makes the configuration information read start signal 88 given from the configuration information read control unit 100 to the FPGA 93 significant. Read start signal 110
The configuration information data is output to the comparison circuit 96 according to the read clock 89 from the configuration information read control unit 100 in the FPGA 93 in which is made significant.

[0005]

The above-mentioned conventional FPG
In the A-diagnosis method, an external circuit such as the configuration information read control unit 100 is required to start reading of the configuration information data. Peripheral circuits must be added, and there is a problem that the circuits become large and high integration cannot be achieved.

The present invention has been made to solve such a conventional problem, and the diagnosis of the configuration information inside the FPGA is performed by a built-in circuit. It is an object of the present invention to provide a diagnostic method of a device using an FPGA realizing a highly reliable and highly reliable device.

[0007]

SUMMARY OF THE INVENTION The present invention is a diagnostic method for an electronic device using an FPGA, wherein the FPGA comprises:
A program area for writing circuit configuration information of the FPGA, and a configuration information storage ROM for storing configuration information data
A configuration information writing control unit that writes configuration information data of the configuration information storage ROM into the program area; a configuration information read control unit that reads configuration information of the program area; and a normality of the read configuration information. And a configuration information diagnosis unit for determining

According to the present invention, a ROM for storing configuration information,
Since the configuration information read control unit, the configuration information write control unit, and the configuration information diagnosis unit can be built in the FPGA, the FPGA
By utilizing the high integration of the device, the size of the device can be reduced, and a highly reliable electronic device can be realized.

[0009]

FIG. 1 is a configuration diagram of an FPGA according to an embodiment of the present invention. In FIG.
0 is an FPGA (Field Programmable)
Gate Array), a program area 101 for writing circuit configuration information, and a configuration information read control unit 10
2. It has a built-in configuration information write control unit 103 and a configuration information diagnosis unit 104 that determines the normality of the read configuration information. Also, the FPGA 10 has a configuration information storage ROM 11 for storing data to be written therein, and a configuration information read signal 12a for the configuration information storage ROM 11.
Is connected.

In this configuration, the FPGA 10 receives the read signal 12 a from the peripheral circuit 12 as an opportunity to read the configuration information data read signal 10 from the configuration information write control unit 103.
The configuration information data is read from the configuration information storage ROM 11 and written into the program area 101 by the read clock 3a and the read clock 103b. If an error occurs in the writing of the configuration information data, the configuration information writing control unit 10
3 outputs a write error signal 103c. Also,
After completing the writing of the configuration information, the FPGA 10 starts operating according to the circuit configuration based on the written configuration information.

The configuration information reading control unit 102
The configuration information data written in the program area 101 can be read from the program area 101 even during the operation of A10. That is, the configuration information data read signal 10 from the configuration information
4a and the configuration information data read clock 104b are input to the configuration information read control unit 102, whereby the configuration information data written in the program area 101 is read from the program area 101, and this configuration information data is output to the configuration information diagnosis unit 104. I do. The configuration information diagnosis unit 104 diagnoses the normality of the configuration information. At this time, the configuration information read control unit 102 outputs a configuration information data read state signal 102a to the configuration information diagnosis unit 104.

FIG. 2 shows a principle diagram of a program area 101 constituting an internal circuit of the FPGA. In FIG. 3A, the connection / control unit 21 uses a vertical wiring 22 and a horizontal wiring 23 to store / combine the inside of the program area.
4 and connections between the input / output units 25. In the storage / combination unit 24, a storage / combination circuit is selected. Furthermore, vertical wiring 2
The connection between the wiring 2 and the horizontal wiring 23 is performed by controlling the transistors constituting the connection control unit 21 to be on or off. The connection of the storage / combination unit 24 is made by turning on / off a transistor provided therein.

In FIG. 2B, 21 is a conceptual diagram of a connection control unit, 24 is a conceptual diagram of a storage / combination unit, and the storage / combination unit 24 is composed of a logic element 24a and a storage element 24b. You.

Referring to FIG. 3, a wiring selection method and storage /
A method for selecting a combination will be described. In FIG. 2A, a connection control unit 21 includes transistors 31 and 32 connected in series to a vertical wiring 22 and a horizontal wiring 23, a transistor 33 connecting the vertical wiring 22 and the horizontal wiring 23 to each other, On / off control units 34, 35, 36 for controlling on / off of 31, 32, 33 depending on whether or not voltage is applied are provided. The on / off control units 34, 35, and 36 determine whether or not a voltage is applied when data is written, to turn on and off the transistors 31, 32, and 33, and determine the connection of each wiring.

In FIG. 3B, the storage / combination unit 24 includes a storage element 37 composed of a D-FF and a combination circuit 38 composed of a logic element. The storage element 37 has a D terminal, a CE terminal, and a CK terminal. Are transistors 39, 4
0, 41 are connected, and the transistors 39, 40, 4
On / off control units 42, 43, and 44 that perform on / off control depending on whether or not a voltage is applied are connected to one gate, respectively. In the case where writing has failed or a transistor has been destroyed, the circuit configuration differs from that of the written configuration information. Thus, the output signal of the configuration information writing control unit is also different from the written value, but this value is output as it is.

FIG. 4 is a diagram showing the principle of reading the configuration information method. In the figure, 101 is a program area,
3A, and the configuration information binary output is output to the configuration information binary sequence output selector 45. Reference numeral 102 denotes a configuration information read control unit, and the configuration information binary output 46 from the configuration information read control unit 102 is provided.
Is output to the configuration information binary row output selector 47.

Reference numeral 48 denotes a counter for counting the row position of the configuration information, and 49 denotes a counter for counting the column position of the configuration information. Each of the counters 48 and 49 has an externally input configuration information read clock. 50 is input, and the count values of the counters 48 and 49 are decoded by the respective decoders 51 and 52, and are sent to the corresponding configuration information binary row output selector 47 and configuration information binary column output selector 45 as select signals. Is output. Also,
Reference numeral 53 denotes a state signal output generation unit which generates and outputs a configuration information read state signal 53a based on the decode outputs from the decoders 51 and 52 and the configuration information read start signal 54, and 55 denotes a configuration information binary row output selector 47. And a selector for switching the configuration information binary sequence output selector 45. Reference numeral 56 denotes a sum value calculation unit that calculates a sum value from the configuration information binary output output from the selector 55, and 57 selects the configuration information binary output from the selector 55 and the configuration information binary output sum value output. It is a selector. Reference numeral 58 denotes a configuration information binary output CRC (Cyclic Redun).
This is a CRC circuit that performs dan- cy checks.
Reference numeral 9 denotes a selector for switching between the configuration information binary output (including the sum value) and the CRC according to the configuration information read state signal 53a.

In this configuration, the program area 10
The configuration information readout control section 102 always outputs the configuration information binary signal 45. The configuration information binary signal 45 is output to the configuration information binary row output selector 47 and the configuration information binary column output selector 45 according to each matrix position, and further output to the selector 54 selected according to each matrix position and used as a bit stream. Is done. The configuration information data in the form of a bit stream is output directly to the selector 57, and the sum value calculation unit 56 calculates the output sum value for each row. Then, after a CRC bit is added by the CRC circuit 58 after the bit stream data including the sum value, the CRC bit is output to the configuration information diagnostic unit 104 shown in FIG.

The above is the output path of the read data. This operation is activated by the configuration information read activation signal 54. During output, the configuration information read state signal 53a is made significant to output to the outside.

FIG. 5 shows an output format of the configuration information. In FIG. 9A, the output data of the configuration information is the sum value 6 of the synchronization pattern section 61 and the configuration information data section 62.
3. It is composed of a CRC section 64. As shown in FIG. 5B, the configuration information data section can be divided in units of rows or the like. The configuration information read state signal at this time is output as shown by reference numerals 65 and 66.

FIG. 6 is a diagram showing the principle of the configuration information diagnosis unit.
In the figure, configuration information data 71 is input to a serial / parallel converter 73 by a configuration information read clock 71. At this time, as is clear from FIG. 5, the configuration information read state signal 66 is output from the beginning to the end of the configuration information data. This configuration information read state signal 66
In the change from the significant state to the insignificant state, the CRC part is stored in the flip-flop 74. The stored CRC is compared with the expected value of the expected value holding unit 75 by the comparator 76. If the values match, the result of the diagnosis is determined to be good. If writing is necessary again according to the result of the diagnosis, writing is performed again and the writing is corrected.

FIG. 7 shows a case where the FPGA of the present invention is applied as a gate array for interface conversion for connecting a terminal device (for example, a data terminal device) to a public network by a terminal adapter (communication control device). It is a block diagram of. In the figure, 81 is MPU, 82 is RO
M and 83 are RAM, 84 is FPGA, 85 is a diagnostic circuit,
86 is an initialization circuit, 87 is a ROM, 88 is a communication control unit,
Reference numeral 89 denotes a terminal device connected to the communication control unit 88, and reference numeral 90 denotes a public network to which the communication control unit 88 is connected. Reference numeral 91 denotes an alarm output unit.

In this configuration, the MPU 81 controls the communication control unit 88 by the control program stored in the terminal 82 to connect the terminal device 89 connected to the FPGA 84 via the communication control unit 88 to the public network 90. , Performs interface conversion and performs communication. After starting the device,
The FPGA 84 reads configuration information from the configuration information storage ROM 87 and writes the configuration information into an internal program area. After the completion of the writing of the configuration information, signals are transmitted to and received from the surroundings by the circuit configuration of the configuration information written in the program area.

In this embodiment, a peripheral circuit of the MPU 81 and an operation instruction circuit of the communication control unit 88 are programmed. Further, the diagnostic circuit 85 periodically makes the configuration information read start signal significant, and reads out the configuration information with the configuration information read clock signal. The read configuration information data is output to the diagnostic circuit 85 and compared with an expected value. When the result of the comparison is determined to be a failure,
An error detection signal is output to the initialization circuit 86. Upon detecting that the error detection signal is significant, the initialization circuit 86 outputs an initialization signal to the FPGA 84. Alternatively, the data is output to the alarm output unit 91 without being initialized by setting and transmitted to the outside.

As described above, even if the FPGA is periodically diagnosed, it is possible to determine the quality of the device without affecting the operation itself of the device.

In this embodiment, the data terminal device is a terminal adapter (a communication control device to which the present invention is applied).
And when communicating with other data terminal devices via the public network,
It can also be used when the device to which the present invention is applied is online.

[0027]

As described above, according to the present invention, since the configuration information storage ROM, the configuration information read control unit, the configuration information write control unit, and the configuration information diagnosis unit can be built in the FPGA, high integration of the FPGA is achieved. This makes it possible to reduce the size of the electronic device and realize a highly reliable device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an FPGA according to an embodiment of the present invention.

FIG. 2 is a principle diagram of a program area 101 configuring an internal circuit of the FPGA according to the embodiment of the present invention.

FIG. 3 is a principle diagram showing wiring between wirings and a storage / combination part according to the embodiment of the present invention.

FIG. 4 is a principle diagram of reading of a configuration information method according to the embodiment of the present invention.

FIG. 5 is an output format of configuration information according to the embodiment of the present invention.

FIG. 6 is a principle diagram of a configuration information diagnosis unit according to the embodiment of the present invention.

FIG. 7 is a block diagram in the case where the FPGA of the present invention is applied as a gate array for interface conversion for connecting a data terminal device to a public network by a communication control device.

FIG. 8 is a block diagram showing a diagnostic circuit of a device using a conventional FPGA.

[Explanation of symbols]

 Reference Signs List 10 FPGA 11 Configuration information storage ROM 12 Peripheral circuit 101 Program area 102 Configuration information read control unit 103 Configuration information write control unit 104 Configuration information diagnostic unit

Claims (1)

[Claims] 1. A diagnostic method for an electronic device using an FPGA, the FPGA comprising: a program area for writing circuit configuration information of the FPGA; a configuration information storage ROM for storing configuration information data; A configuration information write control unit that writes configuration information data of a storage ROM into the program area; a configuration information read control unit that reads configuration information of the program area; and configuration information that determines the normality of the read configuration information A diagnostic method for an electronic device using an FPGA, comprising a diagnostic unit.