JP2009159528A - Detection sensor having cpu-mounted asic - Google Patents

Detection sensor having cpu-mounted asic Download PDF

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JP2009159528A
JP2009159528A JP2007338187A JP2007338187A JP2009159528A JP 2009159528 A JP2009159528 A JP 2009159528A JP 2007338187 A JP2007338187 A JP 2007338187A JP 2007338187 A JP2007338187 A JP 2007338187A JP 2009159528 A JP2009159528 A JP 2009159528A
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cpu
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detection sensor
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electric signal
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JP5248104B2 (en
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Yuji Sakai
雄二 酒井
Masao Shimazaki
政男 嶋崎
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Panasonic Industrial Devices SUNX Co Ltd
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Sunx Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a detection sensor capable of flexibly coping with custom-ordered products or various specification changes and capable of executing various required signal processing at high speed. <P>SOLUTION: A photoelectric sensor 1 has a light receiving circuit 5a which outputs an electric signal at a level corresponding to presence/absence of a detection target object 4, a detection circuit 7 which detects the presence/absence of the detection target object 4 based on the electric signal, and a display unit 8 which displays the detected presence/absence of the detection target object 4. The photoelectric sensor 1 further has a CPU 2a (central processing unit) which executes various operations and a CPU-mounted ASIC 2 (Application Specific Integrated Circuit) on which a logic circuit unit 2b which executes particular operations is integrally mounted. The CPU 2a executes display processing by the display unit 8, and the logic circuit unit 2b executes operations for the electric signal output from the light receiving circuit 5a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、検出センサ、詳しくは、CPU搭載ASIC(CPU:中央演算処理装置、ASIC:特定用途向け集積回路)を備える検出センサに関する。   The present invention relates to a detection sensor, and more particularly to a detection sensor including a CPU-mounted ASIC (CPU: central processing unit, ASIC: application specific integrated circuit).

従来、光電センサ等の検出センサにおける信号処理としては、ワーク等の被検出物4の有無等の状態の検出を行う検出処理や、その検出結果等を所定の表示部へ表示させる表示処理等がある。   Conventionally, as signal processing in a detection sensor such as a photoelectric sensor, detection processing for detecting a state such as the presence or absence of an object to be detected 4 such as a workpiece, display processing for displaying the detection result or the like on a predetermined display unit, and the like. is there.

この種の光電センサにおいて、前記した検出処理及び表示処理を1つのCPU(制御部)で処理する技術が知られている(例えば、特許文献1等を参照)。
特開2000−22514号公報
In this type of photoelectric sensor, a technique is known in which the above-described detection process and display process are performed by a single CPU (control unit) (see, for example, Patent Document 1).
JP 2000-22514 A

ところが、このように複数の信号処理を1つのCPU(マイコン)で実行させると、必然的に各信号処理が逐次処理となってしまう。即ち、例えば、検出処理の完了後に表示処理が実行され、表示処理の完了後に検出処理が実行されることになるので、検出処理の高速化の実現が困難となる。この場合、CPUの高性能化により、各信号処理の速度は或る程度改善されるものの、クロック周波数の増加に伴う消費電力の上昇や、CPUの単価の上昇といった不利益がある。   However, when a plurality of signal processes are executed by a single CPU (microcomputer) in this way, each signal process inevitably becomes a sequential process. In other words, for example, the display process is executed after the detection process is completed, and the detection process is executed after the display process is completed. Therefore, it is difficult to realize a high speed detection process. In this case, although the speed of each signal processing is improved to some extent by improving the performance of the CPU, there are disadvantages such as an increase in power consumption accompanying an increase in the clock frequency and an increase in the unit price of the CPU.

また、近年、光電センサ等の検出センサにおいては、表示機能の多機能化に伴い、表示処理が煩雑になってきていることもあり、表示処理の高速化がますます強く要求されつつある。   In recent years, detection sensors such as photoelectric sensors have become increasingly demanding to increase the speed of display processing because the display processing has become complicated with the increase in the number of display functions.

これに対し、フルロジック回路(フルロジックASIC)を用いて前記した表示処理を高速化し、各信号処理を高速に行う方法も考えられるが、このような方法では、表示処理の変更の都度、新たなロジック回路の形成(フォトマスクパターン全層の変更)が必要になり、特注製品等における表示機能の仕様変更に柔軟に対応できない。   On the other hand, a method of speeding up the above-described display processing using a full logic circuit (full logic ASIC) and performing each signal processing at high speed is also conceivable. Formation of a simple logic circuit (change of all layers of the photomask pattern) is required, and it is not possible to flexibly cope with a change in display function specification in a custom-made product or the like.

本発明は、上記課題を解決するためになされたものであって、その目的は、特注製品や各種の仕様変更に柔軟に対応でき、しかも、求められる多様な信号処理を高速に実行できる検出センサを提供することにある。   The present invention has been made to solve the above-described problems, and its object is to detect a custom-made product and various specification changes flexibly, and to perform various required signal processing at high speed. Is to provide.

上記問題点を解決するために、請求項1に記載の発明は、被検出物の状態に応じたレベルの電気信号を出力する出力手段と、該電気信号に基づいて前記被検出物の状態を検出する検出手段と、少なくとも前記検出された被検出物の状態を表示する表示手段とを備えた検出センサであって、各種の演算処理を実行するCPU(中央演算処理装置)と、特定の演算処理を実行するロジック回路部とを一体的に搭載するCPU搭載ASIC(特定用途向け集積回路)をさらに備え、前記CPUには、前記表示手段による表示処理を実行させるとともに、前記ロジック回路部には、前記検出手段による前記被検出物の状態の検出処理を実行させるようにしたこと、を要旨とする。   In order to solve the above problems, the invention according to claim 1 is characterized in that an output means for outputting an electric signal of a level corresponding to the state of the object to be detected, and the state of the object to be detected based on the electric signal. A detection sensor comprising a detection means for detecting and a display means for displaying at least the state of the detected object, a CPU (central processing unit) for executing various arithmetic processes, and a specific calculation A CPU-mounted ASIC (integrated circuit for a specific application) that is integrally mounted with a logic circuit unit that executes processing is further provided. The CPU causes the display unit to execute display processing, and the logic circuit unit includes The gist of the present invention is that the detection process of the state of the object to be detected is performed by the detection means.

同構成によれば、表示手段に被検出物の状態を表示させるための表示処理がCPU搭載ASICのCPUによって実行されるとともに、出力手段から出力された電気信号の演算処理、即ち、被検出物の検出処理がCPU搭載ASICのロジック回路部によって実行される。これにより、被検出物の検出処理と、表示手段に被検出物の状態を表示させるための表示処理を並行して実行できるようになり、当該表示処理に要する時間に左右されることなく、被検出物の検出処理を連続的に実行することができるようになる。しかも、表示機能の多機能化に伴い、表示手段に各種情報や機能を表示させる表示処理の頻度や種類が増加しても、ロジック回路部の変更(フォトマスクの変更)によることなく、CPUで用いるソフトウェアの変更によって柔軟に対応できるようになる。   According to this configuration, the display process for displaying the state of the detected object on the display means is executed by the CPU of the CPU-equipped ASIC, and the calculation process of the electric signal output from the output means, that is, the detected object This detection process is executed by the logic circuit unit of the CPU-mounted ASIC. As a result, the detection process of the detection object and the display process for displaying the state of the detection object on the display means can be executed in parallel, and the detection process is not affected by the time required for the display process. The detection process of the detected object can be continuously executed. In addition, with the increase in the number of display functions, even if the frequency and type of display processing for displaying various information and functions on the display means increase, the CPU does not change the logic circuit (changes the photomask). It becomes possible to respond flexibly by changing the software used.

請求項2に記載の発明は、請求項1に記載の検出センサにおいて、前記検出センサは、該検出センサの制御に用いる各種情報の設定操作を行わせる操作手段をさらに備え、前記CPUには、前記操作手段により設定された各種情報の演算処理を実行させるようにしたこと、を要旨とする。   According to a second aspect of the present invention, in the detection sensor according to the first aspect, the detection sensor further includes an operation unit that performs a setting operation of various information used for control of the detection sensor, and the CPU includes The gist is that arithmetic processing of various information set by the operation means is executed.

同構成によれば、操作手段により設定された各種情報の演算処理がCPU搭載ASICのCPUによって実行されるので、当該演算処理が同CPUで用いるソフトウェアの変更によって柔軟に対応できるようになる。   According to this configuration, since the arithmetic processing of various information set by the operating means is executed by the CPU of the CPU-equipped ASIC, the arithmetic processing can be flexibly handled by changing the software used in the CPU.

請求項3に記載の発明は、請求項1又は請求項2に記載の検出センサにおいて、前記検出センサは、外部との通信に用いる通信手段をさらに備え、前記ロジック回路部には、前記通信を行うための電気信号の演算処理を実行させるようにしたこと、を要旨とする。   According to a third aspect of the present invention, in the detection sensor according to the first or second aspect, the detection sensor further includes a communication unit used for communication with the outside, and the logic circuit unit includes the communication. The gist of the present invention is that an electric signal calculation process is performed.

同構成によれば、外部との通信を行うための電気信号の演算処理がCPU搭載ASICのロジック回路部によって実行されるので、当該演算処理が同ロジック回路部によってハードウェア的に高速に実行できるようになる。   According to this configuration, since the arithmetic processing of the electrical signal for performing communication with the outside is executed by the logic circuit unit of the CPU-equipped ASIC, the arithmetic processing can be executed at high speed by the logic circuit unit in hardware. It becomes like this.

本発明によれば、特注製品や各種の仕様変更に柔軟に対応でき、しかも、求められる多様な信号処理を高速に実行できる検出センサが提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the detection sensor which can respond flexibly to a custom-made product and various specification changes, and can perform the various signal processing requested | required at high speed can be provided.

以下、本発明を具体化した実施形態について図面に従って説明する。
図1に示すように、本実施形態において、検出センサとしての光電センサ1は、所謂反射型の光電センサであって、生産ラインのコンベアによって搬送されるワーク等の被検出物4に光を照射する投光手段3と、前記被検出物4に入反射された光を受光する受光手段5と、前記投光手段3及び受光手段5の動作を制御する制御手段としてのCPU搭載ASIC2(CPU:中央演算処理装置、ASIC:特定用途向け集積回路)とを備えている。
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings.
As shown in FIG. 1, in this embodiment, the photoelectric sensor 1 as a detection sensor is a so-called reflection type photoelectric sensor, and irradiates light to a detected object 4 such as a workpiece conveyed by a conveyor of a production line. And a light receiving means 5 for receiving the light incident on and reflected by the detected object 4, and a CPU-mounted ASIC 2 (CPU: CPU) as a control means for controlling the operations of the light projecting means 3 and the light receiving means 5. A central processing unit, ASIC (application specific integrated circuit).

前記投光手段3は、投光回路3aと、該投光回路3aに電気的に接続され、同投光回路3aから出力される電気信号を光に変換し、同光を出射する投光素子3bと、該投光素子3bから出射された光の光路を調節して前記被検出物4に照射する投光レンズ3cとにより構成されている。   The light projecting means 3 is a light projecting circuit 3a and a light projecting element that is electrically connected to the light projecting circuit 3a, converts an electric signal output from the light projecting circuit 3a into light, and emits the light. 3b and a light projecting lens 3c that adjusts the optical path of the light emitted from the light projecting element 3b and irradiates the detected object 4 with the light projecting lens 3c.

前記受光手段5は、入力された光を所定の電気信号に変換する受光素子5bと、前記投光素子3bから出射され、前記被検出物4によって反射された光を前記受光素子5bに導く受光レンズ5cと、該受光素子5bに電気的に接続され、前記受光素子5bから前記電気信号が入力される受光回路5aとにより構成されている。本実施形態では、この受光回路5aによって出力手段が構成されており、同受光回路5aでは、入力された電気信号が、前記被検出物4の有無に応じたレベルになるように所定の増幅率で増幅され出力される。   The light receiving means 5 is a light receiving element 5b that converts input light into a predetermined electric signal, and a light receiving device that guides the light emitted from the light projecting element 3b and reflected by the detected object 4 to the light receiving element 5b. A lens 5c and a light receiving circuit 5a electrically connected to the light receiving element 5b and to which the electric signal is input from the light receiving element 5b. In the present embodiment, the light receiving circuit 5a constitutes an output means. In the light receiving circuit 5a, a predetermined amplification factor is set so that the input electric signal has a level corresponding to the presence or absence of the detected object 4. Is amplified and output.

前記投光回路3aには、当該投光回路3aを駆動する駆動回路6が接続されており、同投光回路3aは、当該駆動回路6から出力される制御信号に基づいて前記投光素子3bに電気信号を出力し、同投光素子3bから出射される光の投光量や出射タイミングを調節する。尚、この駆動回路6も本実施形態の光電センサ1の構成要素である。   A driving circuit 6 for driving the light projecting circuit 3a is connected to the light projecting circuit 3a, and the light projecting circuit 3a is configured based on a control signal output from the drive circuit 6. An electric signal is output to the light projecting element 3b to adjust the light projection amount and the emission timing of the light emitted from the light projecting element 3b. The drive circuit 6 is also a constituent element of the photoelectric sensor 1 of the present embodiment.

前記受光回路5aには、前記受光素子5bにより反射光が受光された被検出物4の状態を検出する検出手段としての検出回路7が接続されている。詳しくは、この検出回路7では、前記被検出物4が所定の検出エリアに存在しないときに前記受光回路5aから出力された電気信号のレベル(受光量)と、該被検出物4が所定の検出エリアに存在するときに前記受光回路5aから出力された電気信号のレベル(受光量)と、後述する設定情報(判定条件)とに基づいて閾値が設定される。そして、該閾値とその時々の電気信号のレベル(受光量)とをコンパレータを用いて比較し、該比較結果に基づいて被検出物4の有無が判定され、該判定結果が検出信号(電気信号)として出力される。   Connected to the light receiving circuit 5a is a detection circuit 7 as a detecting means for detecting the state of the detected object 4 whose reflected light is received by the light receiving element 5b. Specifically, in the detection circuit 7, the level (light reception amount) of the electric signal output from the light receiving circuit 5 a when the detected object 4 does not exist in a predetermined detection area, and the detected object 4 A threshold value is set based on the level (light reception amount) of the electrical signal output from the light receiving circuit 5a when present in the detection area and setting information (determination condition) described later. Then, the threshold value and the level (light receiving amount) of the electric signal at that time are compared using a comparator, the presence or absence of the detection object 4 is determined based on the comparison result, and the determination result is a detection signal (electric signal). ) Is output.

前記CPU搭載ASIC2は、各種の演算処理を実行するCPU2aと、特定の演算処理を実行するロジック回路部2bとを一体的に搭載している。該CPU2aは、各種の制御プログラムを格納(記憶)するとともに、該制御プログラムに必要な各種のデータを記憶するためのメモリ2cを備えている。   The CPU-mounted ASIC 2 is integrally mounted with a CPU 2a that executes various arithmetic processes and a logic circuit unit 2b that executes specific arithmetic processes. The CPU 2a stores (stores) various control programs and includes a memory 2c for storing various data necessary for the control programs.

前記CPU2aには、前記駆動回路6が、同CPU2aから出力される制御信号により制御可能に接続されているとともに、前記検出回路7が、前記検出信号(電気信号)を出力可能なように接続されている。尚、この検出回路7は、前記駆動回路6を介して前記CPU2aによって制御可能なように、当該駆動回路6に接続されている。   The CPU 2a is connected to the drive circuit 6 so as to be controllable by a control signal output from the CPU 2a, and the detection circuit 7 is connected to be able to output the detection signal (electric signal). ing. The detection circuit 7 is connected to the drive circuit 6 so as to be controllable by the CPU 2a via the drive circuit 6.

また、前記CPU2aには、前記検出回路7による被検出物4の有無の判定に関わる判定条件等の設定情報(機能)の設定又は変更操作を行うための操作手段としての操作部8と、前記検出回路7によって検出された被検出物4の有無(被検出物4の状態)、及び、該操作部8を介して設定又は変更された前記設定情報をLED等を用いて表示する表示手段としての表示部9とが接続されている。詳しくは、前記設定情報は、関連するもの同士がまとめられて上層(上位階層)、中層(中位階層)及び下層(下位階層)の3層の階層構造に分類されており、前記操作部8の操作(切替操作)に応じて各階層の設定情報が前記表示部9に切替表示され変更可能となっている。尚、汎用性の高い基本的な設定情報は、最上位の層である上層に分類されるとともに、高度な設定情報は、最下位の層である下層に分類されている。   Further, the CPU 2a includes an operation unit 8 as an operation unit for performing setting operation or setting operation of setting information (function) such as a determination condition related to determination of the presence or absence of the detection object 4 by the detection circuit 7, As display means for displaying the presence / absence of the detection object 4 detected by the detection circuit 7 (the state of the detection object 4) and the setting information set or changed via the operation unit 8 using an LED or the like. The display unit 9 is connected. Specifically, the setting information is grouped into a hierarchical structure of three layers, an upper layer (upper layer), a middle layer (middle layer), and a lower layer (lower layer). In response to the operation (switching operation), the setting information of each layer is switched and displayed on the display unit 9 and can be changed. Basic setting information with high versatility is classified into the upper layer, which is the highest layer, and advanced setting information is classified into the lower layer, which is the lowest layer.

さらに、前記CPU2aには、外部通信装置101及び外部通信装置102に対して、光により通信(光通信)可能な通信手段としての通信用投光素子21a及び通信用受光素子22aが、送信回路21及び受信回路22を介して接続されている。尚、これら通信用投光素子21a及び通信用受光素子22aも本実施形態の光電センサ1の構成要素である。   Further, the CPU 2a includes a communication light projecting element 21a and a communication light receiving element 22a as communication means capable of communicating with the external communication apparatus 101 and the external communication apparatus 102 by light (optical communication). And a receiving circuit 22. The communication light projecting element 21a and the communication light receiving element 22a are also constituent elements of the photoelectric sensor 1 of the present embodiment.

本実施形態では、光電センサ1は、外部の制御ユニットにより一括制御され、前記階層構造をなす設定情報が前記表示部9に階層毎に1つずつ順番に表示されるように、互いに通信可能な状態で他の光電センサ1と隣接配置されている。そして、このように隣接配置された複数の光電センサ1,…及び前記制御ユニットによりセンサシステムが構成されている。   In the present embodiment, the photoelectric sensors 1 are collectively controlled by an external control unit, and can communicate with each other so that the setting information having the hierarchical structure is sequentially displayed on the display unit 9 for each hierarchy. In the state, it is adjacent to another photoelectric sensor 1. A sensor system is configured by the plurality of photoelectric sensors 1,... Arranged adjacent to each other and the control unit.

該各光電センサ1では、前記通信用投光素子21a及び通信用受光素子22aを用い、前記外部通信装置101及び外部通信装置102(制御ユニット又は他の光電センサ1の通信用投光素子21a及び通信用受光素子22a)と光通信が行われる。即ち、前記受信回路22は、外部通信装置102から送信され、前記通信用受光素子22aを介して受信された光信号(パルス光信号等)を電気信号(ディジタル信号)に変換し、CPU2aに入力する。また、前記送信回路21は、CPU2aから出力された電気信号(ディジタル信号)を光信号に変換し、前記通信用投光素子21aを介して外部通信装置101に送信する。   Each of the photoelectric sensors 1 uses the communication light projecting element 21a and the communication light receiving element 22a, and uses the external communication device 101 and the external communication device 102 (the communication light projecting element 21a of the control unit or other photoelectric sensor 1). Optical communication is performed with the communication light receiving element 22a). That is, the receiving circuit 22 converts an optical signal (pulse optical signal or the like) transmitted from the external communication device 102 and received via the communication light receiving element 22a into an electric signal (digital signal) and inputs it to the CPU 2a. To do. The transmission circuit 21 converts an electrical signal (digital signal) output from the CPU 2a into an optical signal, and transmits the optical signal to the external communication device 101 via the communication light projecting element 21a.

そして、本実施形態では、前記CPU2aは、前記制御プログラムに基づいて、光電センサ1の制御に用いるべく前記操作部8により設定又は変更された各種情報であって、前記検出回路7による被検出物4の有無の判定に関わる判定条件等の設定情報の演算処理を実行するとともに、当該設定情報及び前記被検出物4の有無を前記表示部9に表示させる表示処理を実行する。このように、本実施形態のCPU2aは、表示部9の表示制御手段、及び、操作部8の設定制御手段として機能する。   In the present embodiment, the CPU 2a is various information set or changed by the operation unit 8 to be used for controlling the photoelectric sensor 1 based on the control program, and is to be detected by the detection circuit 7. In addition to executing calculation processing of setting information such as determination conditions relating to the determination of the presence / absence of 4, display processing for displaying the setting information and the presence / absence of the detected object 4 on the display unit 9 is executed. As described above, the CPU 2a of this embodiment functions as a display control unit of the display unit 9 and a setting control unit of the operation unit 8.

一方、本実施形態では、前記ロジック回路部2bには、前記検出回路7、並びに、送信回路21及び受信回路22が形成されている。そして、該ロジック回路部2bでは、特定の演算処理を実行するように設計されたロジック回路を用いて、被検出物4の状態の検出処理(前記検出回路7における被検出物4の有無の判定のための電気信号のロジック演算処理)、及び、外部通信装置101,102と通信を行うための電気信号の演算処理(前記送信回路21及び受信回路22における光信号及び電気信号相互間のロジック変換処理)が、並列演算処理によって並行して実行されるように構成されている。   On the other hand, in the present embodiment, the detection circuit 7, the transmission circuit 21, and the reception circuit 22 are formed in the logic circuit unit 2b. Then, the logic circuit unit 2b uses a logic circuit designed to execute a specific calculation process to detect the state of the detected object 4 (determination of the presence or absence of the detected object 4 in the detection circuit 7). Logic processing for electrical signals) and electrical signal computation processing for communication with the external communication devices 101 and 102 (logic conversion between optical signals and electrical signals in the transmission circuit 21 and the reception circuit 22) Are configured to be executed in parallel by parallel arithmetic processing.

本実施形態の光電センサ1(複数の光電センサ1,…)は以上のように構成されており、以下のように動作する。
即ち、図1に示すように、各光電センサ1において、前記駆動回路6から制御信号が出力され、前記投光手段3において、投光回路3aが作動し、投光素子3bから所定の投光量Eの光が所定の出射タイミングで、被検出物4に向けて照射される。この被検出物4に照射された光は、被検出物4によって反射され、前記受光手段5の受光素子5bによって受光される。そして、該受光素子5bにおいて電気信号に変換される。
The photoelectric sensor 1 (a plurality of photoelectric sensors 1,...) Of the present embodiment is configured as described above and operates as follows.
That is, as shown in FIG. 1, in each photoelectric sensor 1, a control signal is output from the driving circuit 6, and in the light projecting means 3, the light projecting circuit 3a is operated, and a predetermined light projecting amount from the light projecting element 3b. E light is emitted toward the detection object 4 at a predetermined emission timing. The light irradiated to the detected object 4 is reflected by the detected object 4 and received by the light receiving element 5 b of the light receiving means 5. And it is converted into an electric signal in the light receiving element 5b.

この電気信号は、さらに受光回路5aに入力され、前記被検出物4の有無に応じたレベルの電気信号に増幅されて前記ロジック回路部2bに形成された検出回路7に入力される。そして、該検出回路7において、前記被検出物4の有無の判定のための電気信号のロジック演算処理が行われる。即ち、当該入力された電気信号のレベル(受光量)が前記閾値と比較され、当該閾値以上の場合には、被検出物4が有ると判定される一方、当該閾値未満の場合には、被検出物4がないと判定される。さらに、該判定結果が検出信号として前記CPU2aに出力され、同CPU2aにおいて前記制御プログラムによる表示処理を経て、各光電センサ1の表示部9に被検出物4の有無が表示される。さらにまた、各光電センサ1の表示部9には、他の光電センサ1から送信された階層構造をなす設定情報が、前記ロジック回路部2bに形成された受信回路22における光信号から電気信号へのロジック変換処理及び前記制御プログラムによる表示処理を経て、前記表示部9に階層毎に1つずつ順番に表示される。   This electric signal is further input to the light receiving circuit 5a, amplified to an electric signal of a level corresponding to the presence or absence of the detected object 4, and input to the detection circuit 7 formed in the logic circuit portion 2b. In the detection circuit 7, an electric signal logic calculation process for determining the presence or absence of the detected object 4 is performed. That is, the level of the input electric signal (light reception amount) is compared with the threshold value, and if it is equal to or higher than the threshold value, it is determined that the detected object 4 is present. It is determined that there is no detected object 4. Further, the determination result is output as a detection signal to the CPU 2a, and the presence or absence of the detected object 4 is displayed on the display unit 9 of each photoelectric sensor 1 through the display process by the control program in the CPU 2a. Furthermore, on the display unit 9 of each photoelectric sensor 1, setting information having a hierarchical structure transmitted from the other photoelectric sensor 1 is changed from an optical signal in the receiving circuit 22 formed in the logic circuit unit 2b to an electrical signal. After being subjected to the logic conversion process and the display process by the control program, they are displayed in order on the display unit 9 for each layer.

本実施形態の光電センサ1によれば、以下のような作用・効果を得ることができる。
(1)被検出物4の有無の判定に関わる判定条件等の設定情報の演算処理、並びに、表示部9に前記設定情報を表示させる表示処理及び被検出物4の有無を表示させる表示処理がCPU搭載ASIC2に搭載されたCPU2a(制御プログラム)によって実行されるとともに、被検出物4の検出処理、及び、外部通信装置101,102と通信を行うための電気信号の演算処理(以下、「通信処理」という。)がCPU搭載ASIC2のロジック回路部2bによって並列演算処理によって実行される。これにより、被検出物4の検出処理、通信処理、及び表示部9に各種情報や機能を表示させる表示処理が並行して実行できるようになり、当該表示処理や通信処理に要する時間に左右されることなく、被検出物4の検出処理を連続的に実行することができるようになる。しかも、ロジック回路部2bにおいては、特定の演算処理を実行するように設計されたロジック回路を用いてハードウェア的に高速処理が可能であるので、被検出物4の検出処理のさらなる高速化にも対応できるようになる。
According to the photoelectric sensor 1 of the present embodiment, the following actions and effects can be obtained.
(1) A calculation process of setting information such as a determination condition relating to the determination of the presence / absence of the detected object 4, a display process for displaying the setting information on the display unit 9, and a display process for displaying the presence / absence of the detected object 4 It is executed by the CPU 2a (control program) mounted on the CPU-mounted ASIC 2, and also performs detection processing of the detected object 4 and calculation processing of electrical signals for communication with the external communication devices 101 and 102 (hereinafter referred to as “communication”). Process ") is executed by parallel logic processing by the logic circuit 2b of the CPU-mounted ASIC 2. As a result, the detection process of the detected object 4, the communication process, and the display process for displaying various information and functions on the display unit 9 can be executed in parallel, which depends on the time required for the display process and the communication process. Therefore, the detection process of the detection object 4 can be continuously executed. In addition, the logic circuit unit 2b can perform high-speed processing in hardware using a logic circuit designed to execute specific arithmetic processing, so that the detection processing of the detected object 4 can be further accelerated. Can also respond.

(2)表示機能の多機能化に伴い、表示部9に各種情報や各種機能を表示させる表示処理の頻度や種類が増加しても、新たなロジック回路の形成(フォトマスクパターン全層の変更)によることなく、CPU2aの制御プログラムの変更によって柔軟に対応できるようになる。   (2) With the increase in the number of display functions, even if the frequency and type of display processing for displaying various types of information and various functions on the display unit 9 increase, formation of a new logic circuit (change of all layers of the photomask pattern) ), It is possible to flexibly cope with the change of the control program of the CPU 2a.

(3)操作部8により設定された各種情報の演算処理がCPU搭載ASIC2のCPU2aによって実行されるので、当該演算処理が同CPU2aで用いる制御プログラムの変更によって柔軟に対応できるようになる。   (3) Since the arithmetic processing of various information set by the operation unit 8 is executed by the CPU 2a of the CPU-equipped ASIC 2, the arithmetic processing can be flexibly handled by changing the control program used by the CPU 2a.

(4)外部通信装置101,102との通信を行うための電気信号の演算処理がCPU搭載ASIC2のロジック回路部2bによって実行されるので、当該演算処理が同ロジック回路部2bによってハードウェア的に高速に実行できるようになる。   (4) Since arithmetic processing of electric signals for performing communication with the external communication devices 101 and 102 is executed by the logic circuit unit 2b of the CPU-mounted ASIC 2, the arithmetic processing is performed by the logic circuit unit 2b in hardware. It can be executed at high speed.

尚、上記実施形態は以下のように変形してもよい。
・上記実施形態では、外部の制御ユニットにより一括制御され、前記階層構造をなす設定情報が前記表示部9に階層毎に1つずつ順番に表示されるように、光電センサ1を互いに通信可能な状態で他の光電センサ1と隣接配置し、このように隣接配置された複数の光電センサ1,…及び前記制御ユニットによりセンサシステムを構成した。しかし、本発明の技術的思想はこれに限られず、図2に示すように、単独で構成され、各種の演算処理を実行するCPU12aと、特定の演算処理を実行するロジック回路部12bとを一体的に搭載するCPU搭載ASIC2を備えるとともに、当該CPU12aは、制御プログラム及び該制御プログラムに必要な各種のデータを格納(記憶)するメモリ12cを有し、同CPU12aには、検出回路7によって検出された被検出物4の有無等を表示する表示部9が接続されている光電センサ10(投光手段3、受光手段5、駆動回路6、及び検出回路7は上記実施形態の光電センサ1と同様に構成されている。)にも適用可能である。
The above embodiment may be modified as follows.
In the above-described embodiment, the photoelectric sensors 1 can communicate with each other so that the setting information having the hierarchical structure is displayed on the display unit 9 one by one for each hierarchy in a batch control by an external control unit. In the state, the sensor system was constituted by the other photoelectric sensors 1 and the plurality of photoelectric sensors 1,... However, the technical idea of the present invention is not limited to this, and as shown in FIG. 2, a CPU 12a that is configured independently and executes various arithmetic processes and a logic circuit unit 12b that executes specific arithmetic processes are integrated. The CPU 12a includes a memory 12c for storing (storing) a control program and various data necessary for the control program. The CPU 12a is detected by the detection circuit 7. The photoelectric sensor 10 to which the display unit 9 for displaying the presence or absence of the detected object 4 is connected (the light projecting means 3, the light receiving means 5, the drive circuit 6, and the detection circuit 7 are the same as the photoelectric sensor 1 of the above embodiment. It is also possible to apply to the above.

・上記実施形態では、検出回路7による被検出物4の有無の判定に関わる判定条件等の設定情報(機能)の設定又は変更操作を行うための操作部8をCPU2aに接続し、同CPU2a(制御プログラム)によって、当該操作部8により設定又は変更(入力)された設定情報の演算処理を実行させるようにした。しかし、本発明の技術的思想はこれに限られず、図2に示すように、各種の演算処理を実行するCPU12aと、特定の演算処理を実行するロジック回路部12bとを一体的に搭載するCPU搭載ASIC12を備えるとともに、当該CPU12aには、検出回路7による被検出物4の有無の判定に関わる判定条件等の設定情報(機能)の設定又は変更操作等を行うための操作部8が接続されておらず、且つ、検出回路7によって検出された被検出物4の有無等を表示する表示部9が接続されている光電センサ10(投光手段3、受光手段5、駆動回路6、及び検出回路7は上記実施形態の光電センサ1と同様に構成されている。)にも適用可能である。   In the above embodiment, the operation unit 8 for setting or changing the setting information (function) such as the determination condition related to the determination of the presence / absence of the detected object 4 by the detection circuit 7 is connected to the CPU 2a, and the CPU 2a ( The calculation process of the setting information set or changed (input) by the operation unit 8 is executed by the control program. However, the technical idea of the present invention is not limited to this, and as shown in FIG. 2, a CPU that integrally includes a CPU 12 a that executes various arithmetic processes and a logic circuit unit 12 b that executes specific arithmetic processes. In addition to the on-board ASIC 12, the CPU 12 a is connected to an operation unit 8 for setting or changing setting information (function) such as determination conditions related to determination of the presence / absence of the detection object 4 by the detection circuit 7. And a photoelectric sensor 10 (light projecting means 3, light receiving means 5, drive circuit 6 and detection circuit) connected to a display unit 9 for displaying the presence or absence of the detected object 4 detected by the detection circuit 7. The circuit 7 is configured similarly to the photoelectric sensor 1 of the above embodiment.

以上のような構成の光電センサ10の場合、図1に示す光電センサ1と同様、被検出物4の検出処理、及び、表示部9に各種情報を表示させる表示処理を、それぞれCPU搭載ASIC2のロジック回路部2b、及び、CPU2a(制御プログラム)によって並行して実行させることができる。これにより、当該表示処理に要する時間に左右されることなく、被検出物4の検出処理を連続的に実行することができるようになる。しかも、ロジック回路部2bにおいては、特定の演算処理を実行するように設計されたロジック回路を用いてハードウェア的に高速処理が可能であるので、被検出物4の検出処理のさらなる高速化にも対応できるようになる。   In the case of the photoelectric sensor 10 configured as described above, as in the photoelectric sensor 1 shown in FIG. 1, the detection process of the detection object 4 and the display process for displaying various information on the display unit 9 are respectively performed by the CPU-mounted ASIC 2. The logic circuit unit 2b and the CPU 2a (control program) can execute them in parallel. Thereby, the detection process of the detection object 4 can be continuously executed without being influenced by the time required for the display process. In addition, the logic circuit unit 2b can perform high-speed processing in hardware using a logic circuit designed to execute specific arithmetic processing, so that the detection processing of the detected object 4 can be further accelerated. Can also respond.

・上記実施形態では、本発明の技術的思想を反射型の光電センサ1に具体化したが、これに限られず、その他の検出センサ、例えば、透過型の光電センサ、ファイバセンサ、レーザセンサに具体化してもよい。   In the above embodiment, the technical idea of the present invention is embodied in the reflective photoelectric sensor 1, but is not limited thereto, and is embodied in other detection sensors such as a transmission photoelectric sensor, a fiber sensor, and a laser sensor. May be used.

本発明の実施形態に係る光電センサの電気的構成を示す回路ブロック図。1 is a circuit block diagram showing an electrical configuration of a photoelectric sensor according to an embodiment of the present invention. 本発明の変形例に係る光電センサの電気的構成を示す回路ブロック図。The circuit block diagram which shows the electric constitution of the photoelectric sensor which concerns on the modification of this invention.

符号の説明Explanation of symbols

1,10…光電センサ(検出センサ)、2,12…CPU搭載ASIC、2a,12a…CPU、2b,12b…ロジック回路部、3…投光手段、4…被検出物、5…受光手段。   DESCRIPTION OF SYMBOLS 1,10 ... Photoelectric sensor (detection sensor), 2,12 ... CPU mounting ASIC, 2a, 12a ... CPU, 2b, 12b ... Logic circuit part, 3 ... Light projecting means, 4 ... Detected object, 5 ... Light receiving means.

Claims (3)

被検出物の状態に応じたレベルの電気信号を出力する出力手段と、該電気信号に基づいて前記被検出物の状態を検出する検出手段と、少なくとも前記検出された被検出物の状態を表示する表示手段とを備えた検出センサであって、
各種の演算処理を実行するCPU(中央演算処理装置)と、特定の演算処理を実行するロジック回路部とを一体的に搭載するCPU搭載ASIC(特定用途向け集積回路)をさらに備え、
前記CPUには、前記表示手段による表示処理を実行させるとともに、
前記ロジック回路部には、前記検出手段による前記被検出物の状態の検出処理を実行させるようにしたことを特徴とする検出センサ。
An output means for outputting an electric signal at a level corresponding to the state of the detected object, a detecting means for detecting the state of the detected object based on the electric signal, and at least the detected state of the detected object is displayed. A detection sensor comprising display means for
A CPU-equipped ASIC (integrated circuit for specific applications) that integrally mounts a CPU (central processing unit) that executes various types of arithmetic processing and a logic circuit unit that executes specific arithmetic processing,
The CPU is caused to execute display processing by the display means,
A detection sensor, wherein the logic circuit unit is caused to execute a detection process of the state of the detection object by the detection means.
請求項1に記載の検出センサにおいて、
前記検出センサは、該検出センサの制御に用いる各種情報の設定操作を行わせる操作手段をさらに備え、
前記CPUには、前記操作手段により設定された各種情報の演算処理を実行させるようにしたことを特徴とする検出センサ。
The detection sensor according to claim 1,
The detection sensor further includes operation means for performing an operation for setting various information used for control of the detection sensor,
A detection sensor characterized in that the CPU is caused to execute arithmetic processing of various information set by the operation means.
請求項1又は請求項2に記載の検出センサにおいて、
前記検出センサは、外部との通信に用いる通信手段をさらに備え、
前記ロジック回路部には、前記通信を行うための電気信号の演算処理を実行させるようにしたことを特徴とする検出センサ。
In the detection sensor according to claim 1 or 2,
The detection sensor further includes communication means used for communication with the outside,
A detection sensor, wherein the logic circuit unit is configured to execute a calculation process of an electric signal for performing the communication.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109981492A (en) * 2019-04-04 2019-07-05 深圳市三旺通信股份有限公司 A kind of method that can intuitively show interchanger operating status

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1082839A (en) * 1996-09-06 1998-03-31 Hitachi Telecom Technol Ltd Diagnostic system for electronic device using fpga
JP2000022514A (en) * 1998-07-02 2000-01-21 Keyence Corp Detector switch and photoelectric switch
JP2000324102A (en) * 1999-05-12 2000-11-24 Toshiba Corp Transmitter and transmission system
JP2003530558A (en) * 2000-04-10 2003-10-14 ハネウェル・インターナショナル・インコーポレーテッド Multifunctional optical sensor with variable detection threshold and noise suppression
JP2004032043A (en) * 2002-06-21 2004-01-29 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and compiler
JP2005295276A (en) * 2004-03-31 2005-10-20 Omron Corp Sensor device
JP2006048632A (en) * 2004-03-15 2006-02-16 Omron Corp Sensor controller
JP2006262227A (en) * 2005-03-18 2006-09-28 Konica Minolta Holdings Inc Hardware configuration device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1082839A (en) * 1996-09-06 1998-03-31 Hitachi Telecom Technol Ltd Diagnostic system for electronic device using fpga
JP2000022514A (en) * 1998-07-02 2000-01-21 Keyence Corp Detector switch and photoelectric switch
JP2000324102A (en) * 1999-05-12 2000-11-24 Toshiba Corp Transmitter and transmission system
JP2003530558A (en) * 2000-04-10 2003-10-14 ハネウェル・インターナショナル・インコーポレーテッド Multifunctional optical sensor with variable detection threshold and noise suppression
JP2004032043A (en) * 2002-06-21 2004-01-29 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and compiler
JP2006048632A (en) * 2004-03-15 2006-02-16 Omron Corp Sensor controller
JP2005295276A (en) * 2004-03-31 2005-10-20 Omron Corp Sensor device
JP2006262227A (en) * 2005-03-18 2006-09-28 Konica Minolta Holdings Inc Hardware configuration device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109981492A (en) * 2019-04-04 2019-07-05 深圳市三旺通信股份有限公司 A kind of method that can intuitively show interchanger operating status

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