JPH1079427A - Manufacture of dielectric layer of semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of dielectric layer of a semiconductor circuit which has the effect of flattening and avoids the formation of a tunnel hole at the edge of the dielectric layer. SOLUTION: This dielectric layer is of such stacking structure that first, a thin CVD is deposited as the first oxide layer 30 on the silicon base 10 where the first metallic sketch 20 is made, and silicate SOG(spin-on-glass) 40, having silicate is deposited, and then a thick CVD is deposited as the second oxide layer 50. By such structure, the gap between the first metallic sketches 20 is completely stopped, and since not only is there no formation on the tunnel hole, by also the surface of the dielectric layer is flat, thus the subsequent process goes ahead smoothly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric layer of a semiconductor circuit.

[0002]

2. Description of the Related Art In the manufacture of semiconductor circuits, generally speaking, in the process of forming a plurality of metal layers, the surface of the last metal layer is raised and lowered. On the other hand, the etched metal part is formed in the shape of a valley of a mountain, that is, a gap of a metal pattern. The part that has not been etched is the summit. As such, when the intervening dielectric layer IMD (Inter Metal Dielectric) intervening between the metal layers straddles the step-shaped peaks and valleys, the step-coverage is increased. Due to the failure, a tunnel hole may be formed in the dielectric layer. Before describing the formation factors and the effects on the process, first, the definition of step coverage will be described.

FIG. 1 shows coverage of uniformity. The step coverage is a percentage of the ratio of the thickness Y of the valley to the thickness X of the peak in the metal layer 1 of the dielectric layer 2. In FIG. 1, since X = Y, the step coverage is 100%. However, what is seen in practice typically has non-uniformity and different step coverage. For example, as shown in FIG. 2, since the thickness of the valley of the peak becomes thin, the step coverage becomes small, and there is a possibility of disconnection. The thicker the deposition of the dielectric material 2 or the worse the step coverage, the closer the distance of A in FIG. 2 becomes, and the worse the distance becomes. As shown in FIG.
A tunnel B is formed.

[0004]

If the above-mentioned tunnel is located at the edge of the metal line, the dielectric material has been converted from the peak to the plane at that location, so that a part of the tunnel hole is deposited on the plane. When filled with the body, the other part is not filled. Eventually, when the dielectric is developed in a later process, the light resistance will enter through the unclosed holes and become thinner,
Concave holes are formed in the dielectric layer, which in severe cases affects the reliability of the underlying metal layer. In addition, since it is difficult to remove the resistance of the light that has entered through the holes that have not been closed, the chip is contaminated in a later process, and the yield rate is greatly reduced.

[0005] In sum, the flatness of the surface of the dielectric layer has a significant effect on subsequent processes, especially with the blurring of the light resistance pattern due to lack of exposure in the recesses. , Resulting in a low yield. To remedy the aforementioned deficiencies, one conventional method is SOG (Sp
in On Glass), and SOG itself mainly uses the characteristics similar to the flow of light resistance. The other is to use O ₃ / TEOS which has good step coverage. O ₃
/ TEOS is O ₃ gas and tetraethoxysilane (Tetr
a ethoxysilane: TEOS: a silicon oxide film formed by decomposing or reacting with a gas evaporated from a chemical solution of Si (OC ₂ H ₅ ) ₄ ). However, both methods require an each-back process, which is not only complicated, but also prone to contamination, high cost and low production volume, so that This is extremely troublesome. Therefore, a flattening process must be provided that flattens the surface, avoids tunnel holes, and is easy to do.

The main object of the present invention is to have a flattening effect,
An object of the present invention is to provide a method for manufacturing a dielectric layer of a semiconductor circuit, which avoids formation of a tunnel hole at an edge of the dielectric layer.

[0007]

SUMMARY OF THE INVENTION A dielectric layer according to the present invention is formed by first depositing a thin CVD film on a silicon base on which a metal pattern is formed.
(Chemical Vapor Deposition) is deposited as a first oxide layer, and SOG (sp
This is a stacked structure in which in-glass is deposited, and then thick CVD is deposited as a second oxide layer. With such a structure, the middle gap of the metal pattern is completely filled, and not only no tunnel hole is formed, but also the surface of the dielectric layer is very flat, so that the subsequent process proceeds smoothly.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. 4, a metal layer of a metal such as aluminum or tungsten is deposited on a silicon base 10 (substrate) by a CVD method, exposed with a mask, developed, and etched. A first metal pattern 20 is formed. Gap W between metal patterns
Then, a step is also formed between the gap W and the height H of the metal pattern (that is, the thickness of the metal layer). The larger the H / W, the deeper the recessed hole, the worse the step coverage of the subsequent deposition, and in the worst case, a tunnel hole. Due to the design limitations of VLSI integrated circuits, the H / W cannot be changed and the method for subsequent deposition of dielectric layers must be used.

According to the need for planarization, SOG having characteristics similar to the flow of light resistance is generally used. However, since SOG is poor in quality and has a high impurity content, it can be directly contacted with a metal layer. Must be isolated with good quality oxides such as CVD to avoid contamination. Then, as shown in FIG. 5, a PECVD (Plasma E) with a current of about several hundred A is placed on the first metal pattern 20.
The first oxidized layer 30 formed by lectric Chemical Vapor Deposit is deposited.

[0010] Then, as shown in FIG.
Deposit silicate SOG40 with properties distinctly different from G. In general SOG, organic substances, that is, CH chains are present and easily adsorb moisture (out glssing), so that when a subsequent metal layer is deposited, moisture is released under a good vacuum, The adhesion of the metal layer formed in the metal contact window (VIA) is deteriorated, and the resistance of the metal contact window is increased.
(Poission VIA).

On the other hand, the silicate SO in the present invention
G40 does not have a CH chain and does not adsorb moisture, so that a phenomenon called poission VIA does not occur. At the same time, the silicate SOG40 can also alleviate the sharp space state formed in the metal pattern,
The tunnel holes mentioned above are eliminated while improving the step coverage of the subsequent deposition.

Accordingly, the present invention provides a method for forming a dielectric layer in a post-process, in which the resistance of light is reduced through an unclosed hole and becomes thin when a dielectric layer is etched. Can also avoid affecting the reliability of the underlying metal layer. Furthermore, the problem that the chip is contaminated in a later process by solving the difficulty of removing the resistance of the light entering through the unclosed hole has been solved.

After depositing SOG, baking (ba
king) process is required, and its action is
By making the composition of the G layer similar to that of the CVD oxide layer, SOG and CVD
Improves the adsorbing force between the oxidized layer. Conventional SO
If G is too thick, a rupture problem occurs, and if the thickness is insufficient, the flatness deteriorates. However, since the purpose of the SOG of the present invention is to fill and flatten the above-described gap and may be thin, there is no problem of rupture.

Then, a second oxide layer 50 having a thickness of about several thousand degrees is deposited by a PECVD method. As shown in FIG. 7, according to the present invention, a structure related to a dielectric layer for isolating a metal layer includes a first oxide layer 30 made of thin PECVD, a SOG 40 containing silicate, and a second structure made of thick PECVD. It is composed of a portion such as the oxide layer 50. Subsequently, CMP (ChemicalMe
Etching (etchi) by polishing method called “chanical Polishing”
ng back), exposed with a mask, visualized, and etched, a metal contact window 51 is formed as shown in FIG. As described above, the metal contact window 51
OG40 is exposed, but thanks to the inclusion of silicate,
The phenomenon called Poission VIA does not occur. After that, a second metal layer such as aluminum is deposited, exposed with a mask, developed, and etched to form a second metal layer.
A metal pattern 60 is formed. Then, the multiple metal layer bonding structure of the present invention is completed as shown in FIG.

The following advantages become clear when the present invention is compared with the prior art. (1) The conventional method requires one etching step for each of the second oxide layers formed by SOG and PECVD.
The present invention etches the second oxide layer formed by PECVD only once. Therefore, the present invention has advantages such as a simple process, low contamination, high yield rate, etc., and reduces the cost and greatly enhances the competitiveness of the product. (2) Poisson VIA (poission VIA) because it uses no silicates and has no organic matter and does not absorb moisture.
A) does not occur. (3) The present invention only effectively fills gaps in the metal pattern and avoids the formation of tunnel holes, since the existing silicate SOG helps to improve the step coverage of subsequent deposition. In addition, the surface of each subsequent layer is flattened, which is advantageous for the development of the subsequent steps.

Summarizing the above, the present invention achieves an effect which has not been seen in the past, and is sufficiently useful in the industrial field.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a uniform coverage.

FIG. 2 is a cross-sectional view of non-uniform coverage.

FIG. 3 is a sectional view of a structure in which a metal layer is covered with a dielectric layer.

FIG. 4 is a view showing a first step of a method for manufacturing a dielectric layer according to the present invention.

FIG. 5 is a view showing a second step of the dielectric layer manufacturing method according to the present invention.

FIG. 6 is a view showing a third step of the method for manufacturing a dielectric layer according to the present invention.

FIG. 7 is a view showing a fourth step of the method for manufacturing a dielectric layer according to the present invention.

FIG. 8 is a view showing a fifth step of the method for manufacturing a dielectric layer according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon base 20 1st metal design 30 1st oxide layer 40 Silicate SOG 50 2nd oxide layer 51 Metal contact window (VIA) 60 2nd metal design

Claims (2)

[Claims] First, a first metal pattern is formed on a silicon base, a first oxide layer is deposited by PECVD, and then a silicate SOG having a silicate is deposited, Depositing a second oxide layer thicker than the first oxide layer by PECVD, etching the second oxide layer by CMP, exposing, developing and etching with a mask, and then opening the metal contact window. Forming a second metal layer, depositing a second metal layer, exposing, developing, and etching with a mask to form a second metal pattern. 2. The method according to claim 1, further comprising the step of baking after depositing silicate SOG having silicate.