JPH1079424A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure stable operation of a MISFET by suppressing the substrate floating effect of an SOI (silicon-on-insulator) substrate. SOLUTION: An n-channel type MISFETQn1 is made on the main face of the semiconductor layer 3a (p-type well 4), made through an insulating layer 2 on a semiconductor substrate 1, and an opening 23a is provided in the insulating layer 2 under the source region 5 of this n-channel type MISFET Qn1. Hereby the semiconductor layer 3a (p-type well 4) in the region where the n-channel type MISFET Qn1 is made and the semiconductor substrate 1 are electrically connected with each other through this opening 23a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to an SOI (Silicon) device.
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having an On Insulator structure.

[0002]

2. Description of the Related Art In a SOI technique in which a thin semiconductor layer is formed on a semiconductor substrate via an insulating layer and an element is formed in this semiconductor layer, complete isolation can be achieved. Compared to the case of forming a semiconductor element,
(1) Since the diffusion parasitic capacitance is reduced, the operation speed of the LSI can be improved. (2) Since the generation of electron-hole pairs due to α-rays is limited to a thin semiconductor layer, a soft error of a memory cell is caused. There is an advantage that the durability is high and the reliability of an LSI equipped with a memory can be improved.

However, on the other hand, MISFE is used for SOI substrates.
When T is formed, a problem is pointed out that a kink occurs in the gate voltage-drain current characteristic due to the substrate floating effect, the threshold voltage fluctuates, and the source-drain breakdown voltage deteriorates. (IEEE Transactions on IEEE Transactions on
Electron Devices Vol.38, No.6, June 1991.p.1384〜
p.1391 "Analysis and Control of Floating-Body Bipol
ar Effects in Fully Depleted Submicrometer SOI
MOSFET's ")).

[0004]

The above-mentioned substrate floating effect occurs because the well region of the MISFET is not electrically connected to the substrate, and the potential is not fixed below the region in the depletion layer state. It is a phenomenon.

Therefore, in order to suppress the floating effect of the MISFET formed in the semiconductor layer of the SOI substrate, for example, (1) the thickness of the semiconductor layer is made sufficiently thin so that the well region is completely formed when a gate voltage is applied. Depletion layer (2) MI
It is necessary to take measures such as providing an opening in the insulating layer below the channel region of the SFET and electrically connecting the well region to the semiconductor substrate through the opening to fix the potential of the well region.

However, there are the following problems in measures to sufficiently reduce the thickness of the semiconductor layer of the SOI substrate and to completely deplete the well region when a gate voltage is applied.

(1) Since the threshold voltage of the MISFET is affected by the thickness of the semiconductor layer, it is necessary to control the thickness of the semiconductor layer in order to control the threshold voltage. It is difficult to control the film thickness of the order of several hundred nm which is depleted.

(2) Enhancement type MISFET
In order to obtain the MISFET, the impurity concentration in the well region must be sufficiently high. However, the higher the impurity concentration, the thinner the semiconductor layer must be in order to obtain a fully depleted MISFET. Becomes more difficult.

In addition, there are the following problems in providing a hole in the insulating layer below the channel region of the MISFET to electrically connect the well region to the substrate.

(1) Since the length of the channel region of the MISFET is equal to the gate length, it is difficult to make the MISFET finer and to form an opening having a diameter equal to the gate length.

(2) It is difficult to align the channel region of the fine MISFET with the opening. If the opening is located below the drain region due to misalignment, the diffusion parasitic is proportional to the area of the opening. Because a capacitance is formed, SO
The advantage of using an I substrate is lost.

An object of the present invention is to provide a technique capable of suppressing a substrate floating effect of an SOI substrate and ensuring a stable operation of a MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the semiconductor integrated circuit device of the present invention, a MISFET is formed on a main surface of an SOI substrate having a semiconductor layer formed on a semiconductor substrate via an insulating layer.
An opening is provided in the insulating layer below the source region of T, and the semiconductor layer and the semiconductor substrate in the region where the MISFET is formed are electrically connected through the opening.
A second opening is provided in the insulating layer of the power supply unit,
A fixed potential is supplied to the semiconductor substrate through the second opening.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, (a) after forming an insulating layer on a semiconductor substrate, forming an insulating film having a different etching rate from the insulating layer on the insulating layer; (B) leaving only the element isolation region by etching and removing the insulating film in the region;
Etching the insulating layer below the region where the source region of the MISFET is formed in a later step to form a first opening reaching the semiconductor substrate, and etching the insulating layer of the power supply unit to form the semiconductor substrate Forming a second hole reaching the first and second holes; and (c) epitaxially growing a semiconductor layer on the surface of the semiconductor substrate exposed at the bottom of the first and second holes to form the first and second holes. Covering the upper part of the semiconductor layer and the upper part of the insulating layer with the semiconductor layer; and (d) flattening the semiconductor layer until the surface thereof is substantially equal to the surface of the insulating film. MIS in active area
Forming an FET, and (e) connecting a wiring to the MISFET and the semiconductor layer of the power supply unit.

The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of (a) preparing an SOI substrate having a first semiconductor layer formed on a semiconductor substrate via an insulating layer;
After forming an insulating film on the OI substrate, the MISF
Etching the insulating film in the region where the source region of ET is formed, the first semiconductor layer and the insulating layer to form a first opening reaching the semiconductor substrate; Forming a second opening reaching the semiconductor substrate by etching the first semiconductor layer and the insulating layer; and (c) forming a second opening of the semiconductor substrate exposed at the bottom of the first and second openings. A step of epitaxially growing a second semiconductor layer on the surface; and (d) a step of forming an element isolation region in the first and second semiconductor layers after removing the insulating film on the first semiconductor layer by etching. (E) MIS is applied to each active region of the first and second semiconductor layers.
Forming an FET, (f) connecting a wiring to the MISFET and the second semiconductor layer of the power supply unit,
Contains.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view of a semiconductor substrate showing a main part of a semiconductor integrated circuit device of this embodiment, and FIG. 2 is a sectional view taken along the line II-II 'of FIG. .

The semiconductor integrated circuit device of the present embodiment has an SOI substrate composed of a semiconductor substrate 1 and a semiconductor layer 3a formed on the semiconductor substrate 1 with an insulating layer 2 interposed therebetween. A plurality of semiconductor elements such as n-channel MISFETs Qn1 and Qn2 are formed on the main surface of the semiconductor layer 3a of the SOI substrate. The semiconductor substrate 1 is made of, for example, p-type single crystal silicon (Si) and has an insulating layer 2
Is made of, for example, a silicon oxide film. In addition, the semiconductor layer 3
“a” is made of epitaxial single crystal silicon doped with a p-type impurity (boron) and functions as a p-type well 4.

The n-channel type MISFET Qn1 is, for example, a part of an element constituting a logic part (G) of a gate array. The n-channel MISFET Qn1 includes a source region 5 and a drain region 6 formed in a part of the p-type well 4 (semiconductor layer 3a), a gate oxide film 7 formed on the surface of the p-type well 4, and a gate And a gate electrode 8 formed on the oxide film 7. Source area 5
Is connected to an Al wiring 16 through a connection hole 11 formed in the silicon oxide film 10, and an Al wiring 17 is connected to the drain region 6 through a connection hole 12 formed in the silicon oxide film 10. .

As shown in FIG. 2, the n-channel MI
An opening 23 is formed in the insulating layer 2 under the source region 5 of the SFET Qn1.
a, and the p-type well 4 in the region where the n-channel MISFET Qn1 is formed is formed through the opening 23a.
And the p-type semiconductor substrate 1 are electrically connected. Part of the opening 23a is an n-channel MISFET Qn1.
, But does not extend to the lower part of the drain region 6.

Although not shown, a part of the semiconductor layer 3a of the logic section (G) functions as an n-type well.
An n-type buried layer is provided in the semiconductor substrate 1 thereunder. A plurality of p-channel MISFETs are formed on the main surface of the n-type well, and the p-channel MISFET is formed.
ET and the n-channel type MISFET Qn1
A gate is configured. Also, this p-channel type MI
An opening is formed in the insulating layer 2 below the source region of the SFET, and a p-channel MISFE is formed through the opening.
The n-type well in the region where T is formed and the n-type buried layer are electrically connected.

A well feeder (W) is provided near the n-channel type MISFET Qn1. A p-type semiconductor region 21 having a higher impurity concentration than the p-type well 4 is formed in the p-type well 4 (semiconductor layer 3a) of the well power supply portion (W). This p-type semiconductor region 21 and n-channel type M
It is separated from the ISFET Qn1 by a silicon nitride film 22 for element isolation. The Al wiring 18 for power supply to the well is connected to the p-type semiconductor region 21 through the connection hole 13 formed in the silicon oxide film 10.

As shown in FIG. 2, an opening 23 is formed in the insulating layer 2 under the p-type semiconductor region 21 of the well power supply portion (W).
The p-type well 4 of the well feeder (W) and the p-type semiconductor substrate 1 are electrically connected through the opening 23b. Therefore, the semiconductor substrate 1 has A
A predetermined fixed potential, for example, an n-channel MISFE, via the l wiring 18, the p-type semiconductor region 21 and the p-type well 4.
A potential substantially the same as the source potential of TQn1 is supplied.

Although not shown, a well power supply section (W) is also provided near the p-channel MISFET in the logic section (G), and its semiconductor layer 3a (n-type well) has an n-type well. An n-type semiconductor region having a higher impurity concentration than the type well is formed. An opening is formed in the insulating layer 2 below the n-type semiconductor region, and the n-type well of the well feeder (W) and the n-type buried layer are electrically connected through the opening. . Further, an Al wiring for well power supply is connected to the n-type semiconductor region through a connection hole formed in the silicon oxide film 10. Therefore, the n-type buried layer has a predetermined fixed potential, for example, p-channel type M via the Al wiring, the n-type semiconductor region and the n-type well.
A potential substantially equal to the source potential of the ISFET is supplied.

On the other hand, the n-channel type MISFET Qn2
For example, it is a part of an element constituting an input / output circuit (I / O). The n-channel MISFET Qn2 has a source region 5 formed in a part of the p-type well 4 (semiconductor layer 3a).
And a drain region 6, a gate oxide film 7 formed on the surface of the p-type well 4, and a gate electrode 8 formed on the gate oxide film 7. An Al wiring 19 is connected to the source region 5 through a connection hole 14 formed in the silicon oxide film 10 and a drain region 6 is formed.
Is connected to an Al wiring 20 through a connection hole 15 formed in the silicon oxide film 10. n-channel type MI
The SFET Qn2 and the p-type semiconductor region 21 of the well feeder (W) are separated by a silicon nitride film 22 for element isolation.

As shown in FIG. 2, the n-channel type MI
The insulating layer 2 is not provided below the p-type well 4 in which the SFET Qn2 is formed. That is, the n-channel MIS
The substrate in the region where the FET Qn2 is formed does not have the SOI structure. This is similar to the input / output circuit (I / O)
The circuit that needs to ensure a certain diffusion parasitic capacitance is SO
This is because it is more advantageous to form the substrate on a normal substrate than on the I substrate.

According to the present embodiment configured as described above, when the gate voltage is applied, the n-channel type MISFET
Semiconductor layer 3 until the channel region of Qn1 is completely depleted.
Since the floating effect of the substrate can be suppressed without reducing a, the current driving capability of the n-channel MISFET Qn1 can be improved. Further, the threshold voltage can be prevented from lowering due to the manifestation of the parasitic bipolar transistor effect, and the threshold voltage can be set to an enhancement type.

According to the present embodiment, by supplying the p-type well 4 with a potential substantially equal to the source potential of the n-channel MISFET Qn1, even if the opening 23a is provided below the source region 5, The formation of a diffusion parasitic capacitance in the source region 5 can be prevented.

According to the present embodiment, the opening 23a is provided below the source region 5 wider than the gate length, so that the opening is provided below the channel region having a length equal to the gate length. , It is easier to secure a margin for aligning the MISFET with the opening. That is, even if a part of the opening 23a extends to the channel region due to misalignment, it does not reach the drain region 6, so that the diffusion parasitic capacitance of the n-channel MISFET Qn1 is reduced to realize high-speed operation. can do.

According to the present embodiment, the insulating layer 2 is not provided below the p-type well 4 in which the n-channel MISFET Qn2 of the input / output circuit (I / O) is formed (SO
By not using the I structure, it is possible to secure the diffusion parasitic capacitance required for the input / output circuit.

Next, the manufacturing method of the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 is heat-treated to form a silicon oxide insulating layer 2 on the surface thereof, and a film thickness is formed on the insulating layer 2 by using a CVD method. A silicon nitride film 22 of about 50 to 200 nm is deposited. Next, as shown in FIG. 4, the silicon nitride film 22 in the active region is removed by etching, leaving the silicon nitride film 22 only in the element isolation region.

Next, as shown in FIG. 5, the insulating layer 2 under the region where the source region (5) of the n-channel type MISFET Qn1 of the logic portion (G) is formed in a later step, and the well power supply portion (W The openings 23a and 23b reaching the semiconductor substrate 1 are formed by etching the insulating layer 2 under the region where the p-type semiconductor region (21) is formed. At the same time, the insulating layer 2 of the input / output circuit section (I / O) is etched to expose the semiconductor substrate 1.

Next, as shown in FIG.
A p-type semiconductor layer 3a is selectively epitaxially grown on the surface of the semiconductor substrate 1 where the input / output circuit section (I / O) and the well feed section (W) are exposed. This semiconductor layer 3a
The silicon nitride film 22 is grown so that its surface is higher than the surface of the silicon nitride film 22 for element isolation. The semiconductor layer 3a is grown so as to cover the entire active region including the upper part of the insulating layer 2.

Next, as shown in FIG. 7, the surface of the semiconductor layer 3a is flattened by polishing or etching back by a chemical mechanical polishing method. The surface of the planarized semiconductor layer 3a is made substantially equal to the surface of the silicon nitride film 22 and has a thickness at least such that the channel region is not completely depleted when a gate voltage is applied.

Next, as shown in FIG. 8, a p-type impurity (boron) is ion-implanted into the semiconductor layer 3a to form a p-type well 4
Is formed, an n-channel MISFET Qn1 is formed in the p-type well 4 of the logic unit (G), and the input / output circuit unit (I /
An n-channel MISFET Qn2 is formed in the p-type well 4 of O), and a p-type semiconductor region 21 is formed in the p-type well 4 of the well feeder (W). n-channel type MISFET Qn1
The gate electrode 8 and the gate electrode 8 of the n-channel type MISFET Qn2 are formed by depositing a polycrystalline silicon film and a silicon oxide film 9 on the semiconductor layer 3a by the CVD method. Patterning and simultaneous formation. Source region 5, drain region 6 of n-channel MISFET Qn1 and n-channel MISFET Qn2
The source region 5 and the drain region 6 of the logical part (G)
An n-type impurity (phosphorus) is ion-implanted into the p-type well 4 of the input / output circuit section (I / O) and the p-type well 4 at the same time. Further, the p-type semiconductor region 21 of the well power supply portion (W)
Is formed by ion-implanting a p-type impurity (boron) into the p-type well 4 of the well power supply portion (W).

Next, as shown in FIG. 9, after a silicon oxide film 10 is deposited on the semiconductor layer 3a by the CVD method, the silicon oxide film 10 is etched to form connection holes 11 to 15.

Thereafter, an Al film is deposited on the silicon oxide film 10 by a sputtering method, and the Al film is patterned to form wirings 16 to 20, thereby forming the semiconductor integrated circuit device shown in FIGS. Is completed.

(Embodiment 2) A manufacturing method of this embodiment will be described with reference to FIGS. In this embodiment, first, as shown in FIG. 10, an SOI substrate in which a semiconductor layer 3b is bonded to a semiconductor substrate 1 made of p-type single crystal silicon via an insulating layer 2 of silicon oxide is prepared.
As an SOI substrate, after implanting oxygen ions into a semiconductor substrate made of silicon single crystal, the semiconductor substrate is heat-treated to form an insulating layer of silicon oxide therein.
So-called SIMOX (Separation by Implanted Oxygen)
An SOI substrate manufactured by a method can also be used.

Next, as shown in FIG. 11, the semiconductor layer 3b
After an insulating film 24 made of silicon oxide or silicon nitride is deposited on the upper surface of the substrate by CVD, MISFE is formed in a later step.
The opening 23 reaching the semiconductor substrate 1 by etching the insulating film 24, the semiconductor layer 3b, and the insulating layer 2 in the region where the source region of T is formed and the region where the well power supply unit is formed.
a and 23b are formed.

Next, as shown in FIG.
After the p-type semiconductor layer 3a is selectively epitaxially grown on the surface of the semiconductor substrate 1 exposed at the bottom of 23b, the surface of the semiconductor layer 3a is planarized by polishing by a chemical mechanical polishing method or by etch back. The surface of the semiconductor layer 3a after the planarization is made substantially equal to the surface of the semiconductor layer 3b, and has a thickness at least such that the channel region is not completely depleted when a gate voltage is applied.

Next, the insulating film 24 on the semiconductor layer 3b is removed by etching, and then, as shown in FIG.
After a field oxide film 25 for element isolation is formed on the surfaces of the semiconductor layers 3a and 3b using the COS method, the n-channel MISFET Qn3 and the n-channel MISFET Qn4 are formed.
Is formed, and a p-type semiconductor region 21 is formed in the well power supply portion. Gate electrode 8 of n channel type MISFET Qn3 and n
The gate electrode 8 of the channel type MISFET Qn4 is formed by depositing a polycrystalline silicon film and a silicon oxide film 9 on the semiconductor layers 3a and 3b by the CVD method and then patterning the silicon oxide film 9 and the polycrystalline silicon film at the same time. Form.
The p-type semiconductor region 21 of the well power supply section is formed by ion-implanting a p-type impurity (boron) into the semiconductor layer 3a.

Next, as shown in FIG.
a, 3b, a silicon oxide film 10 is deposited by a CVD method, and then the silicon oxide film 10 is
1 to 15 are formed. Next, after depositing an Al film on the silicon oxide film 10 by a sputtering method, the Al film is patterned to form wirings 16 to 20, whereby the semiconductor integrated circuit device of the present embodiment is completed.

According to the present embodiment, the n-channel MI
By providing the opening 23a in the insulating layer 2 below the source region 5 of each of the SFET Qn3 and the n-channel MISFET Qn4, the same effect as in the first embodiment can be obtained, and the n-channel MISFE formed on the SOI substrate can be obtained.
Stable operation can be ensured by suppressing the substrate floating effect of TQn3 and n-channel type MISFET Qn4.

In the manufacturing method of the present embodiment, the semiconductor layer 3a is selectively epitaxially grown on the surface of the semiconductor substrate 1 exposed at the bottoms of the openings 23a and 23b (FIG. 12). Also, the formation of the semiconductor layer 3a is easier than in the manufacturing method of the first embodiment (FIG. 6) in which the semiconductor layer 3a is epitaxially grown.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first and second embodiments, and does not depart from the gist of the invention. It goes without saying that various changes can be made.

[0049]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) According to the present invention, the MISFET is formed through the opening provided in the insulating layer below the source region of the MISFET.
Since the semiconductor layer (well) in the region where the FET is formed is electrically connected to the semiconductor substrate, it is possible to suppress the substrate floating effect of the semiconductor layer (well) and to ensure the stable operation of the MISFET. In this case, by forming the fixed potential supplied to the substrate through the power supply unit to be substantially the same as the source potential of the MISFET, it is possible to prevent the formation of a diffusion junction capacitance in the source region.

(2) According to the present invention, since an opening is provided below the source region which is wider than the gate length, the MIS is smaller than when a fine opening is provided below the channel region.
It is easy to secure a margin for aligning the FET and the aperture.

[Brief description of the drawings]

FIG. 1 is a main part plan view of an SOI substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a sectional view taken along the line II-II 'of FIG.

FIG. 3 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

8 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.

FIG. 9 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 insulating layer 3 a semiconductor layer 3 b semiconductor layer 4 p-type well 5 source region 6 drain region 7 gate oxide film 8 gate electrode 9 silicon oxide film 10 silicon oxide film 11 to 15 connection hole 16 to 20 Al wiring 21 p-type Semiconductor region 22 Silicon nitride film 23a Opening 23b Opening 24 Insulating film 25 Field oxide film G Logic section I / O Input / output circuit section Qn1 to Qn4 n-channel MISFET W well feed section

Claims (9)

[Claims] 1. A semiconductor integrated circuit device wherein a plurality of MISFETs are formed on a main surface of an SOI substrate having a semiconductor layer formed on a semiconductor substrate via an insulating layer, wherein the MISFET is provided.
A hole is provided in the insulating layer below the source region of
A semiconductor integrated circuit device, wherein the semiconductor layer in a region where an FET is formed and the semiconductor substrate are electrically connected through the opening. 2. The semiconductor integrated circuit device according to claim 1, wherein a second opening is provided in the insulating layer of the power supply unit, and a fixed potential is supplied to the semiconductor substrate through the second opening. A semiconductor integrated circuit device characterized by the above-mentioned. 3. The semiconductor integrated circuit device according to claim 2, wherein said fixed potential is substantially the same as a source potential of said MISFET. 4. The semiconductor integrated circuit device according to claim 1, wherein a part of the opening provided under a source region of the MISFET extends under a channel region of the MISFET. A semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor layer has a thickness at least such that a channel region is not completely depleted when a gate voltage is applied. A semiconductor integrated circuit device comprising: 6. The semiconductor integrated circuit device according to claim 1, wherein said insulating layer is not provided below some of the MISFETs. apparatus. 7. The semiconductor integrated circuit device according to claim 6, wherein said some MISFETs are MISFETs constituting an input circuit or an output circuit. 8. A method of manufacturing a semiconductor integrated circuit device in which a plurality of MISFETs are formed on a main surface of an SOI substrate having a semiconductor layer formed on a semiconductor substrate via an insulating layer, the method comprising: (a)
After forming an insulating layer on a semiconductor substrate, an insulating film having a different etching rate from the insulating layer is formed on the insulating layer,
Removing the insulating film in the active region by etching to leave only the element isolation region; and (b) etching the insulating layer below the region where the source region of the MISFET is formed in a later step. Forming a first opening reaching the substrate and etching the insulating layer of the power supply to form a second opening reaching the semiconductor substrate; (c) the first and second openings (C) epitaxially growing a semiconductor layer on the surface of the semiconductor substrate exposed at the bottom of the semiconductor substrate, and covering the upper portions of the first and second holes and the upper portion of the insulating layer with the semiconductor layer; After planarizing the surface to a height substantially equal to the surface of the insulating film, the MISFET is formed in the active region of the semiconductor layer.
And (e) connecting a wiring to the MISFET and the semiconductor layer of the power supply unit. 9. A method for manufacturing a semiconductor integrated circuit device in which a plurality of MISFETs are formed on a main surface of an SOI substrate having a semiconductor layer formed on a semiconductor substrate via an insulating layer, the method comprising: (a)
A step of preparing an SOI substrate on which a first semiconductor layer is formed on a semiconductor substrate via an insulating layer; (b) after forming an insulating film on the SOI substrate, a source region of the MISFET is formed in a later step A first opening reaching the semiconductor substrate by etching the insulating film, the first semiconductor layer, and the insulating layer in a region to be supplied, and the insulating film, the first semiconductor layer, and Forming a second opening reaching the semiconductor substrate by etching the insulating layer; and (c) forming a second semiconductor layer on the surface of the semiconductor substrate exposed at the bottom of the first and second openings. (D) forming an element isolation region in the first and second semiconductor layers after removing the insulating film on the first semiconductor layer by etching, and (e) forming the first Of the second semiconductor layer Forming a MISFET in each of the active regions; and (f) connecting a wiring to the MISFET and the second semiconductor layer of the power supply unit. .