JPH1078935A - Swap circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the constitution and to reduce the size of a bus swap circuit for a serial interface which is used to an LSI. SOLUTION: This circuit includes a swap register 8 which is connected to an internal bus 1 that reads and writes the data between a CPU and a peripheral block. The register 8 uses a swap control signal 9 as its input and when the signal 9 is not outputted, the register 8 stores the data which are outputted to the bus 1. When the signal 9 is outputted, the value obtained by swapping the higher and lower order bits of the data outputted to the bus 1 is stored. Then the stored data are read out via the bus 1. No swap circuit is needed in a serial interface 5 owing to presence of the register 8, so that the scale and the area can be reduced for the swap circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a swap circuit in an LSI.

[0002]

2. Description of the Related Art In a system constituted by a plurality of LSI chips, a serial interface is often used as a communication means between LSIs. At this time, the specification of the serial interface of the main controller is often requested to be a bus swap specification so that the communication system can be easily configured regardless of the specifications of other LSIs configuring the system.

[0003] A swap circuit in a conventional LSI will be described below.

FIG. 3 shows the structure of a swap circuit in a conventional LSI. Reference numerals 20 and 25 denote serial interface blocks, and reference numeral 19 denotes an internal portion for connecting the serial interface 20 and the serial interface 25 and mutually transmitting data signals. Indicates a bus.

Reference numerals 21 and 26 denote transmission / reception data shift registers, reference numerals 22 and 27 denote serial interface operation mode control circuits, reference numerals 23 and 28 denote bus swap circuits,
Reference numeral 29 denotes a swap operation control signal for the bus swap circuit 23 and the bus swap circuit 28, respectively. The serial interface 20 includes a shift register 21, a control circuit 22, and a bus swap circuit 23.
The serial interface 25 is a shift register 2
6. It comprises a control circuit 27 and a bus swap circuit 28.

FIG. 4 shows the bus swap circuit 23 shown in FIG.
The structure of is shown.

The serial interface 20 shown in FIG.
When a bit shift register 21 is provided, the bus swap circuit 23 is composed of n selectors. FIG. 4 shows a selector connected to the most significant bit and its peripheral circuits. Input signal 31 from internal bus 30
And the input signal 32 correspond to the MSB and LSB of n-bit data. Further, the input signals 31 and 32 are selected by the control signal 33 of the selector 34 and transmitted to the input signal 35 of the shift register. The output signal 36 from the shift register is converted into the output signal 3 to the bus by the control signal 33.
7 or output signal 38. That is, the input / output signal of the shift register determines the swap / through of the bus data by the swap control signal of the swap circuit.

The operation of the conventional serial interface swap circuit configured as described above will be described below.

When inputting transmission data to the shift register 21 of the serial interface 20, for example, the bus 1
Assuming that '0F' is output to the control signal 9, the control signal 24 becomes'
At the time of L ', the signal passes through the bus swap circuit 23 as through data, and' 0F 'is set in the shift register 21. Conversely, when the control signal 24 is "H", the bus data is swapped by the bus swap circuit 23 and the shift register 2
“1” is set to “F0”. When the data of the shift register 21 is output to the bus 19, for example, if the data of the shift register 21 is “A0”, the control circuit 24 passes through the swap circuit 23 when the control signal 24 is “L”. 'A0' is output. Conversely, when the control signal 24 is 'H', '05' is output to the bus 19 after swapping by the swap circuit 23. The operation of the swap circuit of the serial interface 25 is the same as that of the serial interface 20.

As described above, when a plurality of types of serial interfaces are built in the conventional LSI, different LSIs are used.
In order to incorporate a plurality of types of serial interfaces in different combinations for each I, one swap interface is incorporated in one serial interface.

[0011]

In the LSI swap circuit, a bus swap circuit is incorporated in each of a plurality of serial interfaces, so that there is a problem that the circuit scale is increased and the chip area is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to simplify a serial interface circuit and reduce the area.

[0013]

In order to solve this problem, the present invention omits a bus swap circuit built in each serial interface and uses a swap register dedicated to bus bit exchange separately from the serial interface.
The swap register is provided inside the SI, and has a selector for switching between swap and through on the write side, and is configured to be connected to a plurality of serial interfaces via a bus.

With this configuration, it is not necessary to provide a swap circuit in the serial interface, so that in the case of an LSI incorporating a plurality of serial interfaces, the circuit scale is reduced.

According to a second aspect of the present invention, there is provided an input unit for swapping bus data on an internal bus in accordance with a swap control signal and receiving the data as swap data, and a storage unit for storing data captured by the input unit. And an output unit for sending data stored in the storage unit to the internal bus in accordance with a predetermined control signal.

The input unit starts taking in the bus data in accordance with the take-in control signal, and takes in the bus data as swap data or through data without swapping in accordance with the swap control signal. Is also good.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An internal bus for reading and writing data between a CPU and a peripheral block is connected to a swap control signal, and is output to the internal bus when the swap control signal is not output. When the swap control signal is output, a value obtained by swapping the upper and lower bits of the data output to the internal bus is stored, and the stored data is read through the internal bus. A swap circuit characterized by being used as a general-purpose data register. By using this swap circuit as a general-purpose data register, in the case of a specification having a plurality of serial interfaces inside an LSI, it can be compared with a serial interface having a built-in bus swap circuit. The circuit can be simplified and the area can be reduced. The effect of area saving if the over control functions only in the swap function has the effect of increases.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 shows a swap circuit in an LSI according to an embodiment of the present invention. In FIG. 1, 2 and 5 are serial interface blocks, and 1 is a connection between the serial interface 2 and the serial interface 5. And an internal bus for mutually transmitting data signals.

Reference numerals 3 and 6 denote transmission / reception data shift registers.
4 and 7 are control circuits for the operation mode of the serial interface. The serial interface 2 has a shift register 3 and a control circuit 4 without a swap circuit. The serial interface 5 also has no swap circuit. It comprises a shift register 6 and a control circuit 7. Further, unlike the conventional technique, a swap register 8 is provided inside the LSI separately from the serial interface block, and swap / through control is performed by a swap control signal 9.

FIG. 2 shows the structure of the swap register 8 shown in FIG.

When the serial interface 2 of FIG. 1 has an n-bit shift register 3, the swap register 8 is composed of an n-bit register, and FIG. 2 shows only the circuit related to the most significant bit. . Input signal 11 and input signal 12 from internal bus 10 correspond to the MSB and LSB of n-bit data. In addition, input signal 1
1 and 12 are selected by a control signal 14 of a selector 13 and input to a register 16 by a write signal 15. An output signal 17 from the register 16 is output to the bus 10 by a read signal 18.

The operation of the swap circuit having the above-described configuration according to the present embodiment will be described.

First, the swap register 8 will be described. For example, when "0F" is output to the bus 1, if the control signal 9 is "L", "0F" is stored in the swap register 8 and treated as through data. be able to. If the control signal 9 is “H”, the swap register 8 contains “F”
0 'is stored and can be handled as swap data.

When it is desired to store the swap data in the shift register 3 of the serial interface 2 as transmission data, the control signal 9 of the swap register 8 is set to "H", the swap data is stored in the swap register 8, and then stored in the swap register. The read data is read out onto the bus 1 and the data on the bus 1 is stored in the shift register 3, so that the serial transfer of the swap data becomes possible.

If the control signal 9 is set to "L" and the data on the bus 1 is stored in the swap register 8 as through data, the through data is read onto the bus 1 when the swap register 8 is read. The swap register 8 also functions as a general-purpose data register.

In the embodiment of the present invention, the case where the swap register and the two serial interfaces are used has been described. However, the present invention is not limited to the two, and the functional blocks are not limited to the serial interface. Is effective in all cases of handling swap data, and also has a function as a general-purpose data register.

Further, in the present embodiment, the swap register 8 captures a signal on the internal bus as swap data or through data. However, the present invention is not limited to this. The data may be taken as the swap data and may be dedicated to the swap.

[0029]

As described above, according to the present invention, by using a bus swap circuit as a general-purpose data register, in the case of a specification having a plurality of serial interfaces inside an LSI, a serial interface incorporating a bus swap circuit is provided. Circuit simplification and area saving can be realized as compared with the above. In addition, the swap /
If the through control function is replaced with only the swap function, the effect of area saving is increased.

As a general LSI design method, C
Several types of PU peripheral blocks are prepared as functional modules, and the modules are properly used depending on the specifications of the LSI. For example, in the case of a specification that incorporates a plurality of serial interfaces with a swap function, it was necessary to make a modification such as using a common swap circuit in order to reduce the circuit scale. If the serial interface is incorporated in the LSI, a block without a swap function can be used as the serial interface, so that it is not necessary to add a new correction and the design efficiency can be improved.

[Brief description of the drawings]

FIG. 1 shows a swap circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a swap register in the swap circuit according to the embodiment of the present invention;

FIG. 3 shows a conventional swap circuit.

FIG. 4 is a circuit diagram of a swap register in a conventional swap circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Internal bus 2 Serial interface 3 Shift register 4 Control circuit 5 Serial interface 6 Shift register 7 Control circuit 8 Swap register 9 Control signal 10 Internal bus 11 Bus output signal 12 Bus output signal 13 Selector 14 Control signal 15 Write enable signal 16 Swap register 17 Swap register output signal 18 Read enable signal 19 Internal bus 20 Serial interface 21 Shift register 22 Control circuit 23 Bus swap circuit 24 Control signal 25 Serial interface 26 Shift register 27 Control circuit 28 Bus swap circuit 29 Control signal 30 Internal bus 31 Bus output Signal 32 Bus output signal 33 Control signal 34 Selector 35 Shift register input signal 36 Shift register output signal 7 bus input signal 38 bus input signal

Claims (3)

[Claims] 1. An internal bus for reading and writing data between a CPU and a peripheral block, wherein when the swap control signal is not output, the data output to the internal bus is stored, and the swap control is performed. A swap circuit for storing a value obtained by swapping upper bits and lower bits of data output to the internal bus when a signal is output, and reading the stored data through the internal bus; . 2. An input unit for swapping bus data on an internal bus in accordance with a swap control signal and receiving the data as swap data, a storage unit for storing data captured by the input unit, and storing the data in accordance with a predetermined control signal. And an output section for sending data stored in the section onto the internal bus. 3. The input unit starts capturing the bus data according to a capture control signal, and captures the bus data as swap data or through data without swapping according to the swap control signal. The swap circuit according to claim 2, wherein: