JP2001245330A - Subscriber circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a subscriber circuit device that can realize multi-functions while simplifying the circuit configuration. SOLUTION: The subscriber circuit device is provided with a digital signal processor connected to subscriber lines for an analog telephone network and an Integrated Services Digital Network to apply processing to a signal received through the subscriber lines according to a program, a memory circuit that stores the program and necessary data, and a control circuit that designates a 1st or 2nd operating mode adaptive to the respective analog telephone network and the Integrated Services Digital Network. The control circuit uses the memory circuit to store the program, the required data and coefficients for the signal processing on the analog telephone network in the 1st operating mode, and also the control circuit uses the memory circuit as an elastic store memory for the data transmission and reception between the subscriber circuit device and a station side host device in addition to the storage of the program, the required data and coefficients for the signal processing on the Integrated Services Digital Network in the 2nd operating mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subscriber circuit device, and more particularly to a function and an ISDN corresponding to an analog telephone.
The present invention relates to a technique particularly effective for use in a shared subscriber circuit device that can be adapted to both functions corresponding to (integrated digital communication network).

[0002]

2. Description of the Related Art There is an integrated digital communication network (ISDN) in which an analog transmission line for telephone is used as a subscriber line, and a subscriber circuit device (network) provided corresponding to the subscriber line of such an integrated digital communication network. Terminator). A subscriber circuit device includes a so-called digital subscriber line transmission equalizer LSI including an equalizer for correcting the frequency characteristic of the subscriber line or removing intersymbol interference due to echo or the like at each branch of the subscriber line. (Large-scale integrated circuit device), so-called ping-pong L
An SI (semiconductor integrated circuit device) is provided. On the other hand, even in a subscriber circuit device corresponding to an analog telephone, the frequency characteristic of the subscriber line is corrected in response to an analog signal (voice signal), or an intersymbol interference due to an echo or the like at each branch of the subscriber line is removed. An analog subscriber line circuit device is provided.

[0003]

The development of a service-shared subscriber circuit device (line card) which can be selectively applied to both the above-mentioned ISDN and analog telephone is underway.
In such a subscribed circuit device sharing a service, when switching from analog telephone to ISDN, it can be easily performed only by switching the operation mode of the subscriber circuit device, and can be easily applied to a new service. However, in the ping-pong LSI conforming to the ISDN, a logic gate using a flip-flop circuit is used as an elastic store memory for temporarily storing communication data. With this elastic store alone, the logic becomes 4K gates or more, resulting in an increase in logic scale, that is, an increase in chip area. Therefore, in the above-described subscriber circuit device of the shared service type, it is necessary to additionally provide a function corresponding to the aronag telephone, which has a problem that the circuit scale is greatly increased. .

An object of the present invention is to provide a subscriber circuit device which realizes the above-mentioned multi-function while simplifying the circuit. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a digital signal processor which is provided corresponding to the subscriber lines of both the analog telephone and the integrated digital communication network and performs signal processing transmitted through the subscriber lines according to a program, and stores the program and necessary data. Memory circuit, and a control circuit for designating first and second operation modes respectively corresponding to the analog telephone or the integrated digital communication, wherein the control circuit controls the analog telephone in the first operation mode. The memory circuit is used to store a program for signal processing and necessary data and coefficients in the second operation mode, in addition to a program for signal processing for integrated digital communication and storage of necessary data and coefficients. Of data transfer between the subscriber's circuit device and the central station And have the ability to use the memory circuit as Amemori.

[0006]

FIG. 1 is a block diagram showing a main part of an embodiment of a subscriber's circuit device according to the present invention.
Although not particularly limited, each circuit block in the figure is formed on one semiconductor substrate by a known gate array semiconductor integrated circuit manufacturing technique. In this embodiment, a subscriber circuit (SLIC-LSI) corresponding to an analog telephone is used.
And a common subscriber circuit device having the function of a ping-pong LSI compatible with ISDN. FIG. 1 shows a block diagram corresponding to the ISDN mode.

[0007] The communication line is a telephone cable connecting between a telephone station and a subscriber, and a signal transmitted from the communication line is received by an analog interface (I / F) 10. This received signal is processed by a digital signal processor (hereinafter simply referred to as DSP) 20. The DSP 20 includes a memory circuit (hereinafter simply referred to as a RAM
(Referred to as a random access memory) 30 in accordance with a signal processing procedure (program command) stored in the RAM 30 to correct the frequency characteristic of the communication line (subscriber line) or to join the line. A received signal processing including an equalizer for removing an intersymbol interference due to an echo or the like in each branch of the subscriber line is performed using the coefficient data stored in the RAM 30 and the temporarily stored data in the signal processing.

The received data signal-processed by the DSP 20 is reproduced by a received data verification circuit. The received data is relatively low-speed data corresponding to the frequency characteristic of the communication line, and is converted into high-speed data between the host device and the RAM.
An IF (RAM interface) control circuit 90 temporarily writes the data to a predetermined storage area of the RAM 30 included in the DSP 20, that is, an area not used as the temporary storage data by the DSP 20. When a certain amount of received data is accumulated in the RAM 30, the data is read out by the RAM IF control circuit 90 and output to the host device through the output circuit 70 as, for example, 4 MHz data.

[0009] High-speed data (4 MHz
Data) is input by the input circuit 80, and the RA
Through the M IF control circuit 90, the D
The data is stored in a predetermined storage area that is not used as the temporary storage data by the SP 20. The transmission data stored in the RAM 30 is read out by the RAM IF control circuit 90 in accordance with the low-speed data transmission timing on the communication line, and transmitted to the communication line through the transmission data conversion circuit 60.

The operations of the analog I / F 10, the DSP 20, the reception data verification circuit 50, the transmission data conversion circuit 60 and the like are performed by a clock supplied from the timing control circuit 40. The DSP 20 sends phase information to the timing control circuit 40, receives a clock corresponding to the phase information, and performs signal processing using the coefficient data and the temporarily stored data according to the program command.

When operating the subscriber's circuit device in the SLIC mode corresponding to an analog telephone, the reception data verification circuit 50, the RAM IF control circuit 90, and the transmission data conversion circuit 60 do not operate, respectively, and output signals. Is bypassed. Data conversion between the communication line and the host device is performed by the DSP 20. That is, the analog signal received from the communication line is transmitted to the communication line (subscriber line) through the analog I / F 10 as described above.
In addition to the reception signal processing including an equalizer that corrects the frequency characteristic of
Generate high-speed data at z. Conversely, the high-speed data input from the host device is signal-processed by the DSP 20 and converted into an analog signal, and a transmission signal is output to a communication line through a transmission analog I / F (not shown).

As described above, when the DSP 20 is in the SLIC mode, the DSP 20 transmits and receives high-speed data to and from a higher-level device as performed by the reception data verification circuit 50 and the transmission data conversion circuit 60 in the ISDN mode. Such digital data processing is also required, and a data RAM having a relatively large storage capacity is required for such digital data processing.

In the above-mentioned shared subscriber circuit device, the above R
The AM 30 needs to secure a large-capacity data RAM area that is not necessary in the ping-pong mode corresponding to the ISDN for the SLIC mode corresponding to the analog telephone. That is, the program instruction RAM, coefficient data RAM, and data RAM included in the RAM 30
Among them, the data RAM uses a considerable part in the SLIC mode corresponding to the analog telephone, but uses only a small part in the ping-pong mode. Focusing on this, in this embodiment, the RAM IF control circuit 90 is added as described above, and the data RA
The M portion is used as an elastic store memory required in the ping-pong mode. As a result, the elastic store memory configured by the dedicated logic of the ping-pong mode, which was conventionally required, is reduced,
The logical scale as a whole can be reduced.

FIG. 2 is a block diagram for explaining the relationship between the RAM IF control circuit and the RAM according to the present invention. The RAM 30 is connected to a DSP (not shown) by an 18-bit data bus. RAM3
0, DRAMCE is a select signal line and DRCE is
AMRW is a read / write control line, and DRAMAD is an address signal line.

Three types of multiplexers MPX1 to MPX3 are provided for each of these signal lines. One multiplexer MPX1 includes a selection signal line ESRAMCE from the RAM IF control circuit and a selection signal line DRAMC from the DSP.
E1 is selectively connected to the selection signal line DRAMCE. The other multiplexer MPX2 includes read / write control signal lines ESRAMRW and DS from the RAM IF control circuit.
The read / write signal line DRAMRW1 from P is selectively connected to the read / write control signal line DRAMRW. The remaining multiplexer MPX3 is composed of a plurality of address signal lines ESRAMA from the RAM IF control circuit.
Address signal line DRAM composed of a plurality of D and DSP
AD is selectively connected to the address signal line DRAMAD. The multiplexers MPX1 to MPX3 are connected to the RA
According to the control signal ESSEL from the MIF control circuit,
A connection is made to either the RAM IF control circuit or the DSP.

Between the data bus and the RAM IF control circuit, flip-flops (registers) FF1 and FF2 as buffer circuits are provided. That is, RAM
When writing data to the RAM 30 through the IF control circuit, the write data E is controlled by the signal ESINCK.
The SIN is taken into the flip-flop circuit FF1, the output circuit OB is operated by the signal ESDOUT, and the write data is transmitted to the data bus. RAM 30
Is supplied with a selection signal via the multiplexer, and the write data transmitted to the data bus is written to the selected memory cell. Conversely, R
When data is read from the RAM 30 by the AM IF control circuit, a signal on the data bus is taken into the flip-flop circuit FF2 by the signal ESOTCK, and the signal ESOT is taken. A selection signal is supplied to the RAM 30 via the multiplexer, and a read signal is output to a data bus.

FIG. 3 is a timing chart for explaining one embodiment of the control switching operation of the RAM. Normally, the data RAM is used by the DSP.
While the SP is stopped, the signal DSPHALT is set to the high level. In response to the high level of the signal DSPHALT, the ESS is sent from the RAM I / F control circuit 90 to the ESS.
The control is switched by setting the EL signal to the high level. At this time, although not particularly limited, the time for using the RAM 30 as an ES (elastic store) memory is set to 4 steps immediately before the DSP starts to operate, and 1 step before and after the DSP.
p is left open for switching.

In the subscriber's circuit device, data exchange with the telephone line side is performed by a time-division directional control system. For example, in the ISDN mode, data of one bit is transmitted every 320 KHz in transmission of 360 bits and in reception of 360 bits. Are alternately transmitted and received. Therefore, the writing of the reception data and the reading of the transmission data are temporally separated and performed alternately. The data exchange with the host device is 8KHz.
The readout of the received data and the writing of the transmitted data are performed every 8 KHz. Therefore, even if the writing of the reception data and the reading of the transmission data and the writing of the transmission data and the reading of the reception data are the same steps as shown in FIG.

FIG. 4 is a schematic timing chart for explaining an example of the operation of the subscriber circuit device according to the present invention in the ISDN mode. As described above, the exchange of data with the telephone line (communication line) is based on a time-division directional control system, and data is transmitted and received alternately at intervals of 320 KHz by transmitting 1-bit data of 360 bits for transmission and 360 bits for reception. ing. Therefore, the writing of the reception data and the reading of the transmission data are alternately performed in a temporally separated manner. At the same time, data exchange with the host
18 bits are performed every 8 KHz, and reading of received data and writing of transmission data are performed every 8 KHz.

FIG. 5 is a block diagram showing a main part of another embodiment of the subscriber's circuit device according to the present invention. In this embodiment, a subscriber circuit (SLIC-LSI) corresponding to analog telephone and a ping-pong L corresponding to ISDN
It is directed to a shared type subscriber's circuit device having an SI function, and FIG. 1 shows a block diagram corresponding to the ISDN mode.

In this embodiment, the DSP 20 is provided with four registers. That is, the RAM shown in FIG.
The IF control circuit 90 is deleted, and the DSP 20
, Four registers 91 to 94 are added. The first register 91 is used for receiving output data of the received data verification circuit 50 and writing the received data to the RAM 30. The second register 92 is used for receiving the received data read from the RAM 30 and transmitting it to the 4 MHz data output circuit 70. Third register 9
Reference numeral 3 is used as a buffer for receiving transmission data input to the 4 MHz data input circuit 80 and writing it to the RAM 30. The fourth register 94 is used to receive the transmitted data read from the RAM 30 and send it to the transmission data conversion circuit 60.

In the embodiment shown in FIG. 1, access to the RAM 30 is controlled by the hardware (RAM IF control circuit 90).
1 to 94, and the registers 91 to 94 are stored in the DSP 2
Control is performed on the software side by using a DSP internal register so that 0 can be accessed. That is, the writing and reading of the RAM as described above are also one of the signal processes of the DSP 20.
First, it is executed by a program instruction.
This eliminates the need for a hardware control circuit and further reduces the number of logic gates.

The operation and effect obtained from the above embodiment are as follows. (1) A digital signal processor which is provided for both an analog telephone and a subscriber line of an integrated digital communication network and performs signal processing transmitted through the subscriber line according to a program, and stores the program and necessary data. Memory circuit, and a control circuit for designating first and second operation modes respectively corresponding to the analog telephone or the integrated digital communication, and the control circuit controls the analog telephone in the first operation mode. The above-mentioned memory circuit is used to store a program for signal processing for communication and necessary data and coefficients. In the second operation mode, a program for signal processing for integrated digital communication and storage of necessary data and coefficients are used. In addition, the elasticity of data transfer between the subscriber's circuit device and the central station higher-level device By providing a function of using the memory circuit as a memory, it is possible to achieve a subscriber circuit device that realizes the above-mentioned multi-function while simplifying the circuit.

(2) In addition to the above, a first memory circuit for storing program instructions, a second memory circuit for temporarily storing data used in signal processing, and a second memory circuit for storing coefficients used in signal processing. In the memory circuit including three memory circuits, the ISDN in the second memory circuit may be used.
By using the empty area in the mode as the elastic store memory, the SLIC mode and the IS
The effect that the data memory can be used efficiently in the DN mode can be obtained.

(3) In addition to the above, first to fourth registers are further provided, and when outputting data to the higher-level device, receive data is written to the first register, and the higher-level device is passed through the second register. Output data to
When transmitting data to the subscriber line, the higher-level device writes transmission data to a third register, outputs the transmission data through a fourth register, and inputs data between the first to fourth registers and the memory circuit. By performing the output as one of the data processing by the digital signal processor, an effect that the circuit can be further simplified can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, the signal processing by the DSP and the signal processing of digital data may be such that signal processing for additional functions or new services is performed in analog telephone communication and ISDN communication as described above. In such a change or addition of a function, if the above-mentioned RAM is incorporated and a program command is written, the change or addition of such a function can be easily performed. Although not particularly limited, the program instructions and coefficient data stored in the RAM are stored in a non-volatile memory such as a flash memory, and the subscriber circuit malfunctions due to a power cycle of the subscriber circuit device or a lightning strike. In such a case, after the reset, a program command or coefficient data may be transferred from the flash memory. INDUSTRIAL APPLICABILITY The present invention can be widely used for at least a shared type subscriber circuit device for analog telephones and ISDN.

[0027]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a digital signal processor which is provided for both an analog telephone and a subscriber line of an integrated digital communication network and performs signal processing transmitted through the subscriber line according to a program, and stores the program and necessary data. Memory circuit, and a control circuit for designating first and second operation modes respectively corresponding to the analog telephone or the integrated digital communication, wherein the control circuit controls the analog telephone in the first operation mode. The memory circuit is used to store a program for signal processing and necessary data and coefficients in the second operation mode, in addition to a program for signal processing for integrated digital communication and storage of necessary data and coefficients. Elasticity in data transfer between the subscriber's circuit device and the central station By having the ability to use the memory circuit as Toamemori,
It is possible to realize a subscriber circuit device that realizes the above multi-functionality while simplifying the circuit.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing one embodiment of a subscriber circuit device according to the present invention.

FIG. 2 is a diagram illustrating a RAM IF control circuit and a RAM according to the present invention;
FIG. 3 is a block diagram for explaining the relationship with the above.

FIG. 3 is a timing chart for explaining one embodiment of a control switching operation of the RAM of FIG. 1;

FIG. 4 is a schematic timing chart for explaining an example of an operation in an ISDN mode of the subscriber's circuit device according to the present invention.

FIG. 5 is a main part block diagram showing another embodiment of the subscriber's circuit device according to the present invention.

[Explanation of symbols]

10 ... analog I / F, 20 ... DSP, 30RAM,
40 timing control circuit, 50 reception data verification circuit, 60 transmission data conversion circuit, 70 data output circuit, 80 data input circuit, 90 RAM IF control circuit, 91-94 register, FF1, FF2 flip-flop Circuit, MPX1-3 ... Mux.

Claims (3)

[Claims] 1. A subscriber circuit device provided for a subscriber line of both an analog telephone and an integrated digital communication network, wherein the digital signal processing performs signal processing transmitted through the subscriber line according to a predetermined program. A processor, a memory circuit in which a program for signal processing for analog telephone or integrated digital communication and necessary data are stored, and a first circuit and a first adaptive circuit corresponding to the analog telephone or integrated digital communication, respectively. And a control circuit for designating an operation mode. The control circuit uses the memory circuit in the first operation mode to store a program for signal processing for an analog telephone and necessary data and coefficients. In the second operation mode, a program for signal processing for integrated digital communication and necessary data and Subscriber circuit device characterized by and have the ability to use the memory circuit as the elastic store memory at the data transfer between the number of in addition to the storage subscriber circuit devices and Tsubonegawa host device. 2. The memory circuit according to claim 1, wherein the memory circuit includes a first memory circuit for storing a program instruction, a second memory circuit for temporarily storing data used in signal processing, and a coefficient used in signal processing. A subscriber circuit device comprising a third memory circuit for storage, wherein a free area in the second memory circuit is used as the elastic store memory. 3. The device according to claim 1, further comprising first to fourth registers, wherein the first register is provided when outputting data to the host device.
When receiving data is written to a register, data is output to a higher-level device through a second register, and when data is transmitted to the subscriber line, transmission data is written from a higher-level device to a third register, and transmission data is transmitted through a fourth register. Wherein the input / output of data between the first to fourth registers and the memory circuit is performed as one of data processing by the digital signal processor.