JPH1074798A - Method and structure for mounting semiconductor - Google Patents

Method and structure for mounting semiconductor

Info

Publication number
JPH1074798A
JPH1074798A JP23015096A JP23015096A JPH1074798A JP H1074798 A JPH1074798 A JP H1074798A JP 23015096 A JP23015096 A JP 23015096A JP 23015096 A JP23015096 A JP 23015096A JP H1074798 A JPH1074798 A JP H1074798A
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring board
mounting
semiconductor
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23015096A
Other languages
Japanese (ja)
Inventor
Michiko Ono
美智子 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23015096A priority Critical patent/JPH1074798A/en
Publication of JPH1074798A publication Critical patent/JPH1074798A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Abstract

PROBLEM TO BE SOLVED: To provide a method and structure for mounting semiconductor by which the workability of sealing resin injecting work can be improved by smoothly injecting the resin into the narrow clearance between a semiconductor chip and a wiring board. SOLUTION: In a semiconductor mounting method in which a semiconductor chip 10 is mounted on a wiring board 11 in a face-down state, the chip 10 is mounted on the semiconductor chip mounting part of the board 11 in a face- down state after an insulating inorganic filler 16 is supplied to the semiconductor chip mounting part. Then the clearance between the chip 10 and substrate 11 is filled up with a sealing resin 19 and the resin 19 is heated and cured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、半導体チップを
配線基板に実装する半導体実装方法およびその実装構造
に関する。
The present invention relates to a semiconductor mounting method for mounting a semiconductor chip on a wiring board and a mounting structure thereof.

【0002】[0002]

【従来の技術】フリップチップ実装方法は、占有面積を
チップ寸法と同等まで小さくでき、しかも極限まで薄形
化が可能であり、小型軽量化が図れることで注目されて
いる。前記フリップチップ実装方法は、半導体チップを
フェースダウンで配線基板に接続して実装されるように
なっており、半導体チップのバンプが配線基板の電極パ
ッドに直接的に接続される。しかし、半導体チップと配
線基板とは熱膨張係数が異なり、この熱膨張係数の差に
より、接続部に熱応力が生じ、接続部にクラックが発生
する虞がある。
2. Description of the Related Art A flip-chip mounting method has attracted attention because it can reduce the occupied area to the same size as the chip, can be made as thin as possible, and can be reduced in size and weight. In the flip-chip mounting method, a semiconductor chip is mounted face-down on a wiring board and mounted, and bumps of the semiconductor chip are directly connected to electrode pads of the wiring board. However, the semiconductor chip and the wiring board have different coefficients of thermal expansion. Due to the difference in the coefficient of thermal expansion, a thermal stress is generated in the connection part, and a crack may be generated in the connection part.

【0003】そこで、半導体チップと配線基板との間隙
に無機フィラーを混合して熱膨張係数を低くした封止樹
脂を充填することによって、前記半導体チップと配線基
板との熱膨張係数の差によって接続部に生じる熱応力を
緩和することが行われている。
[0003] Therefore, by filling the gap between the semiconductor chip and the wiring board with a sealing resin having a low thermal expansion coefficient by mixing an inorganic filler, a connection is made due to the difference in the thermal expansion coefficient between the semiconductor chip and the wiring board. It has been practiced to reduce the thermal stress generated in the part.

【0004】このような半導体実装構造を形成する半導
体実装方法は、従来、半導体チップをフェースダウンで
配線基板に接続した後、半導体チップの周辺に封止樹脂
を塗布し、毛細管現象を利用した樹脂注入により行うの
が一般的であった。
Conventionally, a semiconductor mounting method for forming such a semiconductor mounting structure is to connect a semiconductor chip to a wiring board face down, apply a sealing resin to the periphery of the semiconductor chip, and use a resin utilizing a capillary phenomenon. It was common to do this by injection.

【0005】図9は従来のはんだバンプを持った半導体
チップの実装方法を示し、1は半導体チップ、2は配線
基板である。半導体チップ1の下面には複数のはんだバ
ンプ3が形成され、配線基板2には前記はんだバンプ3
に対応して電極パッド4が形成されている。
FIG. 9 shows a conventional mounting method of a semiconductor chip having solder bumps, 1 is a semiconductor chip, and 2 is a wiring board. A plurality of solder bumps 3 are formed on the lower surface of the semiconductor chip 1, and the solder bumps 3 are formed on the wiring board 2.
The electrode pad 4 is formed corresponding to.

【0006】図9(a)に示すように、半導体チップ1
をフェースダウンさせ、はんだバンプ3を配線基板2の
電極パッド4に位置決めし、同図(b)に示すように、
配線基板2に半導体チップ1を搭載し、加熱によっては
んだバンプ3を溶融して電極パッド4に接続する。な
お、この段階で半導体チップ1の実装不良が検出された
場合には新たな半導体チップ1に交換(リペア)するこ
とができる。
[0006] As shown in FIG.
Face down, the solder bumps 3 are positioned on the electrode pads 4 of the wiring board 2, and as shown in FIG.
The semiconductor chip 1 is mounted on the wiring board 2, and the solder bumps 3 are melted by heating and connected to the electrode pads 4. If a mounting failure of the semiconductor chip 1 is detected at this stage, the semiconductor chip 1 can be replaced (repaired) with a new semiconductor chip 1.

【0007】次に、同図(c)に示すように、シリンジ
5aを用いディスペンス法によって液状のエポキシ樹脂
等の熱硬化性樹脂からなる封止樹脂5を半導体チップ1
の周辺の配線基板2に塗布すると、封止樹脂5は毛細管
現象によって電極パッド4の間を通って半導体チップ1
と配線基板2との間隙(50μm程度)に充填される。
Next, as shown in FIG. 1C, a sealing resin 5 made of a thermosetting resin such as a liquid epoxy resin is dispensed by a dispensing method using a syringe 5a.
Is applied to the wiring substrate 2 around the semiconductor chip 1, the sealing resin 5 passes through the space between the electrode pads 4 by capillary action.
Is filled in the gap (about 50 μm) between the substrate and the wiring board 2.

【0008】ここで用いているエポキシ樹脂等の封止樹
脂5は、熱膨張係数(60〜70ppm/℃)が接続材
料として用いるはんだ(27ppm/℃)や金(14p
pm/℃)と比較して高いため、樹脂成分中に40〜7
0wt%程度のシリカなどの無機フィラーを混合するこ
とにより、使用温度範囲における熱膨張係数を20〜4
0ppm/℃程度に低下させたものである。
The sealing resin 5 such as epoxy resin used here has a thermal expansion coefficient (60 to 70 ppm / ° C.) of solder (27 ppm / ° C.) or gold (14 p.
pm / ° C), so that 40 to 7
By mixing about 0 wt% of an inorganic filler such as silica, the coefficient of thermal expansion in the operating temperature range is 20 to 4%.
It was reduced to about 0 ppm / ° C.

【0009】次に、封止樹脂5を120〜160℃程度
に加熱させると、同図(d)に示すように、半導体チッ
プ1と配線基板2との間および半導体チップ1の周辺の
封止樹脂5が硬化する。
Next, when the sealing resin 5 is heated to about 120 to 160 ° C., the sealing between the semiconductor chip 1 and the wiring substrate 2 and the periphery of the semiconductor chip 1 is performed as shown in FIG. The resin 5 cures.

【0010】図10は従来の金バンプを持った半導体チ
ップの実装方法を示し、図9と同一構成部分には同一番
号を付して説明を省略する。半導体チップ1の下面には
複数の金バンプ6が形成され、配線基板2には前記金バ
ンプ6に対応して電極パッド4が形成されている。
FIG. 10 shows a conventional mounting method of a semiconductor chip having gold bumps. The same components as those in FIG. A plurality of gold bumps 6 are formed on the lower surface of the semiconductor chip 1, and electrode pads 4 are formed on the wiring board 2 corresponding to the gold bumps 6.

【0011】図10(a)に示すように、まず、配線基
板2の半導体チップ実装部位に熱硬化性樹脂からなる絶
縁性接着剤7を供給する。次に、同図(b)に示すよう
に、半導体チップ1をフェースダウンさせ、金バンプ6
を配線基板2の電極パッド4に位置決めする。
As shown in FIG. 10A, first, an insulating adhesive 7 made of a thermosetting resin is supplied to a semiconductor chip mounting portion of the wiring board 2. Next, as shown in FIG. 2B, the semiconductor chip 1 is face down and the gold bumps 6 are formed.
Are positioned on the electrode pads 4 of the wiring board 2.

【0012】次に、同図(c)に示すように、半導体チ
ップ1を裏面側から矢印F方向に加圧し、半導体チップ
1および金バンプ6によって絶縁性接着剤7を押し退け
て金バンプ6を電極パッド4に接触させる。次に、絶縁
性接着剤7を120〜160℃程度に加熱させると、半
導体チップ1と配線基板2との間および半導体チップ1
の周辺の絶縁性接着剤7が硬化される。
Next, as shown in FIG. 1C, the semiconductor chip 1 is pressed from the back side in the direction of arrow F, and the insulating adhesive 7 is pushed away by the semiconductor chip 1 and the gold bump 6 to remove the gold bump 6. It is brought into contact with the electrode pad 4. Next, when the insulating adhesive 7 is heated to about 120 to 160 ° C., the space between the semiconductor chip 1 and the wiring board 2 and the semiconductor chip 1
Is hardened.

【0013】図11は従来の突起電極を持った半導体チ
ップの実装方法を示し、図9および図10と同一構成部
分には同一番号を付して説明を省略する。半導体チップ
1の下面には金、はんだ等の複数の突起電極8が形成さ
れ、配線基板2には前記突起電極8に対応して電極パッ
ド4が形成されている。
FIG. 11 shows a conventional mounting method of a semiconductor chip having bump electrodes, and the same components as those in FIGS. 9 and 10 are denoted by the same reference numerals and description thereof is omitted. A plurality of projecting electrodes 8 such as gold and solder are formed on the lower surface of the semiconductor chip 1, and electrode pads 4 are formed on the wiring board 2 corresponding to the projecting electrodes 8.

【0014】図11(a)に示すように、半導体チップ
1の突起電極8の先端に導電性接着剤9を転写し、半導
体チップ1をフェースダウンさせ、突起電極8を配線基
板2の電極パッド4に位置決めした後、導電性接着剤9
を加熱して接続する。なお、この段階で半導体チップ1
の実装不良が検出された場合には新たな半導体チップ1
に交換(リペア)することができる。
As shown in FIG. 11A, a conductive adhesive 9 is transferred to the tip of the protruding electrode 8 of the semiconductor chip 1, the semiconductor chip 1 is face-down, and the protruding electrode 8 is connected to the electrode pad of the wiring board 2. 4 and then the conductive adhesive 9
Heat and connect. At this stage, the semiconductor chip 1
If a mounting failure is detected, a new semiconductor chip 1
Can be replaced (repaired).

【0015】次に、同図(b)に示すように、シリンジ
5aを用いディスペンス法によって液状のエポキシ樹脂
等の熱硬化性樹脂からなる封止樹脂5を半導体チップ1
の周辺の配線基板2に塗布すると、封止樹脂5は毛細管
現象によって電極パッド4の間を通って半導体チップ1
と配線基板2との間隙(50μm程度)に充填される。
Next, as shown in FIG. 1B, a sealing resin 5 made of a thermosetting resin such as a liquid epoxy resin is applied to the semiconductor chip 1 by a dispensing method using a syringe 5a.
Is applied to the wiring substrate 2 around the semiconductor chip 1, the sealing resin 5 passes through the space between the electrode pads 4 by capillary action.
Is filled in the gap (about 50 μm) between the substrate and the wiring board 2.

【0016】次に、封止樹脂5を120〜160℃程度
に加熱させると、同図(c)に示すように、半導体チッ
プ1と配線基板2との間および半導体チップ1の周辺の
封止樹脂5が硬化される。
Next, when the sealing resin 5 is heated to about 120 to 160 ° C., the sealing between the semiconductor chip 1 and the wiring board 2 and the periphery of the semiconductor chip 1 is performed as shown in FIG. The resin 5 is cured.

【0017】図12は従来の突起電極を持った半導体チ
ップの実装方法を示し、図9〜図11と同一構成部分に
は同一番号を付して説明を省略する。半導体チップ1の
下面には金、はんだ等の複数の突起電極8が形成され、
配線基板2には前記突起電極8に対応して電極パッド4
が形成されている。
FIG. 12 shows a conventional mounting method of a semiconductor chip having a protruding electrode. The same components as those in FIGS. 9 to 11 are denoted by the same reference numerals and description thereof is omitted. On the lower surface of the semiconductor chip 1, a plurality of projecting electrodes 8 such as gold and solder are formed.
The wiring board 2 has electrode pads 4 corresponding to the protruding electrodes 8.
Are formed.

【0018】図12(a)に示すように、まず、配線基
板2の半導体チップ1が搭載される領域にシリンジ5a
を用いディスペンス法により絶縁性接着剤7を塗布す
る。次に、同図(b)に示すように、半導体チップ1の
突起電極8の先端に導電性接着剤9を転写し、半導体チ
ップ1をフェースダウンさせ、突起電極8を配線基板2
の電極パッド4に位置決めする。
As shown in FIG. 12A, a syringe 5a is first placed in a region of the wiring board 2 where the semiconductor chip 1 is to be mounted.
Is used to apply the insulating adhesive 7 by a dispensing method. Next, as shown in FIG. 2B, the conductive adhesive 9 is transferred to the tip of the protruding electrode 8 of the semiconductor chip 1, the semiconductor chip 1 is face-down, and the protruding electrode 8 is
Is positioned on the electrode pad 4.

【0019】次に、同図(c)に示すように、半導体チ
ップ1を配線基板2に搭載し、半導体チップ1の突起電
極8を電極パッド4に対して加圧しながら、絶縁性接着
剤7を150〜160℃程度に加熱させると、絶縁性接
着剤7と導電性接着剤9とが同時に硬化される。
Next, as shown in FIG. 1C, the semiconductor chip 1 is mounted on the wiring board 2 and the insulating adhesive 7 is pressed while pressing the protruding electrodes 8 of the semiconductor chip 1 against the electrode pads 4. Is heated to about 150 to 160 ° C., the insulating adhesive 7 and the conductive adhesive 9 are simultaneously cured.

【0020】[0020]

【発明が解決しようとする課題】しかしながら、図9に
示す実装方法は、半導体チップ1と配線基板2との僅か
な間隙に毛細管現象を利用して封止樹脂5を注入させる
ため、封止樹脂5の粘度を低下させる必要があるにも拘
らず、無機フィラーの含有量を多くすることにより封止
樹脂5の粘度が増加するため、半導体チップ1と配線基
板2との間隙への封止樹脂5の注入性が悪くなる。
However, according to the mounting method shown in FIG. 9, the sealing resin 5 is injected into the small gap between the semiconductor chip 1 and the wiring board 2 by utilizing the capillary phenomenon. Although the viscosity of the sealing resin 5 is increased by increasing the content of the inorganic filler, it is necessary to reduce the viscosity of the sealing resin 5 in the gap between the semiconductor chip 1 and the wiring board 2. The injection property of No. 5 becomes worse.

【0021】このため、無機フィラーの形状やサイズを
適正化するとともに、配線基板2や封止樹脂5を塗布す
る際に使用するシリンジ5aを40〜90℃に加熱して
封止樹脂5の粘度を低下させるなどの施策が行われてい
るが、なお樹脂注入時間が長く作業性が悪いという問題
があった。
For this reason, the shape and size of the inorganic filler are optimized, and the viscosity of the sealing resin 5 is increased by heating the syringe 5a used for applying the wiring substrate 2 and the sealing resin 5 to 40 to 90 ° C. However, there is a problem that the resin injection time is long and the workability is poor.

【0022】また、半導体チップ1と配線基板2との間
隙は30〜60μm程度と狭く、半導体チップ1の周辺
に配置したはんだバンプ3が100μm以下のピッチで
形成された場合、隣接するはんだバンプ3の間隙が30
μm以下と狭くなり、その間隙を通過して半導体チップ
1の中央部に封止樹脂5が充填する前に、半導体チップ
1の周辺のはんだバンプ3に沿って封止樹脂5が流れて
半導体チップ1の中央部にボイドが生じることにより、
信頼性の低下を招くという問題もある。
The gap between the semiconductor chip 1 and the wiring board 2 is as small as about 30 to 60 μm. When the solder bumps 3 arranged around the semiconductor chip 1 are formed at a pitch of 100 μm or less, the adjacent solder bumps 3 Gap of 30
μm or less, the sealing resin 5 flows along the solder bumps 3 around the semiconductor chip 1 before the sealing resin 5 fills the center of the semiconductor chip 1 through the gap. By creating a void in the center of 1
There is also a problem that reliability is reduced.

【0023】また、図10の実装方法は、エポキシ樹脂
などの熱硬化性の絶縁性接着剤7を用いて半導体チップ
1を配線基板2に強固に接合しているために、実装後に
半導体チップ1が不良と判明したり接続の不良が生じた
場合に、半導体チップ1を取り外して新たな半導体チッ
プ1と交換(リペア)が困難であった。
In the mounting method shown in FIG. 10, the semiconductor chip 1 is firmly bonded to the wiring board 2 by using a thermosetting insulating adhesive 7 such as an epoxy resin. In the case where the semiconductor chip 1 is found to be defective or the connection is defective, it has been difficult to remove the semiconductor chip 1 and replace it with a new semiconductor chip 1 (repair).

【0024】このため、例えばエポキシ樹脂の中に銀粉
を混入した導電性接着剤を用いて突起電極を配線基板の
電極パッドと接続し、この状態で半導体チップ1や実装
の検査を行い、不良と判った場合にはリペアを行った
後、半導体チップ1と配線基板2との間隙に毛細管現象
を利用して絶縁性樹脂を充填して封止を行う方法が採用
されている。しかし、半導体チップ1と配線基板2との
狭い間隙(30〜60μm程度)に毛細管現象を利用し
て粘度の高い絶縁性樹脂を充填させなければならず、作
業性が悪いという問題があった。
For this reason, the protruding electrodes are connected to the electrode pads of the wiring board by using, for example, a conductive adhesive in which silver powder is mixed in an epoxy resin. If it is found, a method is employed in which after repairing, a gap between the semiconductor chip 1 and the wiring board 2 is filled with an insulating resin by utilizing a capillary phenomenon and sealed. However, a narrow gap (about 30 to 60 μm) between the semiconductor chip 1 and the wiring board 2 has to be filled with an insulating resin having a high viscosity by utilizing a capillary phenomenon, and there is a problem that workability is poor.

【0025】また、図11の実装方法は、半導体チップ
1と配線基板2との僅かな間隙(30〜60μm程度)
に封止樹脂5の注入を行うため、封止樹脂5の粘度をで
きるだけ低下させる必要があるにも拘らず、封止樹脂5
の成分中に主として熱膨張係数を低下させる目的により
固形分である無機フィラー(粒径:1〜12μm程度、
含有量:40〜70wt%程度)を含有しているため、
封止樹脂5の粘度を低下させることには限界があり、半
導体チップ1と配線基板2との間隙への封止樹脂5の注
入性が悪いという問題があった。
In the mounting method shown in FIG. 11, a slight gap (about 30 to 60 μm) between the semiconductor chip 1 and the wiring board 2 is used.
Although the viscosity of the sealing resin 5 needs to be reduced as much as possible, the sealing resin 5
Inorganic filler (particle size: about 1 to 12 μm) which is a solid component mainly for the purpose of lowering the coefficient of thermal expansion
Content: about 40-70 wt%)
There is a limit in reducing the viscosity of the sealing resin 5, and there is a problem that the injection property of the sealing resin 5 into the gap between the semiconductor chip 1 and the wiring board 2 is poor.

【0026】さらに、図12の実装方法は、半導体チッ
プ1を配線基板2に搭載する際に、配線基板2に塗布し
た絶縁性接着剤7が半導体チップ1の周辺に形成された
突起電極8の外側へ押し出される際に、突起電極8の先
端に付着した導電性接着剤9が絶縁性接着剤7と共に押
し流されるという問題があった。
Further, according to the mounting method of FIG. 12, when the semiconductor chip 1 is mounted on the wiring board 2, the insulating adhesive 7 applied to the wiring board 2 is applied to the bump electrodes 8 formed around the semiconductor chip 1. When pushed out, there is a problem that the conductive adhesive 9 attached to the tip of the protruding electrode 8 is washed away together with the insulating adhesive 7.

【0027】この発明は、前記事情に着目してなされた
もので、第1の目的は、半導体チップと配線基板との僅
かな間隙にボイドを残さず、かつ封止樹脂の注入性が向
上し、実装作業性の向上を図ることができる狭い接続ピ
ッチに対応した半導体実装方法およびその実装構造を提
供することにある。
The present invention has been made in view of the above circumstances, and a first object of the present invention is to improve the injection property of a sealing resin without leaving a void in a slight gap between a semiconductor chip and a wiring board. Another object of the present invention is to provide a semiconductor mounting method and a mounting structure corresponding to a narrow connection pitch capable of improving mounting workability.

【0028】第2の目的は、半導体チップを配線基板に
対して容易に実装できるとともに、リペアが簡単に行え
信頼性の向上を図ることができる半導体実装方法および
その実装構造を提供することにある。
A second object of the present invention is to provide a semiconductor mounting method and a mounting structure thereof, in which a semiconductor chip can be easily mounted on a wiring board, repair can be easily performed, and reliability can be improved. .

【0029】[0029]

【課題を解決するための手段】この発明は、前記目的を
達成するために、請求項1は、半導体チップをフェース
ダウンで配線基板に実装する半導体実装方法において、
前記配線基板上の半導体チップ実装部位に絶縁性の無機
フィラーを供給する工程と、前記配線基板上の前記無機
フィラーが供給された半導体チップ実装部位に半導体チ
ップをフェースダウンで搭載する工程と、前記搭載され
た半導体チップと前記配線基板との間隙に封止樹脂を充
填する工程と、前記充填された封止樹脂を加熱硬化する
工程とを具備することを特徴とする半導体実装方法。
In order to achieve the above object, the present invention provides a semiconductor mounting method for mounting a semiconductor chip face down on a wiring board.
Supplying an insulating inorganic filler to the semiconductor chip mounting site on the wiring board, and mounting the semiconductor chip face down on the semiconductor chip mounting site where the inorganic filler is supplied on the wiring board; A semiconductor mounting method, comprising: a step of filling a gap between a mounted semiconductor chip and the wiring board with a sealing resin; and a step of heating and curing the filled sealing resin.

【0030】請求項2は、請求項1において、成分中に
無機フィラーと結合するカップリング剤が含有されてい
る封止樹脂を充填することを特徴とする。請求項3は、
請求項1において、封止樹脂を加熱硬化する工程は、配
線基板を反転して半導体チップを前記配線基板の下側に
した後、前記封止樹脂を加熱硬化させることを特徴とす
る。
A second aspect of the present invention is characterized in that, in the first aspect, a sealing resin containing a coupling agent that binds to an inorganic filler is contained in a component. Claim 3
In the first aspect, the step of heating and curing the sealing resin is characterized in that the wiring resin is turned over, the semiconductor chip is placed below the wiring substrate, and then the sealing resin is heated and cured.

【0031】請求項4は、請求項1において、配線基板
は、半導体チップ実装部位に無機フィラーを貯留する凹
部が形成されていることを特徴とする。請求項5は、突
起電極を有する半導体チップをフェースダウンで電極パ
ッドを有する配線基板に実装する半導体実装方法におい
て、前記半導体チップの突起電極形成面の突起電極を除
く素子面、前記配線基板の半導体チップ実装部位の少な
くとも一方に熱可塑性を呈する絶縁性接着剤を供給する
第1の工程と、前記絶縁性接着剤が供給されたのに基づ
き前記配線基板上の半導体チップ実装部位に前記半導体
チップをフェースダウンで載置する第2の工程と、前記
半導体チップの突起電極が形成されていない裏面側から
ボンディングヘッドにより加熱しながら加圧して前記突
起電極を前記電極パッドに押圧し、前記電極パッドを前
記配線基板に押し込ませる第3の工程と、前記半導体チ
ップと前記配線基板との間に介在している前記絶縁性接
着剤を硬化する第4の工程とを具備することを特徴とす
る半導体実装方法。
According to a fourth aspect of the present invention, in the first aspect, the wiring board is formed with a concave portion for storing an inorganic filler in a semiconductor chip mounting portion. 6. A semiconductor mounting method for mounting a semiconductor chip having a protruding electrode face down on a wiring board having an electrode pad, wherein the semiconductor chip of the wiring board has a device surface excluding a protruding electrode on a protruding electrode forming surface of the semiconductor chip. A first step of supplying an insulative adhesive exhibiting thermoplasticity to at least one of the chip mounting parts, and applying the semiconductor chip to the semiconductor chip mounting part on the wiring board based on the supply of the insulative adhesive. A second step of mounting the semiconductor chip face-down, and pressing the projecting electrode against the electrode pad by applying pressure while heating with a bonding head from the back side of the semiconductor chip where the projecting electrode is not formed; A third step of being pushed into the wiring board; and the insulating bonding interposed between the semiconductor chip and the wiring board. Semiconductor mounting method characterized by comprising a fourth step of curing the.

【0032】請求項6は、請求項5において、第3の工
程は、少なくとも電極パッドを有する面がガラスエポキ
シ樹脂層で形成された配線基板をガラス転移点以上の温
度で加熱しながら加圧して突起電極を前記電極パッドに
押圧し、前記電極パッドを前記配線基板に押し込ませる
ことを特徴とする。
In a sixth aspect of the present invention, in the third step, the wiring board having at least the surface having the electrode pads formed of the glass epoxy resin layer is pressurized while being heated at a temperature equal to or higher than the glass transition point. A projection electrode is pressed against the electrode pad, and the electrode pad is pressed into the wiring board.

【0033】請求項7は、請求項5において、第1の工
程は、フィルム状あるいはペースト状の絶縁性接着剤を
突起電極形成面の突起電極を除く半導体チップの素子
面、配線基板の前記半導体チップ実装部位の少なくとも
一方に供給した後、前記絶縁性接着剤中に存在する溶剤
を揮発させる工程を有することを特徴とする。
According to a seventh aspect of the present invention, in the first step, the first step comprises applying a film-like or paste-like insulating adhesive to the element surface of the semiconductor chip except for the protruding electrodes on the protruding electrode forming surface and the semiconductor of the wiring board. After supplying to at least one of the chip mounting portions, a step of volatilizing a solvent present in the insulating adhesive is provided.

【0034】請求項8は、突起電極を有する半導体チッ
プをフェースダウンで電極パッドを有する配線基板に実
装する半導体実装構造において、前記突起電極を介して
前記半導体チップが前記電極パッドと接続されると共
に、この電極パッドの接続面が配線基板の板面より低く
押し込まれた状態で、前記半導体チップの素子面および
前記配線基板の半導体チップ実装面が熱可塑性を呈する
絶縁性接着剤によって封止されていることを特徴とす
る。
In a semiconductor mounting structure for mounting a semiconductor chip having a protruding electrode face down on a wiring board having an electrode pad, the semiconductor chip is connected to the electrode pad via the protruding electrode. In a state where the connection surface of the electrode pad is pressed down below the plate surface of the wiring board, the element surface of the semiconductor chip and the semiconductor chip mounting surface of the wiring substrate are sealed with an insulating adhesive exhibiting thermoplasticity. It is characterized by being.

【0035】請求項9は、請求項8において、半導体チ
ップと配線基板の電気的接続部は、前記半導体チップの
前記配線基板への実装工程中の最も高い加熱温度よりも
融点が高い金属材料からなることを特徴とする。
According to a ninth aspect, in the eighth aspect, the electrical connection portion between the semiconductor chip and the wiring board is made of a metal material having a melting point higher than the highest heating temperature during the step of mounting the semiconductor chip on the wiring board. It is characterized by becoming.

【0036】請求項10は、半導体チップがフェースダ
ウンで配線基板に実装された半導体実装構造において、
前記配線基板の前記半導体チップにより覆われる部位と
この覆われた部位の外側とを結ぶ凹溝を有した配線基板
と、この配線基板の半導体チップ実装部位に実装された
半導体チップと、前記凹溝を介して前記半導体チップ実
装部位に充填され前記半導体チップと配線基板との間を
封止する絶縁性樹脂とを具備したことを特徴とする。
According to a tenth aspect, in the semiconductor mounting structure in which the semiconductor chip is mounted face down on the wiring board,
A wiring board having a groove connecting a part of the wiring board covered by the semiconductor chip and an outside of the covered part; a semiconductor chip mounted on a semiconductor chip mounting part of the wiring board; And an insulating resin that fills the semiconductor chip mounting site via the substrate and seals the space between the semiconductor chip and the wiring board.

【0037】請求項11は、半導体チップをフェースダ
ウンで配線基板に実装する半導体実装方法において、前
記配線基板の前記半導体チップにより覆われる部位とこ
の覆われた部位の外側とを結ぶ凹溝を有した配線基板の
前記半導体チップ実装部位に前記半導体チップをフェー
スダウンで実装した後、前記凹溝の前記半導体チップ実
装部位より外側から絶縁性樹脂を供給し、前記凹溝を介
して前記半導体チップと前記配線基板との間に絶縁性樹
脂を供給して前記半導体チップと前記配線基板とを封止
することを特徴とする。
According to another aspect of the present invention, there is provided a semiconductor mounting method for mounting a semiconductor chip on a wiring board face-down, comprising a concave groove connecting a portion of the wiring board covered by the semiconductor chip and an outside of the covered portion. After the semiconductor chip is mounted face-down on the semiconductor chip mounting portion of the wiring board, an insulating resin is supplied from outside the semiconductor chip mounting portion of the concave groove, and the semiconductor chip is connected to the semiconductor chip via the concave groove. An insulating resin is supplied between the wiring board and the semiconductor chip to seal the semiconductor chip and the wiring board.

【0038】請求項12は、突起電極を有する半導体チ
ップをフェースダウンで配線基板に実装する半導体実装
方法において、前記半導体チップの前記突起電極の少な
くとも先端に導電性接着剤を付着する工程と、前記半導
体チップの前記突起電極が存在しない領域に絶縁性樹脂
を供給する工程と、導電性接着剤および絶縁性樹脂が供
給された前記半導体チップをフェースダウンで前記突起
電極を前記配線基板の電極パッドに位置決めした後、前
記半導体チップを配線基板に搭載する工程と、前記半導
体チップを配線基板に搭載したのに基づき前記導電性接
着剤および絶縁性樹脂を加熱硬化する工程とを具備する
ことを特徴とする。
According to a twelfth aspect of the present invention, in the semiconductor mounting method for mounting a semiconductor chip having a projecting electrode face down on a wiring board, a step of attaching a conductive adhesive to at least a tip of the projecting electrode of the semiconductor chip; A step of supplying an insulating resin to a region of the semiconductor chip where the protruding electrodes are not present; and a step of applying the protruding electrodes to the electrode pads of the wiring board face down with the semiconductor chip supplied with the conductive adhesive and the insulating resin. After the positioning, the method includes a step of mounting the semiconductor chip on a wiring board, and a step of heating and curing the conductive adhesive and the insulating resin based on the mounting of the semiconductor chip on the wiring board. I do.

【0039】請求項13は、請求項12において、前記
半導体チップの突起電極の少なくとも先端に導電性接着
剤を付着する工程は、半導体チップの突起電極が存在し
ない領域に絶縁性樹脂を供給した後、加熱して前記絶縁
性樹脂の粘度を低下させ、前記突起電極を除く前記半導
体チップの全域に前記絶縁性樹脂を拡散させることを特
徴とする。
According to a thirteenth aspect, in the twelfth aspect, the step of attaching a conductive adhesive to at least the tip of the protruding electrode of the semiconductor chip is performed after the insulating resin is supplied to a region of the semiconductor chip where no protruding electrode exists. Heating the insulating resin to lower the viscosity of the insulating resin, and diffusing the insulating resin throughout the semiconductor chip except for the protruding electrodes.

【0040】[0040]

【発明の実施の形態】以下、この発明の実施の形態を図
面に基づいて説明する。図1および図2の第1の実施形
態を示し、図1は半導体実装工程を示し、図2は半導体
実装構造を示す。
Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B show a first embodiment of FIGS. 1 and 2, FIG. 1 shows a semiconductor mounting process, and FIG. 2 shows a semiconductor mounting structure.

【0041】図1に基づいて半導体実装方法を説明す
る。図中10は半導体チップであり、11は配線基板で
ある。半導体チップ10にははんだバンプ13が設けら
れ、配線基板11上にははんだバンプ13の配置に対応
して電極パッド14が形成されている。
The semiconductor mounting method will be described with reference to FIG. In the figure, 10 is a semiconductor chip, and 11 is a wiring board. Solder bumps 13 are provided on the semiconductor chip 10, and electrode pads 14 are formed on the wiring board 11 corresponding to the arrangement of the solder bumps 13.

【0042】15は半導体チップ10と配線基板11と
の間隙に供給する無機フィラー16の供給治具であり、
逆漏斗状の貯留部17の下端開口にはゲート18が設け
られている。
Reference numeral 15 denotes a jig for supplying an inorganic filler 16 for supplying a gap between the semiconductor chip 10 and the wiring board 11.
A gate 18 is provided at the lower end opening of the inverted funnel-shaped storage unit 17.

【0043】まず、図1(a)に示すように、供給治具
15の貯留部17には半導体チップ10と配線基板11
との間隙に供給するに必要な適量の無機フィラー16が
貯留された供給治具15の下端開口を配線基板11の半
導体チップ実装部位(電極パッド14によって囲まれた
領域)に位置決めする。
First, as shown in FIG. 1A, a semiconductor chip 10 and a wiring board 11 are stored in a storage portion 17 of a supply jig 15.
An opening at the lower end of the supply jig 15 in which an appropriate amount of the inorganic filler 16 necessary for supply to the gap is stored is positioned at a semiconductor chip mounting portion of the wiring board 11 (a region surrounded by the electrode pads 14).

【0044】次に、同図(b)に示すように、供給治具
15のゲート18を開放すると、無機フィラー16は配
線基板11の半導体チップ実装部位に供給される。そし
て、同図(c)に示すように、無機フィラー16が配線
基板11の半導体チップ実装部位の全体に亘って略均等
に広がる。
Next, as shown in FIG. 2B, when the gate 18 of the supply jig 15 is opened, the inorganic filler 16 is supplied to the semiconductor chip mounting portion of the wiring board 11. Then, as shown in FIG. 3C, the inorganic filler 16 spreads substantially uniformly over the entire semiconductor chip mounting portion of the wiring board 11.

【0045】ここで、無機フィラー16は、例えばシリ
カ(Si O2)を使用しているが、絶縁性のものであれば
他のものでも良い。無機フィラー16の表面および樹脂
成分とを結合するカップリング剤を予め樹脂に添加して
おくか、無機フィラー16にカップリング剤を形成する
処理を施すことにより、無機フィラー16と樹脂成分と
の濡れ性が良くなり、無機フィラーと樹脂との界面にお
けるボイドが少なくなる。また、カップリング剤を添加
することにより、例えば、樹脂硬化物のガラス転移温度
(例えばTg=140℃)が高温側にシフトするため、
使用温度範囲が広くなり、弾性率などの機械的特性を向
上するため信頼性が高くなる。
Here, for example, silica (SiO 2) is used as the inorganic filler 16, but other inorganic fillers may be used. A coupling agent that binds to the surface of the inorganic filler 16 and the resin component is added to the resin in advance, or the inorganic filler 16 is treated to form a coupling agent, so that the inorganic filler 16 and the resin component are wetted. And the voids at the interface between the inorganic filler and the resin are reduced. Further, by adding a coupling agent, for example, the glass transition temperature (for example, Tg = 140 ° C.) of the cured resin shifts to a higher temperature side.
The operating temperature range is widened, and the mechanical properties such as the elastic modulus are improved, so that the reliability is increased.

【0046】次に、同図(d)に示すように、半導体チ
ップ10をフェースダウンさせ、はんだバンプ13を配
線基板11の電極パッド14に位置決めし、配線基板1
1に半導体チップ10を搭載し、加熱によってはんだバ
ンプ13を溶融して電極パッド14に接続する。なお、
この段階で半導体チップ10の実装不良が検出された場
合には新たな半導体チップ10に交換(リペア)するこ
とができる。また、半導体チップ10や配線基板11に
はんだバンプ13を介さずに、例えば金バンプに導電接
着剤を塗布して半導体チップ10と配線基板11の電極
同士を接続することも可能である。
Next, as shown in FIG. 2D, the semiconductor chip 10 is face down, the solder bumps 13 are positioned on the electrode pads 14 of the wiring board 11, and
1, the semiconductor chip 10 is mounted, and the solder bumps 13 are melted by heating and connected to the electrode pads 14. In addition,
At this stage, if a mounting failure of the semiconductor chip 10 is detected, the semiconductor chip 10 can be replaced (repaired) with a new semiconductor chip 10. Further, it is also possible to connect the electrodes of the semiconductor chip 10 and the wiring board 11 by applying a conductive adhesive to, for example, gold bumps without interposing the solder bumps 13 on the semiconductor chip 10 and the wiring board 11.

【0047】次に、同図(e)に示すように、ディスペ
ンス法によって液状のエポキシ樹脂等の熱硬化性樹脂か
らなる封止樹脂19を半導体チップ10の周辺の配線基
板11に塗布すると、封止樹脂19は毛細管現象によっ
て電極パッド14の間を通って半導体チップ10と配線
基板11との間隙(50μm程度)に充填される。そし
て、同図(f)に示すように、予め供給された無機フィ
ラー16の上層に封止樹脂19が充填される。ここで、
封止樹脂19に対する無機フィラー16の比率は、0.
7〜2.5倍(wt)である。
Next, as shown in FIG. 2E, a sealing resin 19 made of a thermosetting resin such as a liquid epoxy resin is applied to the wiring substrate 11 around the semiconductor chip 10 by a dispensing method. The stopper resin 19 fills the gap (about 50 μm) between the semiconductor chip 10 and the wiring board 11 through the space between the electrode pads 14 by a capillary phenomenon. Then, as shown in FIG. 3F, the sealing resin 19 is filled in the upper layer of the inorganic filler 16 supplied in advance. here,
The ratio of the inorganic filler 16 to the sealing resin 19 is set to 0.1.
It is 7 to 2.5 times (wt).

【0048】次に、同図(g)に示すように、配線基板
11を反転させると、配線基板11の下側に半導体チッ
プ10が位置する。そして、封止樹脂19を50〜80
℃程度に加熱して封止樹脂19の粘度を低下させること
により、無機フィラー16が自重によって沈降し始め、
封止樹脂19中に無機フィラー16が分散させる。さら
に、封止樹脂19を150゜程度に加熱すると、半導体
チップ10と配線基板11との間および半導体チップ1
0の周辺の封止樹脂19が硬化し、図2に示すような半
導体実装構造が得られる。
Next, as shown in FIG. 2G, when the wiring board 11 is inverted, the semiconductor chip 10 is located below the wiring board 11. Then, the sealing resin 19 is set to 50 to 80.
By heating to about ° C. to lower the viscosity of the sealing resin 19, the inorganic filler 16 starts to settle by its own weight,
The inorganic filler 16 is dispersed in the sealing resin 19. Further, when the sealing resin 19 is heated to about 150 °, the space between the semiconductor chip 10 and the wiring substrate 11 and the semiconductor chip 1 are reduced.
The hardening resin 19 around the periphery of the hard disk is hardened, and a semiconductor mounting structure as shown in FIG. 2 is obtained.

【0049】このように第1の実施形態によれば、半導
体チップ10と配線基板11との間隙に予め無機フィラ
ー16を供給し、ついで半導体チップ10と配線基板1
1との間隙に封止樹脂19を注入することにより、封止
樹脂19に無機フィラー16を多く含有させる必要がな
く、封止樹脂19の粘度が高くならないため、流動性が
維持され、半導体チップ10と配線基板11との狭い間
隙にスムーズに注入され、作業性の向上を図ることがで
きる。
As described above, according to the first embodiment, the inorganic filler 16 is supplied to the gap between the semiconductor chip 10 and the wiring board 11 in advance, and then the semiconductor chip 10 and the wiring board 1
By injecting the sealing resin 19 into the gap between the semiconductor chip 1 and the sealing resin 19, there is no need to include a large amount of the inorganic filler 16, and the viscosity of the sealing resin 19 does not increase. It can be smoothly injected into a narrow gap between the wiring board 10 and the wiring board 11, and the workability can be improved.

【0050】図3は第2の実施形態を示し、第1の実施
形態と同一構成部分には同一番号を付して説明を省略す
る。本実施形態の配線基板11の半導体チップ実装部位
(電極パッド14によって囲まれた領域)には無機フィ
ラー16を貯留するための凹部11aが形成されてい
る。20は半導体チップ10と配線基板11との間隙に
供給する無機フィラー16の吸着ヘッドであり、下向き
に開口する凹陥部21が設けられ、この凹陥部21には
無機フィラー16の粒径より細かいメッシュの網体22
が張設されている。吸着ヘッド20は真空吸引源(図示
しない)に接続され、凹陥部21を真空にすることによ
り、網体22に無機フィラー16が吸着保持されるよう
になっている。
FIG. 3 shows a second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. A concave portion 11a for storing the inorganic filler 16 is formed in the semiconductor chip mounting portion (the region surrounded by the electrode pad 14) of the wiring board 11 of the present embodiment. Reference numeral 20 denotes a suction head for the inorganic filler 16 to be supplied to the gap between the semiconductor chip 10 and the wiring board 11, provided with a concave portion 21 which opens downward, and the concave portion 21 has a mesh finer than the inorganic filler 16 in particle size. Net 22
Is stretched. The suction head 20 is connected to a vacuum suction source (not shown), and the concave portion 21 is evacuated so that the inorganic filler 16 is suction-held by the mesh body 22.

【0051】まず、図3(a)に示すように、吸着ヘッ
ド20の凹陥部21を真空にして網体22に半導体チッ
プ10と配線基板11との間隙に供給するに必要な適量
の無機フィラー16を吸着保持し、吸着ヘッド20の下
端開口を配線基板11の凹部11aに位置決めする。
First, as shown in FIG. 3A, an appropriate amount of inorganic filler necessary for supplying the mesh 22 with a gap between the semiconductor chip 10 and the wiring board 11 by evacuating the concave portion 21 of the suction head 20. 16 is held by suction, and the lower end opening of the suction head 20 is positioned in the concave portion 11 a of the wiring board 11.

【0052】次に、同図(b)に示すように、吸着ヘッ
ド20の真空吸引を解除すると、凹陥部21が大気圧と
なり、網体22に吸着されていた無機フィラー16は配
線基板11の凹部11aに供給される。そして、無機フ
ィラー16が配線基板11の凹部11aの全体に亘って
略均等に広がる。
Next, as shown in FIG. 5B, when the vacuum suction of the suction head 20 is released, the depression 21 becomes atmospheric pressure, and the inorganic filler 16 adsorbed by the net 22 is removed from the wiring board 11. It is supplied to the recess 11a. Then, the inorganic filler 16 spreads substantially uniformly over the entire recess 11 a of the wiring board 11.

【0053】次に、同図(c)に示すように、半導体チ
ップ10をフェースダウンさせ、はんだバンプ13を配
線基板11の電極パッド14に位置決めし、配線基板1
1に半導体チップ10を搭載し、加熱によってはんだバ
ンプ13を溶融して電極パッド14に接続する。なお、
この段階で半導体チップ10の実装不良が検出された場
合には新たな半導体チップ10に交換(リペア)するこ
とができる。また、半導体チップ10や配線基板11に
はんだバンプ13を介さずに直接に導電接着剤を塗布し
て半導体チップ10と配線基板11の電極同士を接続す
ることも可能である。
Next, as shown in FIG. 3C, the semiconductor chip 10 is face down, the solder bumps 13 are positioned on the electrode pads 14 of the wiring board 11, and
1, the semiconductor chip 10 is mounted, and the solder bumps 13 are melted by heating and connected to the electrode pads 14. In addition,
At this stage, if a mounting failure of the semiconductor chip 10 is detected, the semiconductor chip 10 can be replaced (repaired) with a new semiconductor chip 10. It is also possible to apply a conductive adhesive directly to the semiconductor chip 10 and the wiring board 11 without the intervention of the solder bumps 13 to connect the electrodes of the semiconductor chip 10 and the wiring board 11 to each other.

【0054】次に、同図(d)に示すように、ディスペ
ンス法によって液状のエポキシ樹脂等の熱硬化性樹脂か
らなる封止樹脂19を半導体チップ10の周辺の配線基
板11に塗布すると、封止樹脂19は毛細管現象によっ
て電極パッド14の間を通って半導体チップ10と配線
基板11との間隙および凹部11aに充填される。そし
て、予め供給された無機フィラー16の上層に封止樹脂
19が充填される。
Next, as shown in FIG. 2D, when a sealing resin 19 made of a thermosetting resin such as a liquid epoxy resin is applied to the wiring substrate 11 around the semiconductor chip 10 by a dispensing method, the sealing is performed. The sealing resin 19 passes between the electrode pads 14 and fills the gap between the semiconductor chip 10 and the wiring board 11 and the concave portion 11a by capillary action. Then, the sealing resin 19 is filled in the upper layer of the inorganic filler 16 supplied in advance.

【0055】次に、同図(e)に示すように、配線基板
11を反転させると、配線基板11の下側に半導体チッ
プ10が位置する。そして、封止樹脂19を50〜80
℃程度に加熱して封止樹脂19の粘度を低下させること
により、無機フィラー16が自重によって沈降し始め、
封止樹脂19中に無機フィラー16が分散する。さら
に、封止樹脂19を150℃程度に加熱すると、半導体
チップ10と配線基板11との間および半導体チップ1
0の周辺の封止樹脂19が硬化して半導体実装構造が得
られる。
Next, as shown in FIG. 5E, when the wiring board 11 is turned over, the semiconductor chip 10 is located below the wiring board 11. Then, the sealing resin 19 is set to 50 to 80.
By heating to about ° C. to lower the viscosity of the sealing resin 19, the inorganic filler 16 starts to settle by its own weight,
The inorganic filler 16 is dispersed in the sealing resin 19. Further, when the sealing resin 19 is heated to about 150 ° C., the space between the semiconductor chip 10 and the wiring board 11 and the semiconductor chip 1 are reduced.
The sealing resin 19 around 0 is cured, and a semiconductor mounting structure is obtained.

【0056】このように第2の実施形態によれば、配線
基板11に凹部11aを設けることにより、半導体チッ
プ10と配線基板11との間隙が大きくなり、毛細管現
象を利用した封止樹脂19の注入性を高めることができ
る。また、凹部11aに無機フィラー16が収容され、
無機フィラー16が周辺の電極パッド14に被さること
によって生じる接続不良を防止でき、半導体チップ10
を配線基板11に確実に接続でき、信頼性を向上でき
る。
As described above, according to the second embodiment, by providing the concave portion 11a in the wiring substrate 11, the gap between the semiconductor chip 10 and the wiring substrate 11 is increased, and the sealing resin 19 utilizing the capillary phenomenon is formed. Injectability can be improved. Further, the inorganic filler 16 is accommodated in the concave portion 11a,
The connection failure caused by the inorganic filler 16 covering the peripheral electrode pads 14 can be prevented, and the semiconductor chip 10
Can be reliably connected to the wiring board 11, and the reliability can be improved.

【0057】図4は第3の実施形態を示し、第1および
第2の実施形態と同一構成部分には同一番号を付して説
明を省略する。半導体チップ10の下面には突起電極と
して高さが50μm程度の複数の金バンプ23が形成さ
れ、配線基板11には前記金バンプ23に対応して電極
パッド14が形成されている。配線基板11は少なくと
も半導体チップ10が実装される上層がガラスエポキシ
樹脂層で、ガラス転移点温度は140℃である。
FIG. 4 shows a third embodiment, in which the same components as those in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted. A plurality of gold bumps 23 having a height of about 50 μm are formed as projecting electrodes on the lower surface of the semiconductor chip 10, and electrode pads 14 are formed on the wiring board 11 corresponding to the gold bumps 23. At least the upper layer of the wiring board 11 on which the semiconductor chip 10 is mounted is a glass epoxy resin layer, and the glass transition point temperature is 140 ° C.

【0058】図4(a)に示すように、まず、シリンジ
(図示しない)を用い、配線基板11の半導体チップ実
装部位に熱可塑性樹脂からなる絶縁性接着剤25を供給
する。次に、半導体チップ10をフェースダウンさせ、
金バンプ23を配線基板11の電極パッド14に位置決
めする。
As shown in FIG. 4A, first, an insulating adhesive 25 made of a thermoplastic resin is supplied to a semiconductor chip mounting portion of the wiring board 11 using a syringe (not shown). Next, the semiconductor chip 10 is face down,
The gold bumps 23 are positioned on the electrode pads 14 of the wiring board 11.

【0059】次に、同図(b)に示すように、半導体チ
ップ10を裏面側からボンディングヘッド24によって
矢印F方向に加圧し、半導体チップ10および金バンプ
23によって絶縁性接着剤25を押し退けて金バンプ2
3を電極パッド14に接触させる。
Next, as shown in FIG. 3B, the semiconductor chip 10 is pressed from the back side in the direction of arrow F by the bonding head 24, and the insulating adhesive 25 is pushed away by the semiconductor chip 10 and the gold bumps 23. Gold bump 2
3 is brought into contact with the electrode pad 14.

【0060】さらに、半導体チップ10をボンディング
ヘッド24によって180℃〜250℃に加熱しながら
加圧すると、電極パッド14が配線基板11の絶縁性樹
脂層に押し込み、電極パッド14の上面が配線基板11
の上面より低くなり、半導体チップ10の素子面および
配線基板11の半導体チップ実装部位が絶縁性接着剤2
5により封止された状態となる。ここで、配線基板11
の肉厚は1〜2mm程度であり、電極パッド14の押し
込み量は10〜20μm程度である。
Further, when the semiconductor chip 10 is pressurized while being heated to 180 ° C. to 250 ° C. by the bonding head 24, the electrode pads 14 are pushed into the insulating resin layer of the wiring board 11, and the upper surface of the electrode pads 14
Of the semiconductor chip 10 and the semiconductor chip mounting portion of the wiring board 11
5 is sealed. Here, the wiring board 11
Has a thickness of about 1 to 2 mm, and the pushing amount of the electrode pad 14 is about 10 to 20 μm.

【0061】その後、半導体チップ10を配線基板11
に加圧した状態で、絶縁性接着剤25を冷却すると、電
極パッド14が配線基板11に押し込んだ状態で硬化
し、実装が完了する。
After that, the semiconductor chip 10 is connected to the wiring board 11.
When the insulating adhesive 25 is cooled under pressure, the electrode pads 14 are cured while being pressed into the wiring board 11, and the mounting is completed.

【0062】本実施形態によれば、半導体チップ10を
フェースダウンさせ、金バンプ23を配線基板11の電
極パッド14に接続でき、しかも電極パッド14が配線
基板11に押し込んだ状態となるため、実装強度が高く
信頼性を向上できる。
According to the present embodiment, the semiconductor chip 10 can be face-down, the gold bumps 23 can be connected to the electrode pads 14 of the wiring board 11, and the electrode pads 14 are pushed into the wiring board 11. High strength and improved reliability.

【0063】また、実装後、半導体チップ10が不良と
判明した場合には、半導体チップ10を封止した後でも
加熱することにより、熱可塑性の絶縁性接着剤25が軟
化し、配線基板11から引き剥してリペアできる。
If the semiconductor chip 10 is found to be defective after mounting, the semiconductor chip 10 is heated even after sealing, so that the thermoplastic insulating adhesive 25 is softened and It can be peeled and repaired.

【0064】図5および図6は第4の実施形態を示し、
第1〜第3の実施形態と同一構成部分には同一番号を付
して説明を省略する。図5に示すように、本実施形態の
配線基板11上には凹溝11bが設けられている。この
凹溝11bは半導体チップ実装部位およびその外側の電
極パッド14の間を通って電極パッド14の配列の外側
まで設けられている。
FIGS. 5 and 6 show a fourth embodiment.
The same components as those of the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 5, a concave groove 11b is provided on the wiring board 11 of the present embodiment. The concave groove 11b extends between the semiconductor chip mounting portion and the electrode pads 14 outside the semiconductor chip mounting portion to the outside of the arrangement of the electrode pads 14.

【0065】次に、配線基板11に半導体チップ10を
実装する実装方法について説明すると、図6(a)に示
すように、半導体チップ10をフェースダウンさせ、は
んだバンプ13を配線基板11の電極パッド14に位置
決めした後、はんだバンブ13を電極パッド14に搭載
し、はんだバンプ13を加熱して電極パッド14に接続
する。なお、この段階で半導体チップ10の実装不良が
検出された場合には新たな半導体チップ10に交換(リ
ペア)することができる。
Next, a mounting method for mounting the semiconductor chip 10 on the wiring board 11 will be described. As shown in FIG. 6A, the semiconductor chip 10 is face down and the solder bumps 13 are connected to the electrode pads of the wiring board 11. After positioning at 14, the solder bumps 13 are mounted on the electrode pads 14, and the solder bumps 13 are heated and connected to the electrode pads 14. If a mounting failure of the semiconductor chip 10 is detected at this stage, the semiconductor chip 10 can be replaced (repaired) with a new semiconductor chip 10.

【0066】次に、同図(b)に示すように、ディスペ
ンス法によって液状のエポキシ樹脂等の熱硬化性樹脂か
らなる封止樹脂19を電極パッド14の配列の外側に延
長した凹溝11bに塗布すると、封止樹脂19は毛細管
現象によって凹溝11bに沿って流れ、半導体チップ1
0と配線基板11との間隙に充填される。この場合、凹
溝11bによって半導体チップ10と配線基板11との
間隔が大きいため、封止樹脂19がスムーズに流れ、注
入性を向上できる。
Next, as shown in FIG. 6B, a sealing resin 19 made of a thermosetting resin such as a liquid epoxy resin is dispensed by a dispensing method into a concave groove 11 b extending outside the arrangement of the electrode pads 14. When applied, the sealing resin 19 flows along the concave groove 11b by capillary action, and the semiconductor chip 1
0 and the space between the wiring board 11 is filled. In this case, since the gap between the semiconductor chip 10 and the wiring board 11 is large due to the concave groove 11b, the sealing resin 19 flows smoothly, and the injection property can be improved.

【0067】次に、封止樹脂19を120〜160℃程
度に加熱させると、同図(c)に示すように、半導体チ
ップ10と配線基板11との間および半導体チップ10
の周辺の封止樹脂19が硬化される。したがって、半導
体チップ10と配線基板11との間にボイドが残ること
はなく、完全に封止でき、接続の信頼性が向上する。
Next, when the sealing resin 19 is heated to about 120 to 160 ° C., as shown in FIG.
Is hardened. Therefore, no void remains between the semiconductor chip 10 and the wiring board 11, the sealing can be completed completely, and the connection reliability is improved.

【0068】なお、配線基板11に設ける凹溝11bの
形状を図7に示すように、上方に向かって広がるテーパ
面11cを形成することにより、封止樹脂19の広がり
が一層スムーズとなる。
As shown in FIG. 7, the shape of the concave groove 11b provided in the wiring board 11 is formed as a tapered surface 11c which expands upward, so that the sealing resin 19 spreads more smoothly.

【0069】また、本実施形態においては、配線基板1
1に1本の凹溝11bを設けたが、凹溝11bは半導体
チップ実装部位に向かって複数本としてもよい(図7
(a))。また、半導体チップ実装部位に向かって下り
勾配の傾斜をつけることにより、封止樹脂19の流れが
一層スムーズとなる(図7(b)。また、凹溝11bは
半導体チップ実装部位に向かって漸次高幅となるテーパ
を有する形状としてもよい(図7(a))。
In this embodiment, the wiring board 1
Although one groove 11b is provided in one, a plurality of grooves 11b may be provided toward the semiconductor chip mounting portion (FIG. 7).
(A)). In addition, the flow of the sealing resin 19 is further smoothed by providing a downward slope toward the semiconductor chip mounting portion (FIG. 7B. The concave groove 11b is gradually formed toward the semiconductor chip mounting portion). A shape having a taper with a large width may be used (FIG. 7A).

【0070】図8は第5の実施形態を示し、第1〜第4
の実施形態と同一構成部分には同一番号を付して説明を
省略する。図7に基づいて配線基板11に半導体チップ
10を実装する実装方法について説明すると、同図
(a)に示すように、本実施形態の半導体チップ10に
は金、はんだ等の複数の突起電極26が形成されてい
る。
FIG. 8 shows a fifth embodiment.
The same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. A mounting method for mounting the semiconductor chip 10 on the wiring board 11 will be described with reference to FIG. 7. As shown in FIG. 7A, the semiconductor chip 10 of the present embodiment has a plurality of bump electrodes 26 such as gold and solder. Are formed.

【0071】同図(b)に示すように、突起電極26の
先端に導電性接着剤27を転写法あるいはディスペンス
法によって付着する。次に、同図(c)に示すように、
まず、半導体チップ10の突起電極26が存在しない領
域にシリンジ28aによってディスペンス法により熱硬
化性樹脂からなる絶縁性樹脂28を塗布する。
As shown in FIG. 7B, a conductive adhesive 27 is attached to the tip of the protruding electrode 26 by a transfer method or a dispense method. Next, as shown in FIG.
First, an insulating resin 28 made of a thermosetting resin is applied by a dispensing method to a region of the semiconductor chip 10 where the protruding electrodes 26 are not present by a syringe 28a.

【0072】次に、半導体チップ10を100℃以下で
数十秒以内で加熱すると、絶縁性樹脂27の粘度が低下
し、同図(d)に示すように、絶縁性樹脂28が突起電
極26を除き半導体チップ10の突起電極26の外側ま
で半導体チップ10の全域に拡散するが、表面張力によ
って周囲に流れ出ることはない。なお、絶縁性樹脂28
を半導体チップ10の突起電極26の外側まで半導体チ
ップ10の全域に広げる際に、半導体チップ10を回転
させ、遠心力を利用してもよい。
Next, when the semiconductor chip 10 is heated at a temperature of 100 ° C. or less within several tens of seconds, the viscosity of the insulating resin 27 decreases, and as shown in FIG. Except for the above, it diffuses to the entire area of the semiconductor chip 10 to the outside of the protruding electrode 26 of the semiconductor chip 10, but does not flow out to the surroundings due to surface tension. The insulating resin 28
The semiconductor chip 10 may be rotated and centrifugal force may be used when spreading the entire area of the semiconductor chip 10 to the outside of the protruding electrode 26 of the semiconductor chip 10.

【0073】次に、同図(e)に示すように、半導体チ
ップ10をフェースダウンさせ、突起電極26を配線基
板11の電極パッド14に位置決めする。次に、同図
(f)に示すように、半導体チップ10を配線基板11
に搭載し、半導体チップ10の突起電極26を電極パッ
ド14に対して加圧すると、突起電極26が押し潰され
て電極パッド14と電気的に接続されると共に、絶縁性
樹脂28が配線基板11に密着する。その後、絶縁性樹
脂28を120〜160℃程度に加熱させると、絶縁性
樹脂28と導電性接着剤27とが同時に硬化される。
Next, as shown in FIG. 7E, the semiconductor chip 10 is face down, and the protruding electrodes 26 are positioned on the electrode pads 14 of the wiring board 11. Next, as shown in FIG.
When the protruding electrode 26 of the semiconductor chip 10 is pressed against the electrode pad 14, the protruding electrode 26 is crushed and electrically connected to the electrode pad 14, and the insulating resin 28 is Adhere to Thereafter, when the insulating resin 28 is heated to about 120 to 160 ° C., the insulating resin 28 and the conductive adhesive 27 are simultaneously cured.

【0074】本実施形態のように、半導体チップ10に
塗布した絶縁性樹脂28を半導体チップ10の周辺に形
成された突起電極26の外側まで押し延ばした状態で、
半導体チップ10をフェースダウンで配線基板11に接
続した後、絶縁性樹脂28を導電性接着剤27と共に硬
化させることにより、半導体チップ10と配線基板11
との間にボイドがなく、確実に実装でき、信頼性を向上
できる。
As in the present embodiment, in a state where the insulating resin 28 applied to the semiconductor chip 10 is extended to the outside of the protruding electrodes 26 formed around the semiconductor chip 10,
After connecting the semiconductor chip 10 to the wiring board 11 face down, the insulating resin 28 is cured together with the conductive adhesive 27 so that the semiconductor chip 10 and the wiring board 11 are hardened.
There is no void between them, and it can be mounted reliably and reliability can be improved.

【0075】[0075]

【発明の効果】この発明の請求項1〜4によれば、半導
体チップと配線基板との間隙に予め無機フィラーを供給
し、ついで半導体チップと配線基板との間隙に封止樹脂
を注入することにより、封止樹脂に無機フィラーを多く
含有させる必要がなく、封止樹脂の粘度が高くならない
ため、流動性が維持され、半導体チップと配線基板との
狭い間隙にスムーズに注入され、作業性の向上を図るこ
とができる。
According to the present invention, an inorganic filler is supplied in advance to the gap between the semiconductor chip and the wiring board, and then the sealing resin is injected into the gap between the semiconductor chip and the wiring board. This eliminates the need for the sealing resin to contain a large amount of inorganic filler, and does not increase the viscosity of the sealing resin. Improvement can be achieved.

【0076】請求項5〜10によれば、電極パッドが配
線基板に押し込んだ状態となるため、基板の反りや伸び
によるバンブ接続部の破断が防止される。また、実装
後、半導体チップが不良と判明した場合には、半導体チ
ップを封止した後でも加熱することにより、熱可塑性の
絶縁性接着剤が軟化し、配線基板から引き剥してリペア
できる。
According to the fifth to tenth aspects, since the electrode pads are pushed into the wiring board, breakage of the bump connection portion due to warpage or elongation of the board is prevented. If the semiconductor chip is found to be defective after mounting, the thermoplastic insulating adhesive is softened by heating even after the semiconductor chip is sealed, and can be repaired by being peeled off from the wiring board.

【0077】請求項11〜13によれば、配線基板に設
けられた凹溝に沿って封止樹脂がスムーズに流れるた
め、半導体チップと配線基板との間隙に充填された封止
樹脂にボイドが残ることはなく、完全に封止でき、信頼
性を向上できる。
According to the present invention, since the sealing resin smoothly flows along the concave groove provided in the wiring board, voids are formed in the sealing resin filled in the gap between the semiconductor chip and the wiring board. It does not remain, can be completely sealed, and can improve reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1の実施形態を示す半導体実装方
法の工程図。
FIG. 1 is a process chart of a semiconductor mounting method according to a first embodiment of the present invention.

【図2】同実施形態の半導体実装構造を示す縦断側面
図。
FIG. 2 is a vertical side view showing the semiconductor mounting structure of the embodiment.

【図3】この発明の第2の実施形態を示す半導体実装方
法の工程図。
FIG. 3 is a process diagram of a semiconductor mounting method according to a second embodiment of the present invention.

【図4】この発明の第3の実施形態を示す半導体実装方
法の工程図。
FIG. 4 is a process chart of a semiconductor mounting method according to a third embodiment of the present invention.

【図5】この発明の第4の実施形態を示す配線基板の斜
視図。
FIG. 5 is a perspective view of a wiring board according to a fourth embodiment of the present invention.

【図6】同実施形態を示す半導体実装方法の工程図。FIG. 6 is a process chart of the semiconductor mounting method according to the embodiment;

【図7】同実施形態の変形例を示す半導体実装構造を示
す縦断側面図。
FIG. 7 is a vertical sectional side view showing a semiconductor mounting structure showing a modification of the embodiment.

【図8】この発明の第5の実施形態を示す半導体実装方
法の工程図。
FIG. 8 is a process chart of a semiconductor mounting method according to a fifth embodiment of the present invention.

【図9】従来の半導体実装方法の第1の例を示す工程
図。
FIG. 9 is a process chart showing a first example of a conventional semiconductor mounting method.

【図10】従来の半導体実装方法の第2の例を示す工程
図。
FIG. 10 is a process chart showing a second example of a conventional semiconductor mounting method.

【図11】従来の半導体実装方法の第3の例を示す工程
図。
FIG. 11 is a process chart showing a third example of a conventional semiconductor mounting method.

【図12】従来の半導体実装方法の第4の例を示す工程
図。
FIG. 12 is a process chart showing a fourth example of a conventional semiconductor mounting method.

【符号の説明】[Explanation of symbols]

10…半導体チップ 11…配線基板 13…はんだバンプ 14…電極パッド 16…無機フィラー 19…封止樹脂 23…金バンプ 25…絶縁性接着剤 26…突起電極 27…導電性接着剤 DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip 11 ... Wiring board 13 ... Solder bump 14 ... Electrode pad 16 ... Inorganic filler 19 ... Sealing resin 23 ... Gold bump 25 ... Insulating adhesive 26 ... Protruding electrode 27 ... Conductive adhesive

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップをフェースダウンで配線基
板に実装する半導体実装方法において、 前記配線基板上の半導体チップ実装部位に絶縁性の無機
フィラーを供給する工程と、 前記配線基板上の前記無機フィラーが供給された半導体
チップ実装部位に半導体チップをフェースダウンで搭載
する工程と、 前記搭載された半導体チップと前記配線基板との間隙に
封止樹脂を充填する工程と、 前記充填された封止樹脂を加熱硬化する工程とを具備す
ることを特徴とする半導体実装方法。
1. A semiconductor mounting method for mounting a semiconductor chip on a wiring board face down, comprising: supplying an insulating inorganic filler to a semiconductor chip mounting portion on the wiring board; Mounting the semiconductor chip face down on the semiconductor chip mounting site to which the semiconductor chip is supplied; filling the gap between the mounted semiconductor chip and the wiring board with a sealing resin; and filling the sealing resin. And a step of heating and curing the semiconductor device.
【請求項2】 成分中に無機フィラーと結合するカップ
リング剤が含有されている封止樹脂を充填することを特
徴とする請求項1記載の半導体実装方法。
2. The semiconductor mounting method according to claim 1, wherein a sealing resin containing a coupling agent that binds to an inorganic filler in the components is filled.
【請求項3】 封止樹脂を加熱硬化する工程は、配線基
板を反転して半導体チップを前記配線基板の下側にした
後、前記封止樹脂を加熱硬化させることを特徴とする請
求項1記載の半導体実装方法。
3. The step of heating and curing the sealing resin, wherein the wiring substrate is turned over so that the semiconductor chip is located below the wiring substrate, and then the sealing resin is heated and cured. The semiconductor mounting method described in the above.
【請求項4】 配線基板は、半導体チップ実装部位に無
機フィラーを貯留する凹部が形成されていることを特徴
とする請求項1記載の半導体実装方法。
4. The semiconductor mounting method according to claim 1, wherein the wiring board has a concave portion for storing an inorganic filler in a semiconductor chip mounting portion.
【請求項5】 突起電極を有する半導体チップをフェー
スダウンで電極パッドを有する配線基板に実装する半導
体実装方法において、 前記半導体チップの突起電極形成面の突起電極を除く素
子面、前記配線基板の半導体チップ実装部位の少なくと
も一方に熱可塑性を呈する絶縁性接着剤を供給する第1
の工程と、 前記絶縁性接着剤が供給されたのに基づき前記配線基板
上の半導体チップ実装部位に前記半導体チップをフェー
スダウンで載置する第2の工程と、 前記半導体チップの突起電極が形成されていない裏面側
からボンディングヘッドにより加熱しながら加圧して前
記突起電極を前記電極パッドに押圧し、前記電極パッド
を前記配線基板に押し込ませる第3の工程と、 前記半導体チップと前記配線基板との間に介在している
前記絶縁性接着剤を硬化する第4の工程とを具備するこ
とを特徴とする半導体実装方法。
5. A semiconductor mounting method for mounting a semiconductor chip having a protruding electrode face down on a wiring board having an electrode pad, wherein: First to supply an insulating adhesive exhibiting thermoplasticity to at least one of the chip mounting portions
A second step of mounting the semiconductor chip face down on a semiconductor chip mounting portion on the wiring board based on the supply of the insulating adhesive; and forming a protruding electrode of the semiconductor chip. A third step of pressing the protruding electrode against the electrode pad by applying pressure while heating with a bonding head from the back side not being pressed, and forcing the electrode pad into the wiring board; and And a fourth step of curing the insulating adhesive interposed therebetween.
【請求項6】 第3の工程は、少なくとも電極パッドを
有する面がガラスエポキシ樹脂層で形成された配線基板
をガラス転移点以上の温度で加熱しながら加圧して突起
電極を前記電極パッドに押圧し、前記電極パッドを前記
配線基板に押し込ませることを特徴とする請求項5記載
の半導体実装方法。
6. The third step is to press a projecting electrode against the electrode pad by heating and pressing a wiring substrate having at least a surface having an electrode pad formed of a glass epoxy resin layer at a temperature equal to or higher than a glass transition point. 6. The semiconductor mounting method according to claim 5, wherein said electrode pad is pushed into said wiring board.
【請求項7】 請求項5記載の半導体実装方法におい
て、第1の工程は、フィルム状あるいはペースト状の絶
縁性接着剤を突起電極形成面の突起電極を除く半導体チ
ップの素子面、配線基板の前記半導体チップ実装部位の
少なくとも一方に供給した後、前記絶縁性接着剤中に存
在する溶剤を揮発させる工程を有することを特徴とする
半導体実装方法。
7. The semiconductor mounting method according to claim 5, wherein the first step comprises applying a film-like or paste-like insulating adhesive to the element surface of the semiconductor chip excluding the projecting electrodes on the projecting electrode forming surface and the wiring board. A semiconductor mounting method, comprising a step of volatilizing a solvent present in the insulating adhesive after supplying to at least one of the semiconductor chip mounting portions.
【請求項8】 突起電極を有する半導体チップをフェー
スダウンで電極パッドを有する配線基板に実装する半導
体実装構造において、 前記突起電極を介して前記半導体チップが前記電極パッ
ドと接続されると共に、この電極パッドの接続面が配線
基板の板面より低く押し込まれた状態で、前記半導体チ
ップの素子面および前記配線基板の半導体チップ実装面
が熱可塑性を呈する絶縁性接着剤によって封止されてい
ることを特徴とする半導体実装構造。
8. A semiconductor mounting structure for mounting a semiconductor chip having a protruding electrode face down on a wiring board having an electrode pad, wherein said semiconductor chip is connected to said electrode pad via said protruding electrode, and said electrode is connected to said semiconductor chip. With the connection surface of the pad pressed down below the plate surface of the wiring board, the element surface of the semiconductor chip and the semiconductor chip mounting surface of the wiring substrate are sealed with a thermoplastic insulating adhesive. Characteristic semiconductor mounting structure.
【請求項9】 請求項8記載の半導体実装構造におい
て、半導体チップと配線基板の電気的接続部は、前記半
導体チップの前記配線基板への実装工程中の最も高い加
熱温度よりも融点が高い金属材料からなることを特徴と
する半導体実装構造。
9. The semiconductor mounting structure according to claim 8, wherein the electrical connection between the semiconductor chip and the wiring board has a melting point higher than the highest heating temperature during the step of mounting the semiconductor chip on the wiring board. A semiconductor mounting structure comprising a material.
【請求項10】 半導体チップがフェースダウンで配線
基板に実装された半導体実装構造において、 前記配線基板の前記半導体チップにより覆われる部位と
この覆われた部位の外側とを結ぶ凹溝を有した配線基板
と、この配線基板の半導体チップ実装部位に実装された
半導体チップと、前記凹溝を介して前記半導体チップ実
装部位に充填され前記半導体チップと配線基板との間を
封止する絶縁性樹脂とを具備したことを特徴とする半導
体実装構造。
10. In a semiconductor mounting structure in which a semiconductor chip is mounted face down on a wiring board, a wiring having a concave groove connecting a part of the wiring board covered by the semiconductor chip and an outside of the covered part. A substrate, a semiconductor chip mounted on the semiconductor chip mounting portion of the wiring substrate, and an insulating resin filled in the semiconductor chip mounting portion via the concave groove and sealing between the semiconductor chip and the wiring substrate. A semiconductor mounting structure comprising:
【請求項11】 半導体チップをフェースダウンで配線
基板に実装する半導体実装方法において、 前記配線基板の前記半導体チップにより覆われる部位と
この覆われた部位の外側とを結ぶ凹溝を有した配線基板
の前記半導体チップ実装部位に前記半導体チップをフェ
ースダウンで実装した後、前記凹溝の前記半導体チップ
実装部位より外側から絶縁性樹脂を供給し、前記凹溝を
介して前記半導体チップと前記配線基板との間に絶縁性
樹脂を供給して前記半導体チップと前記配線基板とを封
止することを特徴とする半導体実装方法。
11. A semiconductor mounting method for mounting a semiconductor chip on a wiring board face-down, wherein the wiring board has a concave groove connecting a portion of the wiring board covered by the semiconductor chip and an outside of the covered portion. After the semiconductor chip is mounted face-down on the semiconductor chip mounting portion, an insulating resin is supplied from outside the semiconductor chip mounting portion of the concave groove, and the semiconductor chip and the wiring board are supplied through the concave groove. And supplying an insulating resin between the semiconductor chip and the semiconductor chip to seal the semiconductor chip and the wiring substrate.
【請求項12】 突起電極を有する半導体チップをフェ
ースダウンで配線基板に実装する半導体実装方法におい
て、 前記半導体チップの前記突起電極の少なくとも先端に導
電性接着剤を付着する工程と、 前記半導体チップの前記突起電極が存在しない領域に絶
縁性樹脂を供給する工程と、 導電性接着剤および絶縁性樹脂が供給された前記半導体
チップをフェースダウンで前記突起電極を前記配線基板
の電極パッドに位置決めした後、前記半導体チップを配
線基板に搭載する工程と、 前記半導体チップを配線基板に搭載したのに基づき前記
導電性接着剤および絶縁性樹脂を加熱硬化する工程とを
具備することを特徴とする半導体実装方法。
12. A semiconductor mounting method for mounting a semiconductor chip having a protruding electrode face down on a wiring board, wherein a step of attaching a conductive adhesive to at least a tip of the protruding electrode of the semiconductor chip; A step of supplying an insulating resin to a region where the projecting electrode is not present; and a step of positioning the projecting electrode on an electrode pad of the wiring board face down with the semiconductor chip supplied with the conductive adhesive and the insulating resin. Mounting the semiconductor chip on a wiring board; and heating and curing the conductive adhesive and the insulating resin based on the mounting of the semiconductor chip on the wiring board. Method.
【請求項13】 請求項12記載の半導体実装方法にお
いて、 前記半導体チップの突起電極の少なくとも先端に導電性
接着剤を付着する工程は、半導体チップの突起電極が存
在しない領域に絶縁性樹脂を供給した後、加熱して前記
絶縁性樹脂の粘度を低下させ、前記突起電極を除く前記
半導体チップの全域に前記絶縁性樹脂を拡散させること
を特徴とする半導体実装方法。
13. The semiconductor mounting method according to claim 12, wherein the step of attaching a conductive adhesive to at least the tip of the protruding electrode of the semiconductor chip includes supplying an insulating resin to a region of the semiconductor chip where no protruding electrode is present. And then heating to reduce the viscosity of the insulating resin and diffuse the insulating resin throughout the semiconductor chip except for the protruding electrodes.
JP23015096A 1996-08-30 1996-08-30 Method and structure for mounting semiconductor Pending JPH1074798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23015096A JPH1074798A (en) 1996-08-30 1996-08-30 Method and structure for mounting semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23015096A JPH1074798A (en) 1996-08-30 1996-08-30 Method and structure for mounting semiconductor

Publications (1)

Publication Number Publication Date
JPH1074798A true JPH1074798A (en) 1998-03-17

Family

ID=16903384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23015096A Pending JPH1074798A (en) 1996-08-30 1996-08-30 Method and structure for mounting semiconductor

Country Status (1)

Country Link
JP (1) JPH1074798A (en)

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