JPH1074061A - Timing adjusting circuit and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a timing adjustment with satisfactory accuracy by forming delay parts while connecting them in series and by adjusting a delay amount while designating non-selections or selections of delay parts by respective transfer gates of external control signals. SOLUTION: First to third delay parts DLY1∼DLY3 consisting of CMOS inverters are connected in series. An input IN of this delay circuit and respective outputs of first to third delay parts DLY1∼DLY3 are taken out to the output OUT of the delay circuit via respective transfer gates TRG1∼TRG3. In the delay circuit, only one transfer gate out of four transfer gates TRG1∼TRG3 can be made conducting and other can be all made nonconducting by the external control signals. Consequently, the signal inputted to the delay circuit can be controlled in four ways such as it is directly outputted or it is outputted via the delay part DLLY 1 or the like. Thus, the input signal becomes adjustable in its delay amount by the external control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing adjustment device for adjusting timing by shifting the phase of a clock signal, and more particularly to a drive circuit integrated type in which a display pixel portion and a drive circuit portion are integrally formed on a substrate. Liquid crystal display (LCD:
Liquid Crystal Display).

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a TFT as a switching element can perform static driving with a duty ratio of 100% in principle in a multiplex manner, and is used for a large-screen, high-definition moving image display.

An active matrix LCD has a substrate (TFT substrate) formed by connecting TFTs to display electrodes arranged in a matrix and a substrate having a common electrode (counter substrate).
Are bonded together with a liquid crystal interposed therebetween. The opposing portion between the display electrode and the common electrode is a pixel capacitance using a liquid crystal as a dielectric layer, and is sequentially selected by a TFT and a voltage is applied. The voltage applied to the pixel capacitor is the OF of the TFT.
It is held for one field period by the F resistor. The liquid crystal has electro-optical anisotropy, and the amount of transmitted light is finely adjusted according to the intensity of the electric field formed by the pixel capacitance. In this way, the distribution of light and dark whose transmittance is controlled for each pixel is visually recognized as a desired display image.

In recent years, by using polycrystalline (poly) silicon (p-Si) as a channel layer of a TFT,
An LCD integrated with a driving circuit in which a matrix pixel portion and a peripheral driving circuit portion are formed on the same substrate has been developed. Generally, p-Si has a higher mobility than amorphous silicon (a-Si). Therefore, the size of the TFT is reduced, and high definition is realized. Further, since high-speed operation can be achieved by miniaturization and reduction of parasitic capacitance by the gate self-alignment structure, a high-speed driving circuit can be formed by forming an n-ch TFT and a p-ch CMOS transistor. As described above, by integrally forming the driving circuit portion and the matrix pixel portion on the same substrate, reduction in manufacturing cost and downsizing of the LCD module can be realized.

FIG. 9 is a block diagram showing the structure of the LCD. The matrix circuit on the left is a display pixel portion. A gate line (GL) serving as a scanning line and a drain line (DL) serving as a signal line are arranged horizontally and vertically.
FT (SE) is formed. TFT (SE) has
One electrode of a pixel capacitor (LC) for driving a liquid crystal and one electrode of a storage capacitor (SC) for holding a charge are connected. The other electrode of the pixel capacitor is entirely formed on another substrate opposed to the liquid crystal layer. Around the display pixel area,
A drain driver (DD) mainly composed of a shift register and a sampling circuit and, in some cases, a hold capacitor, and a gate driver (GD) mainly composed of a shift register are arranged.

The gate driver (GD) and the drain driver (DD) are constituted by a TFT CMOS, and are similar to p-type TFTs (SE) in the pixel portion.
They are formed integrally on the same substrate using Si. The right side of the figure is the controller. The video interface (VDINT) receives the composite video signal, performs intermediate frequency amplification and color demodulation, creates an original picture signal VDSG for the LCD, sends it to the drain driver (DD), performs synchronization separation, and performs timing separation. Generator (T
M) to send a synchronization signal SYNC. The timing generator (TMG) generates a vertical start pulse VST, a vertical clock signal VCKL, a horizontal start pulse HST, and a horizontal clock signal HCLK from the synchronization signal,
Gate driver (GD) and drain driver (D
D).

A gate driver (GD) receives a vertical start pulse VST and a vertical clock signal VCLK,
The gate lines (GL) are sequentially selected in row units, and the TFTs are turned on for the same row. Drain driver (D
D) corresponds to the original image signal VDS in accordance with the scanning timing.
Each pixel signal voltage sampled from G is applied to the drain line (DL), and is applied to each pixel capacitor (LC) via the TFT (SE).

[0008] These video interfaces (VDIN
T) and the timing generator (TM) are formed on an external integrated circuit made of single crystal silicon (C-Si).

[0009]

SUMMARY OF THE INVENTION Such a p-SiT
Driver integrated LCD using FT is p-SiTF
Although realized by utilizing the high-speed operation of T, the logic circuit formed by the p-Si TFT is still slower than the logic circuit formed by C-Si, and a signal delay occurs.

Therefore, various signals supplied from outside are:
As the signal passes through a logic circuit composed of p-Si TFTs, the delay is gradually increased. Therefore, p-Si TFT
In the LCD, there is a problem that a signal having passed through a longer logic history has a phase lag than a signal having passed through a shorter logic history. In particular, the vertical or horizontal shift register constituting each driver (GD, DD) has a p-S
The logic gates are composed of iTFTs, and the signal delay increases as the number of gates configuring each output stage increases. Original image signal V in drain driver (DD)
If there is a deviation between the sampling timing when each pixel signal voltage is sampled from the DSG and the phase of the original image signal VDSG, or if there is a mismatch between the operation timings of the drain driver (DD) and the gate driver (GD), malfunction or display failure may occur. Was inviting problems.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and has a first to second (n-1) th power delay unit and a first delay unit in which the delay unit is unselected. , A second transfer gate for selecting the first delay section, and a second n-th transfer gate for selecting the first to second (n-1) th delay section. In this case, the delay time of the input signal is controlled as 2 to the power of n by selectively setting one of the first to second power transfer gates to a conductive state by an n-bit control signal. This is a timing adjustment circuit.

Thus, various operation timings of the semiconductor device can be optimally adjusted. In particular, the first to the second (n-1) th power delay units are composed of one or more inverter circuits composed of MOS transistors having a lower threshold value, and the outputs of these delay units are provided with a threshold value. In this configuration, an inverter circuit composed of a higher MOS transistor is interposed.

Thus, by performing the threshold control, the delay section and the waveform shaping section are formed on the same substrate, and a high-performance delay circuit is manufactured. In particular, a thin film transistor using a polycrystalline semiconductor and a display electrode forming one of a liquid crystal driving capacitor connected thereto are arranged in a matrix on a display portion of the substrate to form a display pixel. In a liquid crystal display device in which a driving circuit including two types of thin film transistors using a polycrystalline semiconductor is formed to sequentially apply a desired signal voltage to the row or / and column, The clock signal and / or the start pulse for controlling the timing of applying the signal voltage to the column include a first to a second (n-1) th power delay section and a first transfer for unselecting the delay section. A gate, a second transfer gate for selecting the first delay unit, and a second n-th transfer gate for selecting the first to second (n-1) th delay units It consists of a,
An n-bit control signal selectively turns on one of the first to second nth transfer gates to reduce the delay time of the clock signal and / or the start pulse to 2 n The configuration is such that the driving circuit is supplied to the driving circuit via a timing adjustment circuit that performs control in a multiplication manner.

Thus, the timing can be matched with the logic operation having the longer logic history by appropriately inserting and installing the timing adjustment circuit in the shorter portion of the logic history on the board. In particular, the first and second (n-1) th power delay units include one or a plurality of inverter circuits each including a thin film transistor in which a channel region is not doped with an impurity having the opposite conductivity type. In the output, an inverter circuit composed of a thin film transistor in which an impurity having the opposite conductivity type is doped in the channel region is interposed.

As a result, in the delay section, signal distortion occurs due to the resistance of the thin film transistor itself made of a polycrystalline semiconductor having a lower threshold, and further, the signal is shaped into a waveform by an inverter made of a thin film transistor having a higher threshold. Is obtained, and a rectangular wave whose phase is optimally delayed is obtained. In particular, at the output of the delay unit, a plurality of inverter circuits each composed of a thin film transistor having a different concentration of an impurity of the opposite conductivity type doped in the channel region are interposed in parallel. This is a configuration that can be selectively made conductive.

Thus, by selecting the delay section, the magnitude of each delay amount to be controlled discontinuously is selected, so that more accurate timing adjustment is performed.

[0017]

FIG. 1 is an equivalent circuit diagram of a delay circuit according to an embodiment of the present invention. First to third delay units (DLY1, DLY2, DLY3) each having an even number of CMOS type inverters connected to 2, 4, and 6 stages are connected in series, and input (IN) to this delay circuit, The output section of the first delay section (DLY1), the output section of the second delay section, and the output section of the third delay section (DLY3) are respectively transfer gates (TRG1, TRG2, TRG3, TRG4).
To the output (OUT) of the delay circuit.

FIG. 2 is an equivalent circuit diagram of the decoder according to the embodiment of the present invention. N with two inputs
Four OR gates are arranged, and a 2-bit control signal (A, B) input from the outside receives (A,
B), (A, * B), (* A, B) and (* A, * B)
Is entered as The outputs of these NOR gates are respectively non-inverted and inverted outputs (11, 12), (21, 22),
As (31, 32) and (41, 42),
Each transfer gate (TRG1, TRG2, T
RG3, TRG4).

As described above, the timing adjustment circuit of the present invention comprises the delay circuit shown in FIG. 1 and the decoder circuit shown in FIG. The external control signals (A, B) in FIG. 2 are output from the decoder outputs (11, 12),
Of (21, 22), (31, 32) and (41, 42), only one is (H, L) and all others are (L,
H), four types of control are performed. This allows
The delay circuit of FIG. 1 has four transfer gates (TRG).
1, TRG2, TRG3, TRG4) can be made conductive, and all others can be made nonconductive. Therefore, the signal input to the delay circuit is first output directly, secondly, output via the first delay unit (DLY1), or thirdly, the first and second signals. 2 delay unit (DLY
1, DLY2) or fourth, first,
Second and third delay units (DLY1, DLY2, DLY)
3) is controlled in four ways. Therefore, the input signal can freely adjust the delay amount by controlling the non-passing of the delay unit and the passing distance by the control signals (A, B).

This timing adjustment circuit is used, for example, in an LCD in which a display pixel portion and a drive circuit portion are integrally formed by forming a switching TFT and a CMOS transistor on the same substrate by p-Si. In order to adjust the phase of the clock signal of the driving circuit portion, the same is provided by forming a CMOS array of p-SiTFTs, similarly to the driving circuit portion. That is, the delay units (DLY1, DLY1,
DLY2, DLY3), the NOR gate, the inverter, and the like in FIG. 2 are n-ch and p-ch p-Si TFTs.
It consists of.

[0021]

FIG. 4 is an equivalent circuit diagram of a delay circuit according to a first embodiment of the present invention. Each delay unit (DL
Y1, DLY2, DLY3) are a plurality of delay CMOS inverters (50) connected in series, and each transfer gate (TRG1, TRG2, TRG3, TRG4)
Selects the number of stages in four ways, and controls the amount of delay.
Also, on the output side of these delay units, a CMO for waveform shaping is provided.
An S inverter (51) is provided.

In the MOS transistor constituting the inverter (50), the channel is non-doped, that is, the channel region is formed of a semiconductor layer which is not doped with impurities. Therefore, this transistor has a threshold voltage Vth of 0 volt or sufficiently low. Further, the channel length is large and the resistance is sufficiently high. On the other hand, the MOS transistor constituting the inverter (51) has channel doping, that is, the channel region is doped with an impurity having a conductivity type opposite to that of the transistor. Therefore, this transistor is sufficiently higher than the threshold voltage Vth of the inverter (50). Further, the channel length is small and the resistance is sufficiently low.

In the LCD, these CMOS inverters are composed of an n-ch and a p-channel integrated on a substrate.
It is composed of p-Si TFTs of channel ch. FIG. 5 shows how the signal is delayed in this delay section. (A)
Is a source signal such as a clock or pulse to be delayed, (b) is a distortion signal passed through the one-stage inverter (50), (c) is a distortion signal passed through the two-stage inverter (50), ( x) is a distortion signal that has finally passed through all the delay units selected. (Y) is a rectangular wave obtained by shaping the signal (x) by the waveform shaping inverter (51). The source signal which is a square wave is supplied to the delay inverter (5
0), the waveform is distorted by the ON resistance of the transistor. The amount of distortion of this waveform is adjusted by the number of stages of the delay inverter (50) passing therethrough. When the signal voltage rises or falls, the waveform shaping inverter (51) does not conduct until the voltage exceeds the threshold voltage Vth of the transistor, and conducts when the signal voltage exceeds the threshold voltage Vth. Therefore, in the delay unit, the signal (x) rises from the rise (fall) time of the source signal by adjusting the amount of distortion of the signal waveform and the slope at the rise or fall of the signal. Drop), the time difference until the threshold voltage Vth is reached
ly can be adjusted.

This structure is characterized by a delay inverter (5
The high resistance transistor of 0) is formed by channel non-doping. As a result, the threshold value of the transistor is set to 0 volt or sufficiently low, and the signal distorted in the delay unit can distort the rising (falling) slope. Then, by raising the threshold value of the transistor of the waveform shaping inverter (51) by channel doping, a rectangular wave having a delay time corresponding to the time when the signal reaches the threshold value at the time of rising (falling) is obtained.

In particular, in a p-Si TFT LCD,
The delay inverter (50) is formed of the same channel non-doped TFT as the pixel TFT (SE), and the waveform shaping inverter (51) is formed of the channel doped TFT, thereby being integrally formed on the substrate. FIG.
FIG. 9 is an equivalent circuit diagram of a delay circuit according to a second example of the present invention. The difference from the first embodiment is that a plurality of waveform shaping routes are provided. That is, a low-resistance TFT
A waveform shaping inverter (52) is provided in addition to the waveform shaping inverter (51) composed of
0), the switch (53) is switched by external control and the inverter (5).
Either 1) or the inverter (52) is selected. The TFTs constituting the waveform shaping inverters (51) and (52) are adjusted so that the thresholds are different from each other by controlling the channel doping amount. For example, when the threshold value of the inverter (52) is higher than that of the inverter (51), the time required for the distortion signal (x) sent from the delay inverter (50) to reach the threshold voltage Vth is longer than that of the inverter (51). Becomes longer, resulting in a delay time dl
y can be lengthened. Conversely, the inverter (5
When the threshold value of 2) is lower than that of the inverter (50), the delay time dly can be shortened. Therefore, by selecting which path by the switch (52), the transfer gates (TRG1, TRG2, TRG3,
TRG4), each delay time dly controlled as a discontinuous amount is generally lengthened or shortened, a delay with higher resolution is realized, and a more accurate timing Adjustment is possible.

FIG. 7 is a block diagram showing an embodiment in which the timing adjustment circuit of the present invention is applied to a driver-integrated LCD. The left side of the figure is an LCD, in which a gate line (GL) and a drain line (DL) are arranged crossing over the same substrate, and a TFT (SE) is formed at each intersection thereof. The TFT (SE) is connected to one electrode of a pixel capacitance (LC) as a display pixel and one electrode of an auxiliary capacitance (SC) for holding electric charge. The other electrode of the pixel capacitor (LC) is formed on another substrate, and the pair of substrates are opposed to each other with a liquid crystal interposed therebetween. A drive circuit for driving the display pixels is formed around the display pixel portion. That is, a gate driver (GD) that sequentially selects the gate line (GL) to control ON / OFF of writing to the pixel, and a drain line (DL) in synchronization with the selection timing of the gate line (GL). ), A drain driver (DD) for supplying a pixel signal voltage is formed. These drivers (GD, DD) use a C-type TFT using the same p-Si TFT as the TFT (SE) of the display pixel portion.
It is formed by MOS transistors. In this way, the TFTs (SE) are simultaneously switched on for the same row, and correspondingly, the pixel signal voltage is charged to the pixel capacitance via each drain line (DL).

On the right side of the figure is a control section formed on the external integrated circuit. A composite video signal received from the outside is supplied to a video interface circuit (VDIN
In T), synchronization separation, color separation, intermediate frequency amplification and the like are performed. The original image signal generated by the video interface circuit (VDINT) is supplied to a drain driver (DD), and the synchronization signal SYNC is supplied to a timing generator (TMG). The timing generator (TMG) includes a voltage-controlled oscillator (VCO), a vertical and horizontal counter and a decoder, generates a horizontal clock signal HCLK, a horizontal start pulse HST, a vertical clock signal VCLK, and a vertical start pulse VST, and generates a gate driver ( GD) and a drain driver (DD).

The gate driver (GD) mainly includes a shift register, and applies a high-level voltage to the gate line (GL) in accordance with the vertical clock signal VCLK. The drain driver (DD) mainly includes a shift register and a sampling circuit controlled by the shift register. During one horizontal period, a pixel signal voltage corresponding to an original image signal is sampled and applied to each drain line (DL). To go.

In this embodiment, in particular, the horizontal clock signal H
CLK is adjusted by a timing adjustment circuit (TMAD) including the delay circuits shown in FIGS. 1 and 2 and a decoder for controlling the delay circuits.
To supply it to the drain driver (DD) via the. And this timing adjustment circuit (TMAD)
Are n-ch and p- formed on the TFT array substrate.
The display pixel section and each driver (GD, D
D) and integrated on the substrate.

Each stage of the shift register, which is a main part of the gate driver (GD) and the drain driver (DD), includes an inverter and a clocked inverter, and the shift operation is controlled by a vertical clock signal and a horizontal clock signal, respectively. However, in an actual circuit, a logical operation controlled by each shift clock is performed by a plurality of stages of TFT elements until output to a gate line (GL) and a drain line (DD). p
Although the -Si TFT has a sufficient speed as an LCD driver, the speed is lower than that of an integrated circuit made of C-Si. In particular, when the logical operation history becomes long, a considerable signal delay occurs, and a timing shift occurs with the logical operation that has passed through a shorter logical history.

Specifically, a drain driver (DD)
In, a pixel signal voltage corresponding to each pixel is applied to each drain line (DL) by sampling the transmitted original image signal by a sampling transfer gate controlled by a shift register. At this time, if the timing of the sampling operation deviates from the phase of the original image signal, there arises a problem that an accurate pixel signal voltage corresponding to each pixel is not sampled.
That is, in a drain driver (DD) composed of a p-SiTFT CMOS inverter, the signal passes through several stages of logic gates from the shift operation of the shift register until an output signal is actually output from each stage and the sampling gate is turned ON. Therefore, a signal delay occurs. On the other hand, after the original image signal is directly supplied from the external integrated circuit, the signal delay in the drain driver (DD) is small. For this reason, the sampling timing is different from the optimum phase of the original image signal, so that an accurate pixel signal is not created, or a pixel signal voltage different from that of the corresponding pixel is applied.

In particular, a driver-integrated p-Si TFTL
In the CD, the drain driver (DD) performs a dot-sequential driving in which the transmitted original image signal is sampled and simultaneously applied to each drain line (DL) as a pixel signal voltage. Therefore, if the ON timing of the sampling TFT controlled by the shift register is out of phase with the original image signal, a problem occurs in that an accurate pixel signal voltage is not applied to the corresponding pixel.

Further, in an LCD, a gate line (GL)
The selection period of one line and the timing of sending the pixel signal voltage to each drain line (DL) must coincide with high accuracy. If the timing is shifted, the ON period of the pixel TFT is shifted from the application timing of the pixel signal voltage to be supplied to the corresponding pixel.
In line-sequential driving, the ON period of the TFT and the period of voltage application to the pixel capacitor are shifted, and sufficient charging is not performed.
Alternatively, in the dot sequential driving, at the left or right end of the screen, there is a problem that the pixel signal voltage is not supplied during the ON period of the TFT and the display is not displayed.

Therefore, in this embodiment, the horizontal clock signal HCLK is supplied to the timing adjustment circuit (TMA) in order to eliminate the deviation of the logic operation due to the difference in the length of the logic history from each stage output of the shift register to the sampling TFT.
D). Then, the delay amount is actually adjusted by the external control signals (A, B) to control so that the best display is obtained. That is, the timing of the shift operation of the horizontal shift register and the timing of the shift operation of the original image signal or the vertical shift register are matched with high accuracy.

The adjustment of the amount of delay is firstly performed by LC
External control signals (A, B) after completion of D module
A method of fixing the delay circuit by disconnecting and connecting a predetermined position of the decoder by using a YAG laser or the like after designating the optimal delay amount according to the above. Second, the timing saved on the hard disk in a monitor application of a personal computer Adjustment software and an external logic circuit corresponding to the adjustment software are provided, and the user performs bidirectional control of the external control signals (A, B) by external operation such as keyboard input so that the optimum timing is obtained. There is a method of making settings for adjustment, and the like.

FIG. 8 shows the timing adjustment circuit of the present invention as p
FIG. 14 is a block diagram according to another embodiment when applied to a SiTFT LCD. In this embodiment, the horizontal start pulse HST, the horizontal clock signal HCLK, and the vertical start pulse VST and the vertical clock signal VCLK are supplied through the timing adjustment circuit (TMAD). Thereby, the gate line (G) is output from the output of each stage of the shift register in the gate driver (GD).
Even if the logic history up to L) is longer than the logic history from the output of each stage of the shift register to the drain line (DL) in the drain driver (DD), the optimum timing can be adjusted by this configuration. Further, the operation timing of the original picture signal and the horizontal shift register, and the operation timing of the horizontal shift register and the vertical shift register are adjusted with higher accuracy. Therefore, it is most suitable for an ultra-high-definition LCD such as SVGA and XGA in which the timing of the gate driver (GD) and the timing of the drain driver (DD) must match with higher precision.

Further, by adopting this timing adjustment circuit, it is not necessary to insert and form an inverter as appropriate in order to match various timings at the design stage, and the occupied area of the driver section is reduced. That is, in the shift register, the clock signal is delayed, so that the shift operation itself is delayed.
Eliminating several stages of inverters at the output of each stage of the shift register by estimating the delay of the signal in advance eliminates the need for a driver section on the substrate, thereby reducing the frame area. .

[0038]

As is apparent from the above description, a delay circuit having a large degree of freedom is realized by the present invention, so that the timing can be accurately adjusted. In particular, in a liquid crystal display device in which a peripheral driving circuit is formed integrally with a display pixel portion on a substrate, even if there is a difference in the logic history of a logic circuit made of a polycrystalline semiconductor, the logic operation of a path with a shorter logic history is performed. By optimally delaying, the timing of the logical operation can be matched with high accuracy.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a delay circuit according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the decoder according to the embodiment of the present invention.

FIG. 3 is a logic table showing an operation of the delay circuit according to the embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the delay circuit according to the first example of the present invention.

FIG. 5 is a timing chart showing signal delay by the delay circuit of the present invention.

FIG. 6 is an equivalent circuit diagram of a delay circuit according to a second example of the present invention.

FIG. 7 is a block diagram of an LCD according to an embodiment of the present invention.

FIG. 8 is a block diagram of an LCD according to another embodiment of the present invention.

FIG. 9 is a block diagram of a conventional LCD.

[Explanation of symbols]

11, 12, 21, 22, 31, 32, 41, 42 Decoder output 50 Inverter for delay 51, 52 Inverter for waveform shaping

Claims (5)

[Claims] 1. A first to a second (n-1) th power delay unit, a first transfer gate for unselecting the delay unit, and a second transfer gate for selecting the first delay unit A gate, and a second n-th transfer gate for selecting the first to the second (n-1) th delay unit,
By selectively turning on any one of the first to second nth transfer gates by an n-bit control signal, it is possible to control the delay time of the input signal as 2nth power. Characteristic timing adjustment circuit. 2. The first and second (n-1) th power delay units are composed of one or more inverter circuits composed of MOS transistors having a lower threshold value. 2. The timing adjustment circuit according to claim 1, further comprising an inverter circuit including a MOS transistor having a higher threshold value. 3. A display section of a substrate, comprising:
Thin-film transistors using a polycrystalline semiconductor and display electrodes forming one of the liquid crystal driving capacitors connected to the thin-film transistors are arranged in rows and columns, and a desired signal voltage is sequentially applied to the rows or / and columns at the periphery of the substrate. In a liquid crystal display device in which a driving circuit including two types of thin film transistors using a polycrystalline semiconductor is formed, a clock signal for controlling timing of applying a signal voltage to a row and / or a column of the driving circuit is provided. And / or the start pulse includes a first to a second (n-1) th power of a delay unit, a first transfer gate for unselecting the delay unit, and a second transfer gate for selecting the first delay unit. And a second n-th transfer gate for selecting the first to the second (n-1) -th power delay section. The first and second n
By selectively turning on one of the transfer gates of the power to the drive circuit via a timing adjustment circuit for controlling the delay time of the clock signal and / or the start pulse to 2 n powers A liquid crystal display device characterized by being supplied. 4. The first to second (n-1) th power delay units are composed of one or more inverter circuits each composed of a thin film transistor in which a channel region is not doped with an impurity having the opposite conductivity type. 4. The liquid crystal display device according to claim 3, wherein an output of the delay unit includes an inverter circuit including a thin film transistor in which an impurity having a reverse conductivity type is doped in a channel region. 5. An output of the delay unit includes a plurality of inverter circuits formed of thin film transistors having different concentrations of impurities of the opposite conductivity type doped in a channel region in parallel, and these inverter circuits are controlled by an external control signal. The liquid crystal display device according to claim 4, wherein one of the circuits is selectively turned on.