JPH1070583A - Bit synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce data errors by stabilizing synchronizing operation with respect to the fluctuation of a signal level. SOLUTION: A programmable counter 16 frequency-divides the clock T0 of the even-number of times of a baud rate to generate the timing T1 of 1/2 period of the baud rate and a frequency divider 17 converts it into the timing T2 of the baud rate. A phase measuring unit 11 measures the phase changing quantity of former and later halves between the baud timing of an input π/4 shift QPSK(quadrature phase shift keying) signal (x) (amplitude limited signal a) through the use of the timing T1 with a data latch 12 and a subtracter 13 to generate the difference (d) of both of the halves and a data latch 18 makes it a difference (e) corresponding to the timing T2. A multiplier 21 gives weight to the difference (e) according to a signal level (level data f) from a level measuring device 14. An adder 19 corrects initial data (h) by the weighted difference (g) to change the frequency dividing number of the programmable counter to correct a synchronizing timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit, and more particularly to a phase synchronization modulation type signal such as a .pi. / 4 shift QPSK signal whose phase changes at each data baud timing (symbol timing). The present invention relates to a bit synchronization circuit for achieving synchronization of

[0002]

2. Description of the Related Art A conventional bit synchronization circuit of this type is used, for example, in a receiving circuit of a mobile radio communication system, etc.
As shown in the figure, a clock generator 15 for generating a clock T0 that is an even multiple of the baud rate (symbol rate), and a baud rate of 1 when the frequency division number data i becomes the initial data h.
A programmable counter 16 that generates a timing signal T1 having a period of / 2, and the timing signal T1 being input, the .pi. / 4
The phase change of the shift QPSK signal a is １ ／ of the baud rate.
A phase measurement circuit 11 for measuring each cycle, a subtractor 13 for calculating a difference between a first half phase change amount and a second half phase change amount between each baud timing using the phase measurement circuit 11 and the data latch 12, A data latch 18 that divides T1 by 2 and holds it at a timing T2, and an adder 19 that adds and subtracts the held subtraction result e to and from initial data h generated by an initial data generator 20 are provided. When the input π / 4 shift QPSK signal x deviates from the baud timing, the frequency division number data i output by the adder 9 is corrected by the difference between the first half phase change and the second half phase change between each baud timing. As a result, the timing T2 coincided with the baud timing.

[0003]

In the above-mentioned conventional bit synchronization circuit, the amount of correction for synchronization pull-in is fixed irrespective of the level of the received π / 4 shift QPSK signal. Is lost, the signal level is restored, and then the signal is re-synchronized. Therefore, in a system in which the level of the transmitted / received signal fluctuates frequently, for example, in a mobile radio communication system in which the reception field strength of the radio signal fluctuates, the rate of occurrence of data error is increased Was high. Also, in a steady low signal level environment (weak electric field), random synchronization correction is likely to occur, the phase measurement timing fluctuates frequently, and the accuracy of data demodulation is poor.

[0004] It is an object of the present invention to provide a bit synchronization circuit that reduces the occurrence of data errors due to fluctuations in the received signal level by changing the amount of synchronization pull-in correction according to the received signal level.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a bit synchronization circuit for receiving a signal of a phase shift keying type in which the phase changes at each baud timing of data and for synchronizing the baud timing. And generating timing correction instruction information indicating a correction amount of the baud timing according to a difference between the phase change amount in the first half and the phase change amount in the second half between each baud timing, and the timing correction in accordance with the level of the received signal. The correction amount of the instruction information is weighted, and the baud timing of the received signal is synchronized based on the weighted timing correction instruction information.

Further, in the above configuration, a programmable counter for dividing a clock having an even multiple of the baud rate of the received signal to be synchronized to generate a timing signal having a period of ボ ー cycle of the baud rate by dividing the clock according to a preset initial count value; A phase measurement circuit for measuring a phase change of the received signal based on the timing signal for each half cycle of a baud rate; and a phase change amount in a first half and a phase in a second half between each baud timing using the phase measurement circuit. Means for comparing the amount of change and obtaining the difference as timing correction instruction information; a level measurement circuit for measuring the level of the received signal; and weighting the timing correction instruction information according to the result of the level measurement by the level measurement circuit. Means for performing Was subtracted from the initial count value of Rukaunta can moth be configured to have a means to modify the period of the timing signal. Further, the reception signal to be synchronized may be a π / 4 shift QPSK signal.

According to the present invention, in order to minimize the difference between the phase change in the first half and the phase change in the second half between each baud timing of a reception signal to be synchronized, such as a π / 4-shifted QPSK signal, the difference is reduced. By providing a multiplier for performing weighting based on the level measurement result of the received signal before adding or subtracting from the initial value of the programmable counter, the value to be added or subtracted from the initial value of the programmable counter is large when the received signal level is high, and the received signal level is large. When it's low, it gets smaller,
Synchronous operation can be stabilized.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Blocks having the same reference numerals as those in FIG. 2 showing the prior art have the same functions. In FIG. 1, the bit synchronization circuit of the present invention is different from the prior art in that a level measuring unit 14 for measuring the level of a π / 4 shift QPSK signal x which is an input reception signal to be synchronized and an output of a data latch 18 e is multiplied by the output f of the level measuring circuit 14 to obtain an adder 1
9 and a multiplier 21 for inputting the signal to the input terminal 9.

Next, the operation will be described. Clock generator 15
Generates a clock T0 that is 2N times (even number times) the baud rate (symbol rate) of a received signal subjected to equal amplitude phase shift modulation for each symbol corresponding to digital data. When the initial data h stored and output in advance in the initial data generator 20 is set to N, when the output g of the multiplier 11 is ± 0, the adder 19 that adds the initial data h and the output g of the multiplier 21 is used. The determined frequency division number data i to the programmable counter 16 becomes N, and the programmable counter 16
Divides the clock T0 into 1 / i (= N) (divides by N) and outputs the phase measurement timing T1 which is twice the baud rate (１ ／ cycle). Further, a timing (synchronous baud timing (symbol timing)) T2 obtained by dividing the phase measurement timing T1 by が (divided by 2) by the frequency divider 17
Has the same cycle as the borator.

On the other hand, the π /
The 4-shift QPSK signal x becomes a signal a whose amplitude is limited by the limiter 10. The phase change of the signal a at a certain timing is measured by the phase measuring device 11 and output as phase change data b, compared with the previous phase change data c held in the data latch 12 and the difference d is output from the subtractor 13. You. This difference d is held by the data latch 18 at the timing T2. The output is the difference e between the first half phase change amount and the second half phase change amount between each timing T2. The difference e serves as timing correction instruction information that is a basis for correcting the periods of the output timings T1 and T2 by the programmable counter 16 and the frequency divider 17.

If the timing T2 coincides with the baud timing, the phase change amount in the first half and the phase change amount in the second half coincide due to the characteristics of the π / 4 shift QPSK signal, and the difference e becomes ± 0.

If the phase change amount in the first half is large, it indicates that the timing T2 is shifted from the baud timing, the difference e and the output g of the multiplier become positive values, and the frequency division number data i becomes larger than N; The timing T2 is corrected so as to be delayed.

When the amount of phase change in the latter half is large, it indicates that the timing T2 is shifted from the baud timing, the difference e and the output g of the multiplier become negative values, and the frequency division number data i becomes smaller than N, The timing T2 is corrected in the moving direction.

The level measuring device 14 is π / 4 shift QPSK.
The level of the signal x is measured, and level data f indicating the level is generated. For example, when the bit synchronization circuit is applied to a radio receiving circuit, data indicating the received electric field strength of the radio signal is generated. The multiplier 21 weights the difference e with the value of the level data f and corrects the timing correction instruction information. That is, when the received signal level is sufficiently high, the correction amount g of the frequency division number data i becomes equal to the difference e, and as the received signal level decreases, the correction amount g becomes smaller than the difference e. The adder 19 corrects the initial data h from the initial data generator 20 with the correction amount g, and changes the output frequency division number data i. The programmable counter 16 divides the frequency of the clock T0 based on the division number data i whose correction amount has been corrected according to the signal level, and corrects the period of the timings T1 and T2. Thus, the input π / 4 shift Q
Baud timing synchronization with digital data in the PSK signal format can be stabilized.

In the description of the present embodiment, a π / 4 shift QPSK signal is taken as an example of a signal format for a synchronous operation. However, the present invention is not limited to this, and the phase is changed every data baud timing. It is applicable to all signals of changing phase shift keying format.

[0017]

According to the present invention, when the received signal level is low, the amount of correction of the bit synchronization timing is reduced, so that the received signal level temporarily drops like a radio signal used in a radio communication system. Even if it returns, the synchronization is hardly lost. Further, even if the received signal level is constantly low, the bit synchronization timing does not fluctuate, so that the phase measurement can be performed stably and the data error rate can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 10 limiter 11 phase measuring device 12, 18 data latch 13 subtracter 14 level measuring device 15 clock generator 16 programmable counter 17 frequency divider 19 adder 20 initial data generator 21 multiplier

Claims (3)

[Claims] A bit synchronization circuit for receiving a signal in a phase shift keying format in which the phase changes at each baud timing of data and for synchronizing the baud timing, comprising: Along with generating timing correction instruction information indicating a correction amount of the baud timing according to the difference between the phase change amount and the second half phase change amount, the correction amount of the timing correction instruction information is weighted according to the level of the received signal. A bit synchronization circuit for synchronizing the baud timing of the reception signal based on the weighted timing correction instruction information. 2. A programmable counter which divides a clock of an even multiple of the baud rate of a reception signal to be subjected to a synchronous operation in accordance with a preset initial count value and generates a timing signal having a half cycle of the baud rate; A phase measurement circuit that measures a phase change of the received signal at every half cycle of a baud rate based on the first and second phase changes between each baud timing using the phase measurement circuit. Means for comparing and obtaining the difference as timing correction instruction information; a level measurement circuit for measuring the level of the received signal; and means for weighting the timing correction instruction information according to the result of the level measurement by the level measurement circuit. The weighted result of the timing correction instruction information is stored in the initial counter of the programmable counter. Bit synchronization circuit according to claim 1, characterized in that it comprises a means for correcting the periods of acceleration and the timing signal to the cement value. 3. The bit synchronization circuit according to claim 1, wherein the reception signal to be synchronized is a π / 4 shift QPSK signal.