JPH1070267A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of steps by providing a semiconductor substrate, a gate electrode having upper end width shorter than the lower end width formed on the semiconductor substrate through a gate oxide, and a lightly doped region and a heavily doped region formed on the semiconductor substrate and specifying the shape of the gate electrode. SOLUTION: The semiconductor device comprises a semiconductor substrate 11 of silicon, a gate oxide 12 formed on the semiconductor substrate 11, a conductive polysilicon 13 and a tungsten-silicon 14 deposited on the gate oxide 12. The gate oxide 12, the conductive polysilicon 13 and the tungsten-silicon 14 define a gate electrode 15 having upper end width shorter than the lower end width. The semiconductor device further comprises a lightly doped region 16, a heavily doped region 17 and an LDD structure 18 defined by both doped regions 16, 17. Since the gate electrode 15 of the semiconductor device has upper end width shorter than the lower end width, the LDD structure 18 can be formed without forming any sidewall.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an LDD structure and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device which can be formed with a reduced number of steps compared to the conventional one.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing a structure of a conventional semiconductor device having an LDD structure. In the figure, 1 is a semiconductor substrate, 2 is a gate oxide film formed on the semiconductor substrate 1, and 3 and 4 are a polysilicon film and a tungsten silicon film sequentially laminated on the gate oxide film 2. Then, a gate electrode 5 is formed by the gate oxide film 2, the polysilicon film 3, and the tungsten silicon film 4. 6 is a side wall formed on both side walls of the gate electrode 5, 7 is a low-concentration impurity region, 8 is a high-concentration impurity region, and 9 is an LD formed by both impurity regions 8 and 9.
It is a D structure.

Next, a method for manufacturing a conventional semiconductor device having the above-described structure will be described with reference to FIGS.
First, the upper surface of the semiconductor substrate 1 is oxidized to form a gate oxide film 2a. Next, for example, CVD is performed on the gate oxide film 2a.
A polysilicon film 3a having a thickness of about 1000 angstroms is laminated by using the method. Next, a tungsten silicon film 4a having a thickness of about 1000 angstroms is laminated using, for example, a PVD method. Next, a resist is applied on the tungsten silicon film 4a and patterned to form a resist film 10 (FIG. 4A).

Next, anisotropic etching is performed using the resist film 10 as a mask. The condition of the etching gas at this time is, for example, when etching the tungsten silicon film 4a, for example, SF ₆ / Cl / F ₃₂ (CH ₂ F ₂ ) =
5/110/36, and the polysilicon film 3
The etching of the gate oxide film 2a and the gate oxide film 2a is performed, for example, at Cl ₂ / SF ₆ / F ₃₂ = 21/23/21. Thus, the gate electrode 5 composed of the gate oxide film 2, the polysilicon film 3, and the tungsten silicon film 4 is formed.
Is formed. Next, the resist film 10 is removed. Next, using the gate electrode 5 as a mask, the impurity is implanted into the semiconductor substrate 1 under the condition that the impurity is not implanted immediately below the gate electrode 5. Here, phosphorus is applied at 70 KeV.
Implantation of 5 × 10 ¹³ / cm ^{2 is performed} to form the low concentration impurity region 7 (FIG. 4B).

Next, a TEOS 6a having a thickness of about 3000 angstroms is laminated using, for example, a CVD method (FIG. 4C). Next, anisotropic etching of the TEOS 6a is performed. At this time, the conditions of the etching gas are, for example, CHF ₃ / CF ₄ / Ar = 30/3/55 to form the sidewall 6 (FIG. 4D). In this case, width h ₁ of one of the side wall 6 is 0.25 to 0.
It will be formed at 3 microns.

Next, the gate electrode 5 and the side wall 6
Is implanted into the semiconductor substrate 1 under the condition that the impurity is not implanted immediately below the gate electrode 5 and the side wall 6 using the mask as a mask. Here, 4 × 10 ¹⁵ / cm ^{2 is} implanted with arsenic at 40 KeV to form the high-concentration impurity region 8, and the LDD structure 9 including the low-concentration impurity region 7 and the high-concentration impurity region 8 is formed. (FIG. 3).

[0007]

Since the conventional semiconductor device is configured as described above, in order to form the LDD structure 9, the TEOS 6a is laminated thickly and etched to form the side wall 6. This sidewall 6
Since each impurity is implanted by using each shape before and after the formation of
A step of stacking and etching S6a is required.
Further, there is a problem that a large amount of foreign matter is generated during the etching of the TEOS 6a.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor device having an LDD structure capable of reducing the number of steps and reducing generation of foreign matters, and a method of manufacturing the semiconductor device. With the goal.

[0009]

Means for Solving the Problems Claim 1 according to the present invention.
The semiconductor device includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and having an upper end width smaller than a lower end width. A low-concentration impurity region formed on the outer side; and a second impurity formed on the outer side from a position with respect to the lower end of the gate electrode of the semiconductor substrate and higher than the first impurity concentration of the low-concentration impurity region. And a high-concentration impurity region having a high concentration.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming an oxide film on a semiconductor substrate, laminating a conductive film thereon, applying a resist on the conductive film, and patterning. A resist film is formed, and the first impurity is implanted into a position of the semiconductor substrate with respect to a lower portion of the resist film at an energy that does not allow the first impurity to reach the position.
A low-concentration impurity region is formed outward from the position with respect to the end of the resist film. Then, using the resist film as a mask, the conductive film and the oxide film are etched under etching conditions such that the width of the upper end is equal to the width of the resist film, and the width of the lower end is larger than the width of the upper end. An electrode is formed, and a second impurity is implanted into the semiconductor substrate at a position with respect to a lower portion of the gate electrode with an energy that does not reach the second impurity. And forming a high-concentration impurity region having a second impurity concentration higher than the first impurity concentration of the low-concentration impurity region.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the etching conditions are set by combining an anisotropic etching gas and an isotropic etching gas. .

According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor device according to the third aspect, when the conductive film is formed of a tungsten silicon film, an etching gas flow ratio as an etching condition is SF ₆ / Cl. ₂ / F ₃₂ = 8/8
0/15 to 30.

According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor device according to the third aspect, when the conductive film is formed of a polysilicon film, the etching gas flow ratio as an etching condition is HBr / Cl _2. / O ₂ = 50-100 /
35/5.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a configuration of a semiconductor device having an LDD structure according to the first embodiment. In the figure, 1
1 is a semiconductor substrate made of, for example, silicon, 12 is a gate oxide film formed on the semiconductor substrate 11, and 13 and 14 are a polysilicon film and a tungsten silicon film as a conductive film sequentially laminated on the gate oxide film 12. is there.
The gate oxide film 12 and the polysilicon film 13
And the tungsten silicon film 14 to form the gate electrode 1
5 are formed. The gate electrode 15 is formed such that the width of the upper end is shorter than the width of the lower end. 16 is a low-concentration impurity region, 17 is a high-concentration impurity region, and 18 is an LDD structure formed by these two impurity regions 16 and 17.

Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention configured as described above will be described with reference to FIGS.
This will be described with reference to FIG. First, the upper surface of the semiconductor substrate 11 is oxidized to form a gate oxide film 12a. Next, a polysilicon film 13a having a thickness of about 1000 angstroms is laminated on the gate oxide film 12a by using, for example, a CVD method. Next, a tungsten silicon film 14a having a thickness of about 1000 angstroms is laminated using, for example, a PVD method. Next, a resist is applied on the tungsten silicon film 14a and patterned to form a resist film 19.

Next, a resist film 19 on the semiconductor substrate 11 is formed.
In order to prevent, for example, phosphorus as the first impurity from reaching the position on the lower portion (the impurity is diffused after being injected into the semiconductor substrate 11, so that the impurity slightly enters the position on the lower portion of the resist film 19. Since the same operation is performed for other impurities, the description is omitted below). In addition, the impurity is implanted so as to reach the semiconductor substrate 11 outside the position with respect to the end of the resist film 19.
Therefore, it is necessary to take the thickness of the polysilicon film 13a and the tungsten silicon film 14a into consideration as compared with the conventional case. Conventionally, it is performed at 70 KeV, and the projection range of phosphorus in the semiconductor substrate 11 is 855 angstroms. This time, the thickness of the polysilicon film 13a and the thickness of the tungsten silicon film 14a were added to this.
It is necessary to implant with energy having a projection range of 2855 angstroms or more. Therefore, here, implantation is performed at 300 KeV having a projection range of 3812 angstroms.

Next, in order to prevent phosphorus from reaching the position of the semiconductor substrate 11 below the resist film 19, as described above, when phosphorus is implanted at 300 KeV, 30
When injected at 0 KeV, the projected range is 3812 Å, and the standard deviation is 1017 Å, 3
A thickness of 6863 angstroms, which is doubled (to take into account manufacturing variations) is required. Therefore, the thickness of the resist film 19 must be equal to or more than 4863 angstroms, excluding the thickness of the polysilicon film 13a and the tungsten silicon film 14a from the thickness of 6863 angstroms. By setting such conditions and implanting 2.5 × 10 ¹³ / cm ^{2 of} phosphorus, the low concentration impurity region 16 is formed (FIG. 2A).

Next, etching is performed using the resist film 19 as a mask. At this time, by combining an anisotropic etching gas and an isotropic etching gas as etching conditions, etching is performed in a shape in which a lower width is larger than an upper width. For example, when etching the tungsten silicon film 14a, Cl ₂ as an anisotropic etching gas and F ₃₂ (CH ₂ F ₂ ) as an isotropic etching gas are combined, and an etching gas flow ratio is SF ₆ / Cl 2. ₂ / F ₃₂ = 8/80/15 to 30. Here, for example, etching gas: S
F ₆ : 8 sccm, Cl ₂ : 80 sccm, F ₃₂ : 15 s
Ccm, gas pressure: 0.010 Torr, microwave power: 190 mA, RF power: 15 W, cooling gas flow rate (helium gas): 5 sccm.

Next, for example, when the polysilicon film 13a and the gate oxide film 12a are etched in the same manner as described above,
And Cl ₂ as an anisotropic etching gas, combining the HB ₂ as isotropic etching gas, an etching gas flow rate ratio _{HBr / Cl 2 / O 2 =} 50~100 / 35 /
It may be set to 5. Here, for example, etching gas: H
Br: 50 sccm, Cl ₂ : 35 sccm, O ₂ : 5 s
The etching is performed under the following conditions: ccm, gas pressure: 0.010 Torr, microwave power: 160 mA, RF power: 25 W, and cooling gas flow rate (helium gas): 5 sccm.

When the range of the ratio of the gas corresponding to the isotropic etching gas in the above-mentioned etching gas flow rate ratio is less than the minimum value, the difference between the upper width and the lower width disappears. When the value is equal to or more than the maximum value, the difference between the upper width and the lower width becomes unnecessarily large.

By etching using the resist film 19 as a mask under the conditions described above, the gate electrode 15 whose upper end width is shorter than the lower end width is formed.
(B)). Of the thus formed gate electrode 15, while the difference h ₂ of the width of the lower end of the upper end, as well as the width h ₁ of one of the conventional side walls 6, for example, 0.25
It will be formed at 0.3 microns.

Next, the resist film 19 is removed. next,
4 × 10 ¹⁵ / cm ^{2 is} implanted into the semiconductor substrate 11 at a position below the gate electrode 15 at an energy at which arsenic, for example, as a second impurity does not reach, at 40 KeV to form a high-concentration impurity region 17. As a result, an LDD structure 18 including the high-concentration impurity regions 16 and the high-concentration impurity regions 17 is formed (FIG. 1).

In the semiconductor device of the first embodiment configured as described above, since the width of the upper end of the gate electrode 15 is formed smaller than the width of the lower end, the sidewall 6 is formed as in the conventional case. Without this, the LDD structure 18 can be formed. Therefore, the number of steps can be reduced, and the generation of foreign substances can be reduced.

In the first embodiment, the gate electrode 15
Although an example in which the conductive film is formed in two layers has been described, the present invention is not limited to this.
It is needless to say that the film can be similarly formed by setting the etching conditions for each film, that is, the conditions such that the upper end width is the same as the width of the resist film and the upper end width is shorter than the lower end width.

[0025]

As described above, according to the first aspect of the present invention, a semiconductor substrate and a gate electrode formed on the semiconductor substrate via a gate oxide film and having an upper end width smaller than a lower end width are provided. A low-concentration impurity region formed outward from a position of the semiconductor substrate relative to an end of the upper end of the gate electrode;
And a high-concentration impurity region having a second impurity concentration higher than the first impurity concentration of the low-concentration impurity region, the semiconductor substrate being formed outward from a position with respect to the lower end of the gate electrode. By utilizing the shape of the gate electrode, the low concentration impurity region and the high concentration
A semiconductor device that can be formed into a structure can be provided.

According to a second aspect of the present invention, an oxide film is formed on a semiconductor substrate, and a conductive film is laminated thereon.
A resist is applied on the conductive film, patterned to form a resist film, and the first impurity is implanted into the semiconductor substrate at a position below the resist film with energy that does not reach the first impurity. Then, a low-concentration impurity region is formed outward from the position with respect to the end of the resist film. Then, using the resist film as a mask, the conductive film and the oxide film are etched under etching conditions such that the width of the upper end is equal to the width of the resist film, and the width of the lower end is larger than the width of the upper end. An electrode is formed, and a second impurity is implanted into the semiconductor substrate at a position with respect to a lower portion of the gate electrode with an energy that does not reach the second impurity. Forming a high-concentration impurity region having a second impurity concentration higher than the first impurity concentration of the low-concentration impurity region. Therefore, by utilizing the shape of the gate electrode, the low-concentration impurity region and the high-concentration impurity region can be formed. It is possible to provide a method for manufacturing a semiconductor device which can be formed into an LDD structure.

According to a third aspect of the present invention, in the second aspect, the etching condition is set by combining an anisotropic etching gas and an isotropic etching gas, so that the width of the upper end of the gate electrode is set. It is possible to provide a method for manufacturing a semiconductor device, which can easily adjust the formation of the semiconductor device so as to be smaller than the width of the lower end.

According to a fourth aspect of the present invention, in the third aspect, when the conductive film is formed of a tungsten silicon film, the etching gas flow ratio as an etching condition is SF ₆ / Cl ₂ / F ₃₂ = Since the ratio is set to 8/80/15 to 30, it is possible to provide a method of manufacturing a semiconductor device in which a gate electrode having an upper end width smaller than a lower end width can be formed reliably.

According to a fifth aspect of the present invention, in the third aspect, when the conductive film is formed of a polysilicon film, the etching gas flow rate ratio as an etching condition is H.
Since Br / Cl ₂ / O ₂ = 50 to 100/35/5, it is possible to provide a method of manufacturing a semiconductor device that can reliably form a gate electrode having an upper end width smaller than a lower end width. Becomes

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 3;

[Explanation of symbols]

Reference Signs List 11 semiconductor substrate, 12 gate oxide film, 13 polysilicon film, 14 tungsten silicon film, 15 gate electrode, 16 low concentration impurity region, 17 high concentration impurity region, 18 LDD structure, 19 resist film.

Claims (5)

[Claims] A semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and having an upper end width smaller than a lower end width; and an upper end end of the gate electrode of the semiconductor substrate. A low-concentration impurity region formed outward from a position with respect to the first region, and a first impurity concentration of the low-concentration impurity region formed outward from a position with respect to an end of a lower end of the gate electrode of the semiconductor substrate. A high-concentration impurity region having a higher second impurity concentration. 2. A step of forming an oxide film on a semiconductor substrate and laminating a conductive film thereon, a step of applying a resist on the conductive film and patterning the same to form a resist film,
The energy of the first impurity does not reach the position of the semiconductor substrate below the resist film.
Implanting impurities, forming a low-concentration impurity region outward from the position of the semiconductor substrate with respect to the end of the resist film, using the resist film as a mask, the conductive film and the oxide film, A step of forming a gate electrode by etching under an etching condition such that the width of the upper end is the same as the width of the resist film, and the width of the lower end is larger than the width of the upper end; The second impurity is implanted at an energy at which the second impurity does not reach the position with respect to the lower portion of the gate electrode, and the semiconductor substrate is positioned outward from the position with respect to the end of the gate electrode.
A second impurity concentration higher than the first impurity concentration in the low concentration impurity region;
Forming a high-concentration impurity region having a high impurity concentration. 3. The method according to claim 2, wherein the etching conditions are set by combining an anisotropic etching gas and an isotropic etching gas. 4. The method according to claim 1, wherein when the conductive film is formed of a tungsten silicon film, an etching gas flow ratio as an etching condition is SF ₆ / Cl ₂ / F ₃₂ = 8/80/15 to 30. Item 4. The method for manufacturing a semiconductor device according to Item 3. 5. When the conductive film is formed of a polysilicon film, an etching gas flow rate ratio as an etching condition is H.
_{Br / Cl 2 / O 2 =} 50~100 / 35/5 and to a method of manufacturing a semiconductor device according to claim 3, wherein a was.