CN114267639A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN114267639A CN114267639A CN202111467524.8A CN202111467524A CN114267639A CN 114267639 A CN114267639 A CN 114267639A CN 202111467524 A CN202111467524 A CN 202111467524A CN 114267639 A CN114267639 A CN 114267639A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 64
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 60
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 41
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 41
- 125000006850 spacer group Chemical group 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 230000010354 integration Effects 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 7
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
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- 229910052786 argon Inorganic materials 0.000 description 2
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate comprising a high pressure region and a low pressure region; forming a side wall material layer; forming a patterned photoresist layer, and removing the partial thickness of the side wall material layer of the second gate layer in the low-voltage area by taking the patterned photoresist layer as a mask; and etching the side wall material layer to form the side wall. The method takes the patterned photoresist layer as a mask, protects the side wall material layer on the side surface of the first gate layer in the high-voltage area, and removes the side wall material layer with partial thickness on the side surface of the second gate layer in the low-voltage area; therefore, when the side wall is formed by etching the side wall material layer, the thickness of the side wall of the high-voltage area is larger than that of the side wall of the low-voltage area, and meanwhile, the requirement that the high-voltage element needs the side wall with larger thickness and the low-voltage element needs the side wall with smaller thickness when the device is integrated is met; the integration feasibility of the high-voltage element and the deep submicron device is greatly improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
In non-standard logic processes of integrated circuits, High Voltage (HV) devices and deep sub-micron (28-90 nm) CMOS devices (including Low Voltage (LV) devices, for example) are often integrated together, i.e., integrated into the same semiconductor device. The high voltage device and the low voltage device have different performance requirements, which results in a large difference in device structure requirements. With standard logic processes, the performance of high voltage devices is often limited. The high-voltage element needs a side wall with larger thickness due to high voltage requirement; the low voltage components require device speed and require a spacer with a smaller thickness, which makes integration and manufacturing of the semiconductor device difficult.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, the thickness of a side wall of a high-voltage area of the formed semiconductor device is larger than that of a side wall of a low-voltage area, and the integration feasibility of a high-voltage element and a deep submicron device is improved.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate comprising a high pressure region and a low pressure region; a first gate layer is formed above the substrate in the high-voltage area, and a second gate layer is formed above the substrate in the low-voltage area;
forming a side wall material layer, wherein the side wall material layer at least covers the side face of the first gate layer and the side face of the second gate layer;
forming a patterned photoresist layer, wherein the patterned photoresist layer at least covers the side wall material layer positioned on the side surface of the first gate layer and at least exposes the side wall material layer positioned on the side surface of the second gate layer;
removing the side wall material layer with partial thickness on the side face of the second gate layer by taking the patterned photoresist layer as a mask;
removing the patterned photoresist layer;
and etching the side wall material layer to form a side wall, wherein the side wall comprises the side wall material layer positioned on the surface of the side wall of the first gate layer and the side wall material layer positioned on the surface of the side wall of the second gate layer and having partial thickness.
Further, the side wall material layer comprises any one or a combination of more than two of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, a silicon carbide layer and a polysilicon layer.
Further, forming the side wall material layer specifically includes: and sequentially forming a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer at least covering the side surface of the first gate layer and the side surface of the second gate layer.
Further, removing the partial thickness of the sidewall spacer material layer on the side of the second gate layer includes: and etching to remove the second silicon oxide layer positioned on the side surface of the second gate layer, and reserving the first silicon oxide layer and the silicon nitride layer positioned on the side surface of the second gate layer.
Furthermore, the sidewall spacer of the high-voltage region includes the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer, which are located on the side surface of the first gate layer, and the sidewall spacer of the low-voltage region includes the first silicon oxide layer and the silicon nitride layer, which are located on the surface of the sidewall of the second gate layer.
Further, etching the side wall material layer to form a side wall specifically includes:
and etching the second silicon oxide layer by adopting an etching process with a high selection ratio of the silicon oxide layer to the silicon nitride layer, and only reserving the second silicon oxide layer on the side wall of the first gate layer.
Further, after etching the second silicon oxide layer, the method further includes:
and etching the silicon nitride layer by adopting an etching process with a high selection ratio of the silicon nitride layer to the silicon oxide layer, and only remaining the silicon nitride layer on the side wall of the first gate layer and the side wall of the second gate layer.
The present invention also provides a semiconductor device comprising:
a substrate comprising a high pressure region and a low pressure region; a first gate layer is formed above the substrate in the high-voltage area, and a second gate layer is formed above the substrate in the low-voltage area;
and the side wall covers the side face of the first gate layer and the side face of the second gate layer, and the thickness of the side wall, which is positioned on the side face of the first gate layer in the high-voltage area, is greater than that of the side wall, which is positioned on the side face of the second gate layer in the low-voltage area.
Further, the side wall includes any one or a combination of two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, a silicon carbide layer and a polysilicon layer.
Furthermore, the side wall located in the high-voltage region includes the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer located on the side surface of the first gate layer, and the side wall located in the low-voltage region includes the first silicon oxide layer and the silicon nitride layer located on the surface of the side wall of the second gate layer.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate comprising a high pressure region and a low pressure region; a first gate layer is formed above the substrate in the high-voltage area, and a second gate layer is formed above the substrate in the low-voltage area; forming a side wall material layer, wherein the side wall material layer at least covers the side face of the first gate layer and the side face of the second gate layer; forming a patterned photoresist layer, wherein the patterned photoresist layer at least covers the side wall material layer positioned on the side surface of the first gate layer and at least exposes the side wall material layer positioned on the side surface of the second gate layer; removing the side wall material layer with partial thickness on the side face of the second gate layer by taking the patterned photoresist layer as a mask; removing the patterned photoresist layer; and etching the side wall material layer to form a side wall, wherein the side wall comprises the side wall material layer positioned on the surface of the side wall of the first gate layer and the side wall material layer positioned on the surface of the side wall of the second gate layer and having partial thickness.
The patterned photoresist layer is used as a mask, the side wall material layer on the side face of the first gate layer in the high-voltage area is protected, and meanwhile, the side wall material layer with partial thickness on the side face of the second gate layer in the low-voltage area is removed; adding a photomask to form a patterned photoresist layer, and removing the side wall material layer with partial thickness on the side surface of the second gate layer in the low-voltage area; in this way, when the sidewall material layer is etched to form the sidewall, the sidewall on the side of the first gate layer in the high-voltage region is approximately (slightly lost during etching) the sidewall material layer with the whole thickness, and the sidewall on the side of the second gate layer in the low-voltage region is approximately the sidewall material layer with the residual thickness (the thickness left after removing the sidewall material layer with the partial thickness on the side of the second gate layer by using the patterned photoresist layer as the mask); therefore, the thickness of the side wall of the high-voltage area is larger than that of the side wall of the low-voltage area, and the requirement that the side wall with larger thickness is needed by a high-voltage element due to high voltage requirement during device integration is met; the low-voltage element requires the speed of the device and needs a side wall with smaller thickness; by increasing limited cost, the feasibility of integrating high-voltage elements and deep submicron devices is greatly improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a semiconductor device according to an embodiment of the present invention after a substrate is provided.
Fig. 3 is a schematic view of the semiconductor device manufacturing method according to the embodiment of the invention after a spacer material layer is formed.
Fig. 4 is a schematic diagram of the manufacturing method of the semiconductor device according to the embodiment of the invention after the spacer material layer with partial thickness in the low-pressure region is etched.
Fig. 5 is a schematic diagram illustrating the method for manufacturing a semiconductor device according to the embodiment of the invention after removing the patterned photoresist layer.
Fig. 6 is a schematic view of the semiconductor device manufacturing method according to the embodiment of the invention after forming the side wall.
Fig. 7 is a schematic diagram of a source and drain formed by the method for manufacturing a semiconductor device according to the embodiment of the present invention.
Wherein the reference numbers are as follows:
10-a substrate; i-high pressure region; II-low pressure area; 11-a first gate oxide layer; 12-a first gate layer; 13-a second gate oxide layer; 14-a second gate layer; 15-side wall material layer; 15 a-a first silicon oxide layer; 15 b-a silicon nitride layer; 15 c-a second silicon dioxide layer; 16-a photoresist layer; STI-shallow trench isolation; 151-side wall; 152-side walls; s1-a first source region; d1-a first drain region; s2-a second source region; d2-a second drain region.
Detailed Description
The embodiment of the invention provides a manufacturing method of a semiconductor device. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 1, including:
s1, providing a substrate which comprises a high-pressure area and a low-pressure area; a first gate layer is formed above the substrate in the high-voltage area, and a second gate layer is formed above the substrate in the low-voltage area;
s2, forming a side wall material layer, wherein the side wall material layer at least covers the side face of the first gate layer and the side face of the second gate layer;
s3, forming a patterned photoresist layer, wherein the patterned photoresist layer at least covers the side wall material layer on the side surface of the first gate layer and at least exposes the side wall material layer on the side surface of the second gate layer;
s4, removing the side wall material layer with partial thickness on the side face of the second gate layer by taking the patterned photoresist layer as a mask;
s5, removing the patterned photoresist layer;
and S6, etching the side wall material layer to form a side wall, wherein the side wall comprises the side wall material layer positioned on the surface of the side wall of the first gate layer and the side wall material layer positioned on the surface of the side wall of the second gate layer and having partial thickness.
The steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention will be described with reference to fig. 2 to 7.
As shown in fig. 2, a substrate 10 is provided, which includes a high pressure region I and a low pressure region II; base ofA first gate oxide layer 11 and a first gate layer 12 are formed on the substrate 10 in the high-voltage region I, and a second gate oxide layer 13 and a second gate layer 14 are formed on the substrate 10 in the low-voltage region II; lightly doping the substrate at two sides of the first gate layer 12 in the high-voltage region to form a first source region S1And a first drain region D1(ii) a Lightly doping the substrate at two sides of the second gate layer 14 in the low-voltage region to form a second source region S2And a second drain region D2Also known as Lightly Doped Drain (LDD) implant. And a Shallow Trench Isolation (STI) is arranged between the high-voltage area I and the low-voltage area II. The thickness of the first gate oxide layer 11 located in the high voltage region I is greater than the thickness of the second gate oxide layer 13 located in the low voltage region II. The first gate oxide layer 11 and the second gate oxide layer 13 may be silicon dioxide. The first gate layer 12 and the second gate layer 14 may be polysilicon material, or may be metal material, for example, high-k (dielectric constant) metal material. In a specific embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or the like; alternatively, the material of the substrate 10 may include other materials such as group iii-v compounds such as gallium arsenide. The substrate may be selected as desired by those skilled in the art, and thus the type of substrate should not limit the scope of the present invention.
As shown in fig. 3, forming a sidewall spacer material layer 15, where the sidewall spacer material layer 15 covers the upper surface and the side surface of the first gate layer 12 in the high voltage region, and the upper surface and the side surface of the second gate layer 13 in the low voltage region; the spacer material layer 15 is usually a dielectric material, and the spacer material layer 15 may include any one or a combination of two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, a silicon carbide layer, and a polysilicon layer. Illustratively, an ONO stacked structure of a first silicon oxide layer 15a, a silicon nitride layer 15b and a second silicon oxide layer 15c in this order from below. The sidewall material layer 15 may further cover the first source region S of the high voltage region I1And a first drain region D1A second source region S of the low voltage region II2And a second drain region D2And Shallow Trench Isolation (STI). The sidewall material layer 15 can be grown by thermal oxidation, Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).
As shown in fig. 4, a patterned photoresist layer 16 is formed, and the patterned photoresist layer 16 covers the high voltage region I and exposes the low voltage region II; specifically, the surface of the sidewall material layer 15 in the high-voltage region I is covered, and the surface of the sidewall material layer in the low-voltage region II is exposed. And removing the partial thickness of the sidewall material layer 15 on the side surface of the second gate layer 13 in the low-voltage region II by using the patterned photoresist layer 16 as a mask, for example, removing the second silicon oxide layer 15c on the side surface of the second gate layer 13 in the low-voltage region II, and removing the second silicon oxide layer 15c by using an HF acid wet etching method.
As shown in fig. 4 and 5, the patterned photoresist layer 16 is removed, and an ashing process may be used.
As shown in fig. 6, a sidewall is formed, the sidewall material layer may be etched by a maskless etching process to form a sidewall, and the remaining sidewall material layer after etching is used as the sidewall.
Specifically, a plasma dry etching process with a high selection ratio of the silicon oxide layer and the silicon nitride layer is adopted to etch the second silicon oxide layer 15 c; illustratively, the etching conditions are: the gas pressure is 30-60 mtor, the power is 300-500W, and the etching gas is mainly C4F6Or C4F8Mainly, Ar and O can be doped in an auxiliary way2Etc. to appropriately increase the etch rate. The selection ratio of the silicon oxide layer to the silicon nitride layer is more than or equal to 10: 1, the silicon nitride layer 15b is hardly lost while the second silicon oxide layer 15c is etched. Specifically, the second silicon oxide layer 15c located right above the first gate layer 12 is removed by etching, the second silicon oxide layer 15c located above the substrate 10 and the STI is removed by etching, the second silicon oxide layer 15c located on the sidewall of the first gate layer 12 is left, and a little etching is performed on the top of the second silicon oxide layer 15c located on the sidewall of the first gate layer 12.
Next, the silicon nitride layer 15b is etched by using an etching process having a high selection ratio of the silicon nitride layer to the silicon oxide layer. The silicon nitride layer 15b may be etched using a fluorocarbon-based gas and oxygen, and a diluent gas such as argon gas that can form a stable plasma may be introduced based on the fluorocarbon-based gas and oxygen. The fluorocarbon-based gas may be CF4And CH2F2Group (2)Or CF of4And CH3Combinations of F or CH alone3F. Illustratively, by adjusting CH3F and O2The high selectivity ratio of the obtained silicon nitride to the obtained silicon oxide is 16: 1-22: 1. Exemplary, CH3F and O2The ratio of (A) to (B) is 3:2 to 3:1, and the selectivity ratio of silicon nitride to silicon oxide is higher, for example, 16:1 to 22: 1. Specifically, the silicon nitride layer 15b located right above the first gate layer 12 and the second gate layer 14 is removed by etching, the silicon nitride layer 15b located above the substrate 10 is removed by etching, the silicon nitride layer 15b located on the sidewall of the first gate layer 12 and the sidewall of the second gate layer 14 is left, and a little etching is performed on the top of the silicon nitride layer 15b located on the sidewall of the first gate layer 12 and the sidewall of the second gate layer 14.
And then, etching to remove the first silicon oxide layer 15a located right above the first gate layer 12 and the second gate layer 14, wherein the first silicon oxide layer 15a located above the substrate 10 is also consumed to a certain thickness in the etching process, the first silicon oxide layer 15a located above the substrate 10 can be kept to a certain thickness, the first silicon oxide layer 15a located on the side wall of the first gate layer 12 and the side wall of the second gate layer 14 is left, the top of the first silicon oxide layer 15a located on the side wall of the first gate layer 12 and the side wall of the second gate layer 14 is slightly etched, and the rest of the etched spacer material layer is used as a spacer.
Illustratively, the sidewall 151 of the high-voltage region includes a first silicon oxide layer 15a, a silicon nitride layer 15b and a second silicon oxide layer 15c on the sidewall surfaces of the first gate layer 12 and the first gate oxide layer 11, that is, the sidewall of the high-voltage region is an ONO stacked structure; the sidewall 152 of the low voltage region includes a first silicon oxide layer 15a and a silicon nitride layer 15b located ON the surfaces of the sidewalls of the second gate electrode layer 14 and the second gate oxide layer 13, that is, the sidewall 152 of the low voltage region is an ON stacked structure, and sidewalls with different thicknesses in a High Voltage (HV) region and a Low Voltage (LV) region are formed at the same time. The side wall prevents the source and drain from being penetrated through due to the fact that higher-dose source and drain injection is too close to a channel when a source and a drain are formed subsequently, and therefore device failure and yield are reduced. In addition, in the above case, by controlling the thickness of the second silicon oxide layer 15c, the thickness difference between the high-voltage region side wall and the low-voltage region side wall can be accurately controlled, so that the performance of the device can be more accurately controlled. Meanwhile, the maskless etching is adopted subsequently, so that the cost is effectively saved.
As shown in fig. 7, source/drain electrodes are formed, and source/drain region ion implantation is performed on both sides of the sidewall 151 of the high voltage region and both sides of the sidewall 152 of the low voltage region to form a source and a drain of the high voltage region and a source and a drain of the low voltage region, respectively.
In summary, the present invention provides a semiconductor device and a method for fabricating the same. The patterned photoresist layer is used as a mask, the side wall material layer on the side face of the first gate layer in the high-voltage area is protected, and meanwhile, the side wall material layer with partial thickness on the side face of the second gate layer in the low-voltage area is removed; adding a photomask to form a patterned photoresist layer, and removing the side wall material layer with partial thickness on the side surface of the second gate layer in the low-voltage area; in this way, when the side wall material layer is etched to form the side wall, the side wall of the side face of the first gate layer in the high-voltage region is approximately the side wall material layer with the whole thickness, and the side wall of the side face of the second gate layer in the low-voltage region is approximately the side wall material layer with the residual thickness; therefore, the thickness of the side wall of the high-voltage area is larger than that of the side wall of the low-voltage area, and the requirement that the side wall with larger thickness is needed by a high-voltage element due to high voltage requirement during device integration is met; the low-voltage element requires the speed of the device and needs a side wall with smaller thickness; by increasing limited cost, the feasibility of integrating high-voltage elements and deep submicron devices is greatly improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate comprising a high pressure region and a low pressure region; a first gate layer is formed above the substrate in the high-voltage area, and a second gate layer is formed above the substrate in the low-voltage area;
forming a side wall material layer, wherein the side wall material layer at least covers the side face of the first gate layer and the side face of the second gate layer;
forming a patterned photoresist layer, wherein the patterned photoresist layer at least covers the side wall material layer positioned on the side surface of the first gate layer and at least exposes the side wall material layer positioned on the side surface of the second gate layer;
removing the side wall material layer with partial thickness on the side face of the second gate layer by taking the patterned photoresist layer as a mask;
removing the patterned photoresist layer;
and etching the side wall material layer to form a side wall, wherein the side wall comprises the side wall material layer positioned on the surface of the side wall of the first gate layer and the side wall material layer positioned on the surface of the side wall of the second gate layer and having partial thickness.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the spacer material layer comprises any one or a combination of two or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, a silicon carbide layer, and a polysilicon layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the side wall material layer specifically comprises: and sequentially forming a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer at least covering the side surface of the first gate layer and the side surface of the second gate layer.
4. The method for manufacturing the semiconductor device according to claim 3, wherein the removing of the partial thickness of the spacer material layer located on the side surface of the second gate layer comprises: and etching to remove the second silicon oxide layer positioned on the side surface of the second gate layer, and reserving the first silicon oxide layer and the silicon nitride layer positioned on the side surface of the second gate layer.
5. The method for manufacturing the semiconductor device according to claim 4, wherein the sidewall spacer of the high-voltage region comprises the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer on the side surface of the first gate layer, and the sidewall spacer of the low-voltage region comprises the first silicon oxide layer and the silicon nitride layer on the surface of the sidewall of the second gate layer.
6. The method for manufacturing the semiconductor device according to claim 3, wherein the etching the side wall material layer to form the side wall specifically comprises:
and etching the second silicon oxide layer by adopting an etching process with a high selection ratio of the silicon oxide layer to the silicon nitride layer, and only reserving the second silicon oxide layer on the side wall of the first gate layer.
7. The method for manufacturing a semiconductor device according to claim 6, further comprising, after etching the second silicon oxide layer:
and etching the silicon nitride layer by adopting an etching process with a high selection ratio of the silicon nitride layer to the silicon oxide layer, and only remaining the silicon nitride layer on the side wall of the first gate layer and the side wall of the second gate layer.
8. A semiconductor device, comprising:
a substrate comprising a high pressure region and a low pressure region; a first gate layer is formed above the substrate in the high-voltage area, and a second gate layer is formed above the substrate in the low-voltage area;
and the side wall covers the side face of the first gate layer and the side face of the second gate layer, and the thickness of the side wall, which is positioned on the side face of the first gate layer in the high-voltage area, is greater than that of the side wall, which is positioned on the side face of the second gate layer in the low-voltage area.
9. The semiconductor device according to claim 8, wherein the side wall comprises any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, a silicon carbide layer, and a polysilicon layer or a combination of two or more thereof.
10. The semiconductor device of claim 8, wherein the sidewall spacers in the high-voltage region comprise the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer on the sides of the first gate layer, and the sidewall spacers in the low-voltage region comprise the first silicon oxide layer and the silicon nitride layer on the surfaces of the sidewalls of the second gate layer.
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| CN117690927A (en) * | 2024-02-04 | 2024-03-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117690927A (en) * | 2024-02-04 | 2024-03-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117690927B (en) * | 2024-02-04 | 2024-06-07 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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