JPH1069541A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture processor improved in the using efficiency of a memory. SOLUTION: If a start address SA2 is specified by an X-Y space specifying signal Sxy, a selector 205 reads out a line pitch LP2 from a line pitch register 202, on the other hand, a selector 206 reads out a pixel size PS2 from a pixel size register 203. If the line pitch LP2 is outputted to a multiplier 207, the multiplier 207 multiplies the line pitch LP2 by a Y address Ay to generate 'LP2×Ay'. On the other hand, a multiplier 208 multiples the pixels size PS2 by an X address Ax to generate 'PS2×Ax'. If these multiplied results are added to each other by an adder 209, it comes to 'LP2×Ay+PS2×Ax'. In an adder 210, the start address SA2 is further added to the added result and thus the final output comes to 'SA2+LP2×Ay+PS2×Ax', so that a linear address LA is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for improving the use efficiency of a memory.

[0002]

2. Description of the Related Art Generally, when a graphic is displayed on a display by a computer, when drawing data indicating the graphic is generated by a CPU, the drawing data is temporarily stored in an image display memory. Then, the drawing data is sequentially read from the image display memory and displayed on the display. Incidentally, an image of one frame is represented by a set of pixels at each sample timing of drawing data.
For example, an image of 640 × 480 has a horizontal pixel number of 6
There are 40 and 480 vertical pixels. In this case, drawing data can be designated for each pixel using an XY address having one point on the screen as the origin. In the above example, if the origin is the upper left corner of the screen,
The X address (the horizontal address) of the pixel at the lower right corner of the screen is 639, and the Y address (the vertical address) is 479.

[0003]

Here, the image display memory is 1 megabyte (= 1024.times.1024.times.8 bits).
And the drawing data is composed of 8 bits / pixel. Assuming that an image of 640 × 480 in one frame is stored in the image display memory using the XY address, the drawing data is stored as shown in FIG. In the figure, frame # 1 is stored in storage area A, and claim # 2 is stored in storage area B. In this case, even if frame # 3 is to be stored, it cannot be stored because there is no large storage area.

FIG. 5 shows the storage area of the image display memory in units of lines. In the figure, the hatched portion is an area where no data is stored,
The storage area of the image display memory is not used continuously. Therefore, when drawing data is stored using the XY address, there is a problem that the use efficiency of the image display memory is low. In addition, the CPU accesses the memory using a continuous address generally called a linear address. Therefore, if the image display memory is managed using the XY address, there is a problem that the image display memory cannot be directly mapped to the memory space of the CPU.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides an image processing apparatus capable of improving the utilization efficiency of an image display memory and easily managing the image display memory by a CPU. The main purpose is.

[0006]

According to the first aspect of the present invention, there is provided an image processing apparatus for processing drawing data for each pixel constituting a screen. In each storage area using a continuous address, an area specifying means for generating an area specifying signal for specifying one of the storage areas to be accessed, and a horizontal for specifying a horizontal pixel position. Horizontal and vertical address generation means for generating a vertical address indicating an address and a pixel position in the vertical direction; start address storage means for storing a start address indicating a storage start position of the drawing data for each of the storage areas; A line pitch data storage method for storing line pitch data indicating a data length of one line of the drawing data for each storage area. When the pixel size data for instructing the number of bits per pixel of the drawing data,
Pixel size data storage means for storing for each storage area, the start address read from the start address storage means, the line pitch data storage means and the pixel size data storage means based on the area designation signal, A conversion unit that converts the horizontal and vertical addresses into the continuous addresses using the line pitch data and the pixel size data; and a memory access unit that accesses the memory using the continuous addresses. .

Further, according to the invention described in claim 2,
The conversion means LA = SA + LP × Ay + PS × Ax
(However, LA is the continuous address, SA is the start address, LP is the line pitch data, Ay is the vertical address, PS is the pixel size data, and Ax is the horizontal address.) Is generated.

[0008]

DETAILED DESCRIPTION OF THE INVENTION 1. Configuration of Embodiment Hereinafter, a configuration of an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a drawing processor, which receives drawing instructions for drawing a straight line or painting a figure from input means (not shown) such as a mouse, and generates drawing data GD in accordance with those instructions. . The drawing data GD is stored in each storage area of the image display memory 3 on a frame basis. Reference numeral 10 denotes an XY address generation unit provided inside the drawing processor 1, where an XY address Axy of the drawing data GD is provided.
Then, an XY space designation signal Sxy is generated. The XY space designation signal Sxy designates each recording area of the image display memory 3.

Reference numeral 2 denotes a memory access circuit for accessing the image display memory 3, in which an XY address-linear address converter 20 is provided.
There, the XY address Axy is converted to a linear address LA based on the XY space designation signal Sxy. In this case, since the XY space designation signal Sxy indicates a storage area, it is possible to generate the linear address LA using different parameters for each storage area. Various drawing data GD are continuously stored in each storage area of the image display memory 3 using the linear address LA thus generated. Therefore, the drawing data GD is not separately stored, and the utilization efficiency of the image display memory 3 is improved.

[0010] 2. XY address-linear address conversion
Processing Next, a description will be given of a process for converting the X-Y address Axy to the linear address LA. The XY address-linear address converter 20 generates a linear address LA according to the following arithmetic expression. LA = SA + LP * Ay + PS * Ax

In this arithmetic expression, Ax is an X address constituting an XY address Axy, and Ay is a Y address. In addition, SA is a start address, and indicates a head position where the drawing data GD to be accessed is stored, that is, a head address of each storage area.
LP is a line pitch, which indicates the data length of one line, that is, the address interval between a certain line and the next line in the image display memory 3. PS is a pixel size and indicates the number of bits per pixel. Normally, since the linear address LA is managed in byte units, it is basically 8 bits = 1 byte, 16 bits = 2 bytes, or 32 bits = 4 bytes.

Here, 1024 × 6 is stored in the image display memory 3.
If the frame # 1 composed of 40 and the frame # 2 composed of 640 × 480 are stored, the memory map is as shown in FIG. In addition, frame #
The pixel size of the drawing data GD related to 1 and 2 is 8 bits. In this case, the K-th frame # 1
If a pixel PK located at the head of a line (K is a natural number) is to be read, X indicating the pixel PK
The address Ax becomes “0”, and the Y address Ay becomes “K−
1 ". In this example, the start address SA is SA1 in the figure, and the line pitch LP is 1024 (= 102
4 x 1 byte). Then, by substituting these values into the above equation, the linear address LA of the pixel PK is obtained.
Is calculated. Next, when reading frame # 2, SA2 is used instead of start address SA1.
Also, the line pitch LP is 640 (= 640 × 1 byte)
Is used to generate the linear address LA.

When the frame size of the drawing data GD stored in each storage area is different or the pixel size PS is different, it is necessary to change the line pitch LP and the pixel size PS in the above equation. Also, since the start address SA differs for each storage area, it is necessary to change this point as well. For this reason, the XY address-linear address converter 20
A start address SA, a line pitch LP, and a pixel size PS are stored for each storage area. Then, these parameters are read out according to the storage area indicated by the XY space designation signal Sxy, and the above-mentioned arithmetic expression is executed.

[0014] 3. XY address-linear address conversion
Vessels Next, X-Y address - the structure of the linear address converter 20 with reference to FIG. 3 now be described. FIG. 3 is a circuit diagram of the XY address-linear address converter. In the figure, 201 is a start address register, 202 is a pitch register, and 203 is a pixel size register.
In these registers, a start address SA, a line pitch LP, and a pixel size PS corresponding to each storage area of the image display memory 3 are stored. Also,
Each of the registers 204 to 205 is a selector based on the XY space designation signal Sxy.
From 6, the start address SA, the line pitch LP, and the pixel size PS are read. As a result, the parameters in the above equation can be changed instantaneously.

The multiplier 207 multiplies the selected line pitch LP by the Y address Ay, and
8 is the selected pixel size PS and X address Ax
Is multiplied. These multiplication results are added by the adder 209, and the result and the selected start address SA are added again by the adder 210 to generate the linear address LA.

Next, the operation of the XY address-linear address converter 20 will be described with reference to FIG. Now, X
If the -Y space designation signal Sxy indicates # 2, the selector 205 reads the line pitch LP2 from the line pitch register 202, while the selector 206 reads the pixel size PS2 from the pixel size register 203. When the line pitch LP2 is output to the multiplier 207, the multiplier 207 multiplies the line pitch LP2 by the Y address Ay to generate “LP2 × Ay”. On the other hand, the multiplier 208 multiplies the pixel size PS2 by the X address Ax to generate “PS2 × Ax”. When these multiplication results are added by the adder 209, "LP2
× Ay + PS2 × Ax ”. Since the adder 210 further adds the start address SA2 to the addition result, the final output is “SA2 + LP2 × Ay + PS2 × A
x ", and the linear address LA can be obtained.

As described above, in this embodiment, XY
The start address SA, the line pitch LP, and the pixel size PS are stored in each register for each address space (for each storage area), and are read out by the XY space designation signal Sxy. The parameter corresponding to the XY space thus set can be changed instantaneously. As a result, the linear address LA can be generated at a high speed with a simple configuration, and the image speed of the computer can be improved. Further, since the image display memory 3 can be accessed by the linear address LA,
This memory can be mapped directly into the memory space of the CPU. Further, even if a plurality of claims of different sizes are required, they can be stored in the image display memory 3 continuously, so that the memory utilization efficiency can be effectively used.

[0018] 4. Modifications The present invention is not limited to the above-described embodiment, and various modifications are possible, for example, as follows. In the above embodiment, if the line pitch LP or the pixel size PS is limited to a power of 2, the multipliers 207, 2
A shifter circuit that performs a bit shift instead of 08 may be used. In the above embodiment, the start address SA, the line pitch LP, and the pixel size PS
Has been described as being stored in advance in each register. However, in order to correspond to a new display size, an empty space may be left in each register and data corresponding thereto may be added. In addition, as drawing data representing a three-dimensional figure, data called Z data indicating depth may be used in addition to normal data. In this case, normal drawing data may be stored in the storage area of the image display memory shown in FIG. 2 as frame # 1 and Z data as frame # 2.

[0019]

As described above, according to the present invention, since the drawing data can be continuously stored in the memory, the utilization efficiency of the memory can be improved. And can be easily controlled. Further, since parameters can be varied for each storage area, continuous addresses can be generated at high speed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a memory map of an image display memory according to the embodiment.

FIG. 3 is a block diagram of an XY address-linear address converter according to the embodiment.

FIG. 4 is a diagram showing a memory map of a conventional image display memory.

FIG. 5 is a diagram showing a memory map when a storage area of a conventional image display memory is expressed in units of lines.

[Explanation of symbols]

2 ... memory access circuit (memory access means), 3 ...
Image display memory (memory), 10... XY address generation unit (region specifying means, horizontal and vertical address generation means), 20
DESCRIPTION OF SYMBOLS 1 ... Start address register (start address storage means), 202 ... Line pitch register (line pitch data storage means), 203 ... Pixel size register (pixel size data storage means), 207, 208 ... Multiplier (conversion means), 209 210, adder (conversion means), GD, drawing data, Ax, X address (horizontal address), Ay, Y address (vertical address), Sxy, X
-Y space designation signal (area designation signal), LA: linear address (continuous address), SA: start address (start address).

Claims (2)

[Claims] 1. An image processing apparatus for processing drawing data for each pixel constituting a screen, comprising: a memory for storing a plurality of drawing data in each storage area using a continuous address; Area specifying means for generating an area specifying signal for specifying one area to be provided; horizontal and vertical address generating means for generating a horizontal address for specifying a horizontal pixel position and a vertical address for specifying a vertical pixel position; Start address storage means for storing a start address indicating a storage start position of the drawing data for each storage area; and line pitch data indicating a data length per line of the drawing data for each storage area. A line pitch data storage unit that stores the number of bits per pixel of the drawing data Pixel size data storing means for storing the size data for each of the storage areas; and read out from the start address storing means, the line pitch data storing means and the pixel size data storing means based on the area designating signal, respectively. Conversion means for converting the horizontal and vertical addresses into the continuous addresses using the start address, the line pitch data, and the pixel size data; and memory access means for accessing the memory by the continuous addresses. An image processing apparatus characterized by the above-mentioned. 2. The conversion means: LA = SA + LP × Ay + PS × Ax (where LA is the continuous address, SA is the start address, LP is the line pitch data, Ay is the vertical address, PS
The image processing apparatus according to claim 1, wherein the continuous address is generated by calculating the pixel size data and Ax (the horizontal address).