JPH10162162A - Image processor and image processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to paste arbitrary image information, which is being displayed on a screen to the surface of a three-dimensional graphic by generating a three-dimensional image obtained by sticking a three-dimensional image, stored in a memory, to the surface of a desired three-dimensional graphic and stored image in the memory. SOLUTION: Graphic A, which is a two-dimensional graphic, is pasted to the flank of graphic B, which is a three-dimensional graphic. For this process, a CPU 1 instructs the image A for a mapping process so as to constitute it on part (flank) of the graphic B, and this instruction is sent to a display control processor 2 through a bus 5. The display control processor 2 makes a raster scan on the image A and sends respective data to a DDA circuit part 3. The DDA circuit part 3 calculates the coordinates and density on a straight line (r) by pixels according to those respective data. The coordinates and density which are thus obtained are stored in a frame memory 4 and then displayed, so that the graphic having the graphic A pasted to one flank of the graphic B is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing system for displaying a gray-scale image on a display, and more particularly to an image processing system for displaying an image having a different brightness for each pixel due to the influence of illumination or the like. The present invention relates to an image processing device and an image processing system.

[0002]

2. Description of the Related Art In order to process a color image at high speed, Japanese Patent Application No. 59-30278, "Image memory access device"
Has a computing unit for each frame memory plane,
The method of processing in parallel is shown.

[0003]

The above-mentioned prior art does not take into account a wide calculation system for a grayscale image. For this reason, if a density conversion process of a grayscale image is to be performed, the host processor (CPU) needs to perform image conversion. Has to be recalculated, and the display cannot be changed in real time.

[0004] An application request for clarifying this problem will be described in more detail with reference to the drawings. As shown in FIG. 2, the left image data A is defined with shading on a two-dimensional plane. If this is applied to one side of a rectangular parallelepiped such as the right side and texture mapping processing is performed to form the image B, mapping is performed so that a density difference occurs between the rear and the front of the surface (or the rear and the front when viewed from the view side). Without (image conversion), it does not look like an actual event. Therefore, for example, the front is darkened and the rear is thinned.

[0005] In order to realize this processing, for example, for a pixel mapped backward, mapping is performed by multiplying the value of each pixel of the grayscale image on the secondary plane by 0.6. It is necessary to perform mapping by multiplying by 0.0 and to take an intermediate value of (0.6 to 1.0) during the mapping. As a result, the density at the rear becomes thinner than the original density on the two-dimensional plane. However, density conversion in such processing has conventionally been performed by a host processor, and real-time processing has not been easy.

An object of the present invention is to provide an image processing apparatus and an image processing system capable of attaching arbitrary image information displayed on a screen to the surface of a three-dimensional figure.

[0007]

An object of the present invention is to generate a memory for recording image information to be displayed and a three-dimensional image in which a two-dimensional image is pasted on the surface of a desired three-dimensional figure. In the image processing apparatus provided with image conversion means for storing, the image conversion means generates a three-dimensional image in which the three-dimensional image stored in the memory is pasted on the surface of a desired three-dimensional figure, and It is achieved by storing.

The object is to provide a display device, a memory for recording image information to be displayed on the display device, and a three-dimensional image in which a two-dimensional image is displayed on the surface of a desired three-dimensional figure. And an image conversion unit that stores the three-dimensional image stored in the memory on a surface of a desired three-dimensional figure, and generates the three-dimensional image in the memory. It is achieved by storing.

Image information to be displayed on the screen of a display device is usually displayed in a memory called a frame memory (which may be substituted by a main memory). The image information stored in the memory, that is, the displayed image information is pasted to the surface of the three-dimensional figure as a source image, and the resulting image information is stored in the memory. The three-dimensional image information to which the information has been pasted can be further pasted on the surface of the three-dimensional figure.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of an image processing system according to one embodiment of the present invention, and FIG.

In FIG. 3, a CPU 1 is a host processor, and instructs a display control processor 2 to convert an image or draw a figure via a bus 5. The display control processor 2 converts the contents instructed via the bus 5 into a DDA
Divided into units that can be processed by the circuit unit 3,
It instructs the DA circuit unit 3.

The DDA circuit section 3 calculates a gray scale value for each pixel and writes it to a frame memory (FM) 4 via a bus 7. The contents of FM4 are always refreshed on the display (not shown). Therefore, the operator can always see the created image in real time.

The above-described processing example shown in FIG. 3 will be briefly described based on the graphic example shown in FIG. FIG. 4 shows an example of converting the left A graphic into the right B graphic. The A figure is a two-dimensional figure, and the B figure is a three-dimensional figure, and a process of pasting the A figure on one side of the B figure is performed.

In this process, the CPU 1 first instructs a mapping process on the left A image so as to constitute a part of the B graphic as shown on the right. This instruction is bus 5
Via the display control processor 2.

The display control processor 2 raster scans the image A. For each raster scanning line, as shown by the scanning line 1 (ell) in FIG. 4, the starting point (S
X, SY), the coordinates (DX, DY) of the destination corresponding to the start point (SX, SY), and the brightness information I (0 ≦ I ≦ 1), and S
Displacement ΔSX, ΔX, Δ with the next point of X, DX, DY, I
Y, ΔI.

Here, the coordinates of the day stay (D
X, DY) is the corresponding value of the A graphic coordinate on the B graphic, S
The next point of X, DX, DY, I is the next scan point in the horizontal direction (X direction) on the scanning line l (for example, if the start point is the current scan point, the next scan point of the start point is In general, the scan pitch in the X direction is constant.)
There is ΔSX and ΔSY is unnecessary because there is no change in the Y coordinate in one scanning line l.
Exists because the scanning line 1 becomes a straight line r on the B figure, and not only the value of X but also the value of Y changes on the straight line r. Also, the start point a is a1 and the end point b is b
It becomes 1. Further, the scanning line 1 changes from the upper part of the figure to the lower part of the figure with a constant Y coordinate displacement. The number is predetermined.

The display control processor 2 stores the data SX, SY, I, DX, DY, .DELTA.SX, .DELTA.X, .DELTA.Y, .DELTA.
I is sent to the DDA circuit unit 3.

The DDA circuit section 3 calculates the coordinates and the density on the straight line r for each pixel based on these data.
When the coordinates and density thus obtained are stored in the frame memory 4 and then displayed, a figure is obtained in a state where it is pasted on one side of the figure B in FIG.

The embodiment of FIG. 1 will be described. DDA 31
A symmetric DDA is used. A functional diagram of the symmetric DDA is shown in FIG. Small values Δ are added one after another starting from a certain numerical value, and the integer part is output one after another for each added value. This output integer value is a converted value from the start point to the end point. FIG. 5 shows the function. Small value Δ for decimal part
Is added and embedded in place of the previous decimal value. The integer value at that time is output for each embedding. There are cases where the integer part is updated by embedding and cases where it is not updated. The case of being updated is a case where an integer value of 1 is obtained as a result of adding Δ to the decimal part, and the case of not being updated does not reach the integer value of 1 even if Δ is added to the decimal part. Is the case. The former is a carrier occurrence,
The latter is an example where no carry occurs.

Here, the starting points are SX, DX, DY, I
And the small value Δ is ΔSX, ΔX, ΔY, Δ
Each value of I is referred to. For SY, one arbitrary scan line
As for l, there is no change, Δ = 0, and the above operation is unnecessary. The processing of FIG. 5 is individually performed on the five data SX, DX, DY, and I, and the data update to the end point is individually performed on each of the five data.

The register 32 is composed of n plane registers 321, 322 to 32n. Each register 321-
32n are FIFO type registers. Each of the registers 321 to 32n has a capacity of 16 bits xm.

Here, n is the number of bits constituting one pixel, 16 bits is the number of bits transferred at one time, and m is the number of individual registers as FIFO. Therefore, m is a value that determines the capacity of the FIFO register. In many cases, n takes 4, 8, or 16, or the like. The greater the number n, the greater the number of gradations. There are also examples of 8 bits and 32 bits instead of 16 bits. Image data is input FI to the register 32 via the bus 6.

The selector 33 includes n selectors 331-33.
n. The selector 33 selects one of the output of the register 32 and the data read from the frame memory (FM) 4. This selection is performed by a selection signal. The selection signal selects the FO output of the register 32 when the address (SX, SY) indicates the address of the main memory, and selects the frame when the address (SX, SY) indicates the address of the frame memory. Select memory output (FM DATA via bus 7-2). The selectors 331 to 32n of the selector 33 are
~ 32n. The selectors 331 to 33n correspond to 16xn of the FM DATA output from the bus 7-2.

The source registers 34 and 35 have n
341-34n and 351-35n. These two source registers 34 and 35 are for 32 pixels and perform buffering of 16 pixels each.
The reason why the number of pixels is 32 is to generate data shifted by 16 pixels. Therefore, first, data is latched in the register 34, and then this data is sent to the register 35 for latching, and the register 34 is operated to latch new data.

The barrel shifter 36 is composed of n barrel shifters 361 to 36n. This barrel shifter 36
Has the function of shifting multiple bits at once.

The multiplier 37 includes 16 multipliers 37-1 to 37-3.
Consists of 7-16. Each of the multipliers 37-1 to 37-16 corresponds to one pixel. The multiplication is performed between the information I and each pixel data.

The write data buffer 38 is composed of n buffers 381 to 38n. This write control is performed based on the decoding result of the lower 4 bits of DX. This decoding is performed by the decoder 70.

The computing unit 39 is composed of n computing units (ALU).

The control circuit 71 performs DDA control. Fifth
The designation L of the number of loops in the function shown in the figure and the start command COM are set. If COM is started, the DDA operation is continued until L = 0,
In the case of reading / writing, reading from or writing to FM is performed. Here, the condition of FM writing is (the integer part of DY has changed) + (the value of DY has crossed the memory boundary). Further, the fact that the value of DX has crossed the memory boundary means that a carry has occurred in the fourth to fifth bits from the lower 4 bits of DX, and that a unit of 16 pixels is at the time of a frame memory boundary.

The day stay register (DSTR)
The EG) 40 includes n registers 401 to 40n.

In the configuration shown in FIG. 1, the components 32, 3
The reason why 3, 34, 35, 36, 38, 39, and 40 are composed of n planes is that when an image is composed of n bits per pixel, the plane of n bits can be commonly processed in plane units. It is. Thereby, parallel processing is performed. However, as for the multiplier 37, a multiplier is individually provided for each pixel in order to generate a carrier propagation between planes.

The operation of FIG. 1 will be described. The parameters (SX, SY, DX, DY,
I, ΔX, ΔY, ΔSX, ΔI) are set in registers in the DDA circuit 31.

If a raster starting with (SX, SY) exists on the frame memory 4, the selector 54
The X and SY addresses are output via the bus 7-1 as addresses for the frame memory 4, and access the FM4. Read data from within this address from FM4 is sent via bus 7-2, and selector 33 selects and takes in the read data on bus 7-2.

On the other hand, the raster starting with SX and SY is CP
When the data is in the main memory on the U1 side, the read data is sequentially written to the FIFO register 32 via the bus 6, and the selector 33 takes in the data in the register 32 according to the FO method.

The data obtained via the selector 33 is data of 16 pixels. Since each pixel has n bits, 1
The data of six pixels is data of 16 × n bits.

The data selected by the selector 33 is latched in a source register (SOURCE REG) 34 and then sent to a register 35. These registers 34 and 35
And 2 × 16 × n bits of information are latched.

The parallel shifter 36 determines the contents of the register 3 based on the contents of the lower 4 bits (indicating the position in the 16-bit bus width) in the SX register in the DDA.
The data received from 4, 35 is shifted. The result is
The multiplier 37 multiplies each pixel by the stored value I of the brightness information in the DDA. The result of this multiplication is once stored in the write data buffer 38. Data for 16 pixels is stored at one time.

Since FM4 and the like are generally addresses in word units, any one of α bits (0 ≦ α ≦ 15, 1 word 16 bits) can be inserted between the source data and the corresponding destination data. Has occurred. Elements 34, 35, and 36 correspond to this circuit. That is, the shifter 36 shifts an α bit, and the registers 34 and 35 hold two words of source data so that a one-word dart can be generated even if the α shift is performed.

On the other hand, the frame memory address to be written is
Since the address is given by the output 50 of the DDA 31 of DX and DY, the address is output by the selector 54 as the address 7-1 to the FM4 to access the FM4.
The data read by this access is transmitted to the bus 7-
The data is set in the destination register 40 via 2 (for 16 pixels).

The final write data is obtained by calculating the contents of the write data buffer 38 and the destination register 40 simultaneously by the arithmetic unit 39 for 16 pixels. This result is output to F via bus 7-1.
Written to M4.

Regarding the writing of the above operation result to the FM4, the writing pattern of the source data is basically at the bit boundary, whereas the writing of the FM4 is performed in word units. Will break the data. Therefore, the register 40 for reading the original data of the day storage and the data 38 to be written are provided.
It is necessary to perform a process of merging with. An arithmetic unit for this is the arithmetic unit 39.

The processing in the DDA 31 has been described above.
In a mathematical expression, the following operation is performed for each command.

DX ← DX + ΔX DY ← DY + ΔY I ← I + ΔI SY ← SX + ΔSX SY ... Constant value By this, the address of the next pixel to be written, brightness information, and the address of the source pixel to be written can be calculated in pixel units.

According to this embodiment, since multiplication can be performed up to 16 pixels at a time, if the size of the source image and the destination image is unchanged and the brightness information is constant, 16 pixels at a time Calculations can be performed, and further speeding up can be achieved.

Note that 16 pixels is an example, and 8 pixels,
It is also possible to handle 32 pixels and the like.

[0046]

According to the present invention, since image data having shading information can be converted by sequentially calculating brightness information, it is possible to create an image on a display display in which brightness is differently displayed according to illumination. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a graphic conversion process.

FIG. 3 is a configuration diagram of an image processing system according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a graphic conversion process obtained by the image processing device according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a processing example of DDA.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Display control processor, 3 ... DDA circuit diagram, 4 ... Frame memory.

Continued on the front page. (72) Inventor Takeshi Kato 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi, Ltd. Omika Plant

Claims (6)

[Claims] 1. A memory for recording image information to be displayed, and image conversion means for generating a three-dimensional image in which a two-dimensional image is pasted on a surface of a desired three-dimensional figure and storing the generated three-dimensional image in the memory. In the image processing apparatus, the image conversion means generates a three-dimensional image in which the three-dimensional image stored in the memory is pasted on a surface of a desired three-dimensional figure, and stores the three-dimensional image in the memory. Processing equipment. 2. A first memory for storing a two-dimensional image,
A second memory for storing image information to be displayed, and a two-dimensional image stored in the first memory are read out to generate a three-dimensional image in which the two-dimensional image is displayed on a desired three-dimensional figure surface An image processing apparatus comprising: an image conversion unit that stores the three-dimensional image stored in the second memory; the image conversion unit reads the three-dimensional image stored in the second memory; An image processing apparatus for generating a displayed three-dimensional image. 3. A CPU that issues a command to convert a two-dimensional image into a three-dimensional figure and display the three-dimensional figure on the surface of the three-dimensional figure.
A first memory for storing a two-dimensional image, a second memory for storing image information for display, and receiving a command from the CPU, reading the two-dimensional image stored in the first memory; An image conversion unit that generates a three-dimensional image in which the two-dimensional image is displayed on the surface of a desired three-dimensional figure and stores the three-dimensional image in the second memory; An image to be displayed on the surface of a desired three-dimensional figure is read from the first memory or the second memory based on the command from the third memory, and the read image is displayed on the surface of the desired three-dimensional figure. An image processing apparatus for generating an image and storing the generated image in the second memory. 4. A display device, a memory for recording image information to be displayed on the display device, and a three-dimensional image in which a two-dimensional image is displayed on a surface of a desired three-dimensional figure, and stored in the memory. An image processing system comprising: an image conversion unit configured to generate a three-dimensional image in which the three-dimensional image stored in the memory is displayed on a surface of a desired three-dimensional figure and store the generated three-dimensional image in the memory An image processing system, characterized in that: 5. A display device and a first device for storing a two-dimensional image.
, A second memory for storing image information to be displayed on the display device, and a two-dimensional image stored in the first memory, and reading the two-dimensional image onto a surface of a desired three-dimensional figure. An image processing system comprising: a three-dimensional image displayed on the second memory; and an image conversion unit configured to store the three-dimensional image in the second memory. The image conversion unit reads the three-dimensional image stored in the second memory, An image processing system for generating a three-dimensional image displayed on a surface of a desired three-dimensional figure. 6. A CPU for issuing a command for converting a two-dimensional image into a three-dimensional figure and displaying the three-dimensional figure on the surface of the three-dimensional figure,
A display device, a first memory for storing a two-dimensional image, a second memory for storing image information to be displayed on the display device, and a command received from the CPU for storage in the first memory Read out the obtained two-dimensional image, generate a three-dimensional image that displays the two-dimensional image on the surface of the desired three-dimensional figure, and image conversion means for storing the two-dimensional image in the second memory, The image conversion means reads an image to be displayed on the surface of a desired three-dimensional figure from one of the first memory and the second memory based on a command from the CPU, and reads the read image as a desired image. An image processing system, which generates a three-dimensional image displayed on the surface of the three-dimensional figure and stores the generated three-dimensional image in the second memory.