JPH1069515A - Translinear multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a perfect four-quadrant multiplier to be linearly operated corresponding to two input voltages by providing a multiplier core circuit which is composed of a nonuple tail cell with the output of a linear gain cell group as an input and outputs the multiplied value of two signals. SOLUTION: Concerning the respective differential outputs of two voltage/ current converting circuits 101 and 102 to which a 1st input signal voltage Vx and a 2nd input signal voltage Vy are respectively inputted, two stages of diodes 104 and 105 and diodes 106 and 107 are defined as loads, and differential voltages 2ΔVx and 2ΔVy are respectively outputted between the terminals of these diodes. These differential voltages 2 Vx and 2 Vy are passed through differential amplifiers 108 and 109 of a gain '1', and the desired sum voltage or difference voltage of differential voltages 2ΔVx and 2ΔVy is outputted by plural linear gain cell groups 103 defined as differential inputs, and supplied as the respective base voltages of nine transistors at the bipolar nonuple tail cells consisting of the multiplier core circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying two analog signals, and more particularly to a linearized four-quadrant multiplier suitable for being constructed on a bipolar semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a prior art of a multiplier, for example, reference (1) "B. Gilbert," A Precise Four-Quadr "
ant Analog Multiplier with Subnanosecond resp
onse ”, IEEE J. Solid-State Circuits, vol.SC-
3, no. 4, pp. 353-365, Dec. 1968. "

At present, a complete bipolar multiplier performing this type of linear operation has not yet been realized. A somewhat linearized bipolar multiplier of this kind was introduced in 1968, and Gilbert multiplier (Gilbert multiplier)
well known as r). However, voltage-current (V
-I) It is well known that if the conversion circuit operates completely linearly, a complete 4-quadrant multiplier that operates linearly can be obtained even with a Gilbert multiplier using a cross-coupled bipolar differential pair.

The relationship between the collector current I _{ci of the} transistor and the base-emitter voltage V _BEi is represented by the following equation (1), _assuming that it follows an exponential law.

[0005]

(Equation 1)

[0006] Here, I _s is the saturation current, V _T is the thermal voltage, denoted as V _T = kT / q. Here, q is a unit electron charge, k is a Boltzmann constant, and T is an absolute temperature.

The above equation (1) represents the base-emitter voltage V
_When a transistor having a _{BEi of} about 600 mV normally operates, the exponent exp (V _BEi / V _T ) becomes a value of about 10 power,
-1 can be ignored. Therefore, the following equation (2) holds.

[0008]

(Equation 2)

First, the operation of the inverse hyperbolic tangent-hyperbolic tangent conversion circuit shown in FIG. 9 will be described. Referring to FIG. 9, voltage-current (VI) conversion circuits 61 and 62 that receive first and second input voltages V _x and V _y and output currents, and a VI-VI conversion circuit 62 A first differential pair transistor Q1 and Q2 having an emitter commonly connected to one current output terminal and a second differential pair transistor Q3 having an emitter commonly connected to a second current output terminal of the VI conversion circuit 62. , Q4, and the first and second current output terminals of the VI conversion circuit 61, the emitters of which are connected to each other.
Q6, the collectors of transistors Q1 and Q3,
The collectors of the transistors Q2 and Q4 are cross-connected to each other, and the emitter outputs of the transistors Q5 and Q6 are first,
A differential input is applied to the base of the second differential pair transistor, and a differential current is extracted from the collectors of the transistors Q1 and Q4. Voltage-current (VI) conversion circuit 6 that operates linearly
1 and 62 are called “linear gain cells”.

[0010] Linear differential output current of the gain cell 61 I _x ^+, I _x ^- diode connected to the transistors Q5,
When Q6 is driven, the following equations (3) and (4) hold. However, V _BE5 and V _BE6 are the bases of the transistors Q5 and Q6.
Emitter voltage, the G _x is 1/2 of the conductance of a linear gain cells ^{_{(ΔI = I x + -I x}} - = 2G x V x).

[0011] ^{_{I x + = I Ox + G}} x V x = I s exp (V BE5 / V T) ... (3) I x - = I Ox -G x V x = I s exp (V BE6 / V T) …(Four)

Therefore, the output voltage ΔV _x of the diode-connected transistors Q5 and Q6 is given by the following equation (5).

[0013]

(Equation 3)

The differential output current of the bipolar transistor differential pair becomes a hyperbolic tangent function, and the differential output current ΔI of the cross-coupled bipolar differential pair Q1, Q2 and Q3, Q4 is derived by the following equation (6). I will

[0015]

(Equation 4)

However,

[0017]

(Equation 5)

## EQU1 ##

Therefore, if the output current of the VI conversion circuit 61 operating linearly is converted into a voltage by using a pn junction, an inverse hyperbolic tangent circuit is formed, and the cross-connected bipolar differential pair Q1, Q2, which is a hyperbolic tangent circuit, is formed. , And Q3 and Q4, a linear operation can be realized also with respect to the input signal voltage of the cross-connecting bipolar differential pair.

Similarly, a cross-connected bipolar differential pair Q
1, Q2, and the differential output current (I
_0y ± G _y V _y) inverse hyperbolic tangent also - can be linear operation by converting hyperbolic tangent.

[0021]

(Equation 6)

However,

[0023]

(Equation 7)

## EQU1 ##

Therefore, the following equation (12) is obtained, and a complete four-quadrant multiplier that operates linearly is obtained.

[0026]

(Equation 8)

[0027]

In analog signal processing, a multiplier is an indispensable function block. In particular, there is a growing need for a complete four quadrant multiplier that operates linearly with two input voltages.

The conventional Gilbert multiplier cannot realize a complete inverse hyperbolic tangent-hyperbolic tangent conversion because the voltage-current (VI) conversion circuit does not operate completely linearly.
For this reason, the conventional Gilbert multiplier has not been a complete four-quadrant multiplier that operates linearly with respect to two input voltages.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a complete multiplier that operates linearly with respect to two input voltages as a multiplier particularly important in analog signal processing. It is to provide a four quadrant multiplier.

[0030]

In order to achieve the above object, a translinear multiplier according to the present invention has a first and a second input signals which output a differential current corresponding to respective voltages. , A second voltage-current conversion circuit, a pn junction element for converting the differential output current of each of the first and second voltage-current conversion circuits into a voltage, and the first and second voltage-current conversion circuits.
A voltage between the pn junction elements connected to the voltage-current conversion circuit is set as a differential input voltage, and a linear gain cell group that outputs a sum or a difference voltage thereof, and a differential output pair whose outputs are commonly connected to each other. Including two pairs of transistors that make up
The emitters are connected in common and driven by a common current,
A multiplier core circuit comprising a non-pull tail cell to which the output of the linear gain cell group is input, and which outputs a multiplication value of two signals.

In the present invention, the differential input voltage can be logarithmically compressed by using a linear gain cell as a voltage-current (VI) conversion circuit that operates linearly. The desired sum or difference voltage is obtained, and nine transistors are provided as the base voltage of a non-pull tail cell driven by a common tail current. And the non-pull tail cell can be operated as a multiplier core circuit, thus
It is possible to realize a complete four-quadrant multiplier that is equivalently exponentially converted and operates linearly.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

A circuit in which three or more transistors are driven by one common tail current is called a "multi-tail cell". For example, in the case of nine transistors, a "non-pull tail cell" is used. In this case, it will be referred to as a "quadridecimal tail cell".

FIG. 1 is a block diagram showing a configuration of a bipolar multiplier according to an embodiment of the present invention. For the convenience of drawing, the multiplier core circuit is
This is shown in FIG. 1 (B) and FIG.

Referring to FIG. 1, a first input signal voltage (V
_x ) and the second input signal voltage (V _y ) are respectively input to two voltage-current (VI) conversion circuits 101 and 102.
Of the two-stage diode 104, 1
05, and 106 and 107 as a load, respectively difference between the terminals of these diodes voltage 2.DELTA.V _x, outputs the 2.DELTA.V _y.

A plurality of linear gain cell groups 103 having the differential voltages 2ΔV _x and 2ΔV _y as differential inputs via differential amplifiers 108 and 109 having a gain of 1 provide a differential voltage 2ΔV _x , 2ΔV _x ,
Outputs a desired sum voltage or difference voltage of 2ΔV _y , and outputs the base voltage of each of the nine transistors of the bipolar non-pull tail cell constituting the multiplier core circuit, or the fourteen bipolar quadridecimal tail cells. Are supplied as base voltages of respective transistors (see FIG. 2).

FIG. 10 shows the overall circuit configuration of the translinear multiplier according to the embodiment of the present invention.
Note that, with reference to FIG. 10, the first input signal voltage (V _x )
In FIG. 10, the differential outputs of the two voltage-current (VI) conversion circuits 101 and 102 to which the second input signal voltage (V _y ) and the second input signal voltage (V _y ) are input, respectively,
04, 105, and 106 and 107 are loads, and the respective differential voltages between the terminals of these diodes are input to two voltage-current (VI) conversion circuits 110 and 111,
The differential current outputs of the voltage-current (VI) conversion circuits 110 and 111 are input to a current adder (current adder) 120, added and subtracted by the current, and output as a voltage from the connection point of the load resistance group 122, which will be described later. The emitters are connected in common to the multi-tail cell 130 connected to the constant current source, and the multiplied value of the two signals is extracted. Note that the buffer amplifiers 108, 10 in FIG.
9 and the linear gain cell group are the voltage-current (VI) conversion circuits 110 and 11 in the circuit configuration of FIG.
1, the current adder 120, and the load resistance group 122. The terminal voltage of the load resistor group 122 may be the base voltage of each of the nine transistors of the bipolar non-pull tail cell constituting the multi-tail cell 130, or the fourteen transistors of the bipolar quadri-decimal tail cell (FIG. 2). (See Reference). FIG. 10 shows a configuration in which the diodes 104 and 105 and 106 and 107 are vertically stacked in two stages. The mirror ratio of the current mirror circuit that sums the currents in the current adder 120 and the load resistance group 122 are shown. By appropriately setting the resistance value, the diode may be provided in one stage.

Next, an example of the configuration of the voltage-current (VI) conversion circuits 101 and 102 using diodes as loads is shown in FIG.
Shown in

Referring to FIG. 3, the base-emitter voltages of two transistors Q1 and Q2 driven by a constant current are as follows.
When the drive currents are equal, the same is obtained, and the differential input voltage V _x
Is directly applied to the emitter-to-emitter resistance _Rx . Therefore, since the resistance R _x is a linear element, the resistance R _x
Current flowing through is proportional to the differential input voltage V _x, and inversely proportional to the resistance value. However, since the two transistors Q1 and Q2 forming the differential pair are driven at a constant current, the transistors Q3 and Q4 connected to the emitters of the respective transistors Q1 and Q2 have the emitter-to-emitter resistance R
_The current added or subtracted by the current flowing in _x flows. Therefore, the voltage-current (VI) conversion circuit shown in FIG. 3 operates linearly and acts as a linear gain cell. It should be noted that the diode-loaded VI conversion circuit shown in FIG. 3 extracts the voltage (2ΔV _x ) between the base terminals of the transistors Q3 and Q4, and is supplied to the differential amplifier 108 shown in FIG. 1 as 2ΔV _x ^+. (The same applies to the VI conversion circuit 102).

Therefore, in the circuit shown in FIG. 3, if a current mirror circuit with an emitter follower is added to the emitters of the transistors Q1 and Q2 in order to extract a current output, the current gain becomes a linear gain cell having a current output, and a differential output is obtained. If the current outputs of a plurality of linear gain cells are added to the current by wire, and a resistance load is applied, equivalently, the input voltage ΔV _x to each linear gain cell,
The sum voltage of ΔV _y aΔV _x + bΔV _y, or differential voltage a '
ΔV _x −b′ΔV _y is obtained differentially.

Since the multiplier core circuit in the block diagram shown in FIG. 1B is a bipolar non-pull tail cell, it is driven by a tail current _IEE , assuming good matching between elements. The collector current of each bipolar non-pulple tail cell is expressed by the following equation (13).
Given by (21).

[0042]

(Equation 9)

Where V _R is the DC voltage of the input signal, V _E
Is the common emitter voltage.

From the condition of the tail current, the following equation (2)
2) holds.

[0045]

(Equation 10)

Where α _F is the DC current gain of the transistor. By solving the above equation (22) from the above equation (13),
The following equation (23) is obtained.

[0047]

[Equation 11]

Referring to FIG. 1B, the differential output current ΔI of the bipolar non-pull tail cell is determined by the sum of the collector currents of transistors Q1 and Q2 and transistors Q3 and Q
4 is given by the difference of the sum of the collector currents,
It is represented by

[0049]

(Equation 12)

Here, as shown in FIG. 4, the voltage applied to each base of the nine transistors Q1 to Q9 of the bipolar non-pull tail cell forming the multiplier core circuit is V ₁ = a (2ΔV _x ) + b (2ΔV _y ), V ₂ = (a-1) (2ΔV _x ) + (b-1) (2ΔV _y ), V ₃ = (a-1) (2ΔV _x ) + b (2ΔV _y ), V ₄ = a (2ΔV _x ) + (b-1) (2ΔV _y ), V ₅ = (a-1 / 2) (2ΔV _x ) + (b-1 / 2) (2ΔV _y ) + V _T ln2, V ₆ = a (2ΔV _x ) + (b-1 / 2) (2ΔV _y ), V ₇ = (a-1) (2ΔV _x ) + (b-1 / 2) (2ΔV _y ), V ₈ = (a-1 / 2) (2ΔV _x ) + b (2ΔV _y ), V ₉ = (a-1 / 2) (2ΔV _x ) + (b-1) (2ΔV _y ) Substituting into (24) gives bipolar
The differential output current ΔI of the multiplier is obtained by the following equation (25).

[0051]

(Equation 13)

In a general bipolar process, α
_F is between 0.98 and 0.99, which is close to unity. The above equation (25) is given by sinhz / (coshz + 1)
Of the function of sinhz / (cosh
z + 1) is matched to the transfer characteristics of the triple tail cell.

Here, the difference voltages ΔV _x and ΔV _y are obtained as follows.

[0054] shown in FIG. 3, inputs the differential input voltage V _x, the voltage to the diode load - current (V-I) differential output current of the converter circuit, respectively obtained as follows. Here, V _BE5 and V _BE6 are base-emitter voltages of the transistors Q5 and Q6 (corresponding to the diodes 104 and 105).

[0055] ^{_{I x + = I Ox + V}} x / R x = I s exp (V BE5 / V T) ... (26) I x - = I Ox -V x / R x = I s exp (V BE6 / V _T )… (27)

Therefore, the differential output voltage ΔV _x is obtained by the following equation (28).

[0057]

[Equation 14]

Similarly, the differential output current of the voltage-current (VI) conversion circuit which receives the differential input voltage _Vy as an input and which is a diode load is obtained as follows. Where V
_BE7 and V _BE8 are base-emitter voltages of transistors corresponding to the diodes 106 and 107 in FIG. 1 (corresponding to the transistors Q5 and Q6 in FIG. 3).

[0059] ^{_{I y + = I Oy + V}} y / R y = I s exp (V BE7 / V T) ... (29) I y - = I Oy -V y / R y = I s exp (V BE8 / V _T )… (30)

Therefore, the differential output voltage ΔV _y is obtained by the following equation (31).

[0061]

(Equation 15)

By substituting the above equations (28) and (31) into the above equation (25), the following is obtained.

[0063]

(Equation 16)

However,

[0065]

[Equation 17]

Is as follows.

Thus, a complete four-quadrant analog multiplier operating linearly is obtained.

As described above, the voltage applied to the base of each of the four transistors of the bipolar non-pull tail cell constituting the multiplier core circuit, V ₁ = a (2ΔV _x ) + b (2ΔV _y ), V ₂ = (a-1) (2ΔV _x ) + (b-1) (2ΔV _y ), V ₃ = (a-1) (2ΔV _x ) + b (2ΔV _y ), V ₄ = a (2ΔV _x ) + (b-1) (2ΔV _y ), V ₅ = (a-1 / 2) (2ΔV _x ) + (b-1 / 2) (2ΔV _y ) + V _T ln2, V ₆ = a (2ΔV _x ) + (b-1 / 2) (2ΔV _y ), V ₇ = (a-1) (2ΔV _x ) + (b-1 / 2) (2ΔV _y ), V ₈ = (a-1 / 2) (2ΔV _x ) + b (2ΔV _y ), V ₉ = (a−1 / 2) (2ΔV _x ) + (b−1) (2ΔV _y ) Was.

[0069] It should be noted that, in the above-mentioned V _5, transistor Q
By doubling the emitter area of 5 (see FIG. 4), a constant term + V _T ln2 can be realized.

Further, as shown in FIG. 2, when transistors Q10 to Q14 are added to form a bipolar quadruple-decimal tail cell, transistors Q1, Q2, Q
5, Q6, Q7, Q8, Q9 and transistors Q3, Q4, Q10, Q11, Q12, Q13, Q14
Are obtained by shunting the tail current: I ₀ , respectively, so that when no signal is input, I _0/2 is set as the DC operating point. Therefore, at the time of signal input, the current changes around this DC operating point (I _0/2 ). In this case, it is understood that the respective output currents become linear without taking the difference current. .

Similarly, transistors Q1, Q2, Q3,
If the emitter area of Q4, Q5, and Q10 (see FIG. 5) is doubled, a constant term + V _T ln2 can be realized.

That is, FIG. 5 corresponds to the case where the bypass current I bypass shown in FIG. 4 is divided into two and added to the output current.

Accordingly, a complete four-quadrant analog multiplier operating linearly can be obtained by using the bipolar quadri-decimal tail cell.

In the above-described linear gain cell, by setting the resistance between the emitters and the like, this arbitrary constant a,
b cannot be realized. That is, by setting the constants a and b to specific values, a complete 4
A quadrant analog multiplier is obtained.

For example, if a = 1/2 and b = 1/2, this can be easily realized by increasing the number of outputs of the current mirror circuit of the two linear gain cells. FIG. 6 shows a connection circuit diagram of two linear gain cells in this case. However, in FIG. 6, V ₅ (not shown) is the DC voltage V _T ln2
However, it can be easily realized by doubling the emitter area of the transistor Q5 in FIG.

In the case of quadri-decimal tail cells, similarly, in FIG. 6, V ₁ , V ₂ , V ₃ , V ₄ , V ₅ ,
Although the V ₁₀ DC voltage V _T ln2 is superimposed, it is easy realized by doubling the emitter area of the transistors Q1, Q2, Q3, Q4, Q5, Q10 of FIG.

Referring to FIG. 6, difference voltages (ΔV _x , ΔV _y )
Are connected to each other, and the outputs of the current mirror circuits are connected to each other, and the sum or difference current of each is obtained. from the resulting terminal voltage of the load resistor R by the current in which they were taken out of the voltage V ₁ ~V ₉ (however, in the case of a = b = 1/2 is
As described above, the base voltage V of the transistor Q5 in FIG.
_5, also the base voltage V _5, V ₁₀ of the transistor Q5 and Q10 in FIG. 5, it is not necessary to take out from the linear gain cell). First linear gain cell has an emitter connected by a resistor R, the differential input voltage [Delta] V _x based input consists differential pair transistors Q1, Q2 respectively to the collector constant current source I ₀ is connected, the emitter current I ₀ ± G _x ΔV _x is first output from, are input to the input terminal of the second current mirror circuit (including an emitter follower circuit), the output terminals of these current mirror circuits (each of the three output Is connected to the power supply VCC via the resistor R alone (for example, the nodes V ₆ , V ₇
See), third second linear gain cells to enter the differential input voltage [Delta] V _y, is connected to the power supply VCC through the output end and are commonly connected to the resistance R of the fourth current mirror circuit. The same applies to the second linear gain cell. Note that when the linear gain cell shown in FIG. 6 is applied to the linear gain cell group 103 shown in FIG. 1, the differential input voltages ΔV _x and ΔV _y of the linear gain cell
08,109, which is the output of Δ2V _x, are Δ2V _y.

If a = 1 and b = 1, it can be easily realized by increasing the number of outputs of the current mirror circuit of the two linear gain cells and changing the mirror ratio. FIG. 7 shows a connection circuit diagram of two linear gain cells in this case. However, the emitter area of the transistor Q5 in FIG. 4 is doubled. In FIG. 7, V10 to V14 indicate base voltages of the quadri-decimal tail cells.

Similarly, a = 1/2, b = 1 or b = 0
Then, it can be easily realized by increasing the number of outputs of the current mirror circuit of the two linear gain cells and changing the mirror ratio. FIG. 8 shows a connection circuit diagram of two linear gain cells in this case. However, also in this case, the emitter area of the transistor Q5 of FIG. 4 is doubled, and the emitter areas of the transistors Q1, Q2, Q3, Q4, Q5, and Q14 of FIG. 5 are doubled.

According to the above-described embodiment, a complete four-quadrant multiplier that operates linearly can be realized and a constant voltage operation can be performed. For example, at a low voltage of about 1.9 V, a completely linear input voltage close to 1 V _PP is obtained. A multiplier with a range is realized.

[0081]

As described above, according to the present invention, a complete linear circuit and a complete inverse hyperbolic tangent circuit can be realized, so that a complete four-quadrant multiplier that operates linearly is realized. It has the effect of being able to.

Further, according to the present invention, since a low-voltage operation is enabled by using a linear gain cell that operates linearly as a current mirror circuit output, for example, at a low voltage of about 1.9 V, a complete voltage of about 1 V _PP is obtained. This has the advantage that an ideal multiplier having a wide linear input voltage range is realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a bipolar multiplier according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a bipolar multiplier according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of the present invention, in which a voltage-current (V) with a diode as a load according to the embodiment of the present invention;
FIG. 3I is a diagram illustrating a configuration example of a conversion circuit.

FIG. 4 is a diagram showing an example of the present invention, and is a diagram showing a bipolar multiplier core circuit in the embodiment of the present invention.

FIG. 5 is a diagram showing an example of the present invention, and is a diagram showing a bipolar multiplier core circuit in the embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of the present invention, and is a diagram illustrating an example of a linear gain cell according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of the present invention, and is a diagram illustrating a configuration example of another circuit of the linear gain cell according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of the present invention, and is a diagram illustrating a configuration example of still another circuit of the linear gain cell according to the embodiment of the present invention.

FIG. 9 is a diagram showing a conventional inverse hyperbolic tangent-hyperbolic tangent conversion circuit for realizing a complete four-quadrant multiplier.

FIG. 10 is a diagram showing a configuration of a bipolar multiplier according to an embodiment of the present invention.

[Explanation of symbols]

 I0 Current source 101 VI conversion circuit 104, 105, 106, 107 Diode 109 Linear gain cell 110 Multiplier core circuit Q1-Q9 Transistor R Resistance VCC Power supply

Claims (9)

[Claims] A first and second voltage-current conversion circuit for receiving a first and a second input signal and outputting a differential current corresponding to each voltage; and the first and second voltage-current circuits. A pn junction element for converting the respective differential output currents of the conversion circuit into a voltage, and a voltage between the pn junction elements connected to the first and second voltage-current conversion circuits as a differential input voltage. A linear gain cell that outputs a sum or difference voltage; and a pair of transistors whose outputs are commonly connected to each other to form a differential output pair. The emitters are commonly connected and driven by a common current. A translinear multiplier comprising a non-pull tail cell having an output of a group as an input, and a multiplier core circuit for outputting a multiplied value of two signals. 2. The translinear multiplier according to claim 1, wherein said pn junction elements are vertically stacked in one or two stages. 3. The multiplier core circuit according to claim 2, wherein the outputs are commonly connected to each other to form a differential current output pair.
A first transistor, a second transistor, and a fifth transistor to a ninth transistor, the first transistor including a third transistor and the fourth transistor, the fifth transistor including a collector connected in common, and the fifth transistor being connected to a power supply; 9. A non-pull tail cell, wherein the emitters of the first to ninth transistors are connected in common and driven by one constant current source.
The described translinear multiplier. 4. The first and second transistors, wherein the multiplier core circuit is a pair of transistors whose outputs are commonly connected to each other and connected to a differential current output pair. 5th to 1st transistors each including a transistor and having a collector connected in common and each connected to an output pair.
4. A quadri-decimal tail cell comprising: a first transistor to a fourth transistor; and an emitter of the first to fourteenth transistors connected in common and driven by one constant current source. Translinear multiplier. 5. The method according to claim 4, wherein the voltage between the two-stage pn junction elements of each voltage-current conversion circuit is 2Δ
V _x, upon the 2.DELTA.V _y, Roh first to the base voltage of the ninth transistor constituting the news pull tail cells (V _1,
V ₂ , V ₃ , V ₄ , V ₅ , V ₆ , V ₇ , V ₈ , V ₉ ) are respectively expressed as V ₁ = a (2ΔV _x ) + b (2ΔV _y ), V ₂ = (a−1) (2ΔV _x ) + (b−1) (2Δ
V _y ), V ₃ = (a−1) (2ΔV _x ) + b (2ΔV _y ), V ₄ = a (2ΔV _x ) + (b−1) (2ΔV _y ), V ₅ = (a−1 / 2) ) (2ΔV _x ) + (b − ／) (2
ΔV _y ) + V _T ln2, V ₆ = a (2ΔV _x ) + (b − ／) (2ΔV _y ), V ₇ = (a−1) (2ΔV _x ) + (b−1 / 2) (2ΔV
_{y), V 8 = (a} -1/2) (2ΔV x) + b (2ΔV y), V 9 = (a-1/2) (2ΔV x) + (b-1) (2ΔV
_y ) (where a and b are arbitrary constants). 6. The method according to claim 4, wherein the voltage between the pn junction elements of the two-stage configuration of each voltage-current conversion circuit is 2Δ
V _x, upon the 2.DELTA.V _y, first to the base voltage of the fourteenth transistor constituting the quaterphenyl drill decimal tail cells _{(V 1, V 2, V} 3, V 4, V 5, V 6, V 7, V _8, V _9, V
₁₀ , V ₁₁ , V ₁₂ , V ₁₃ , V ₁₄ ) are calculated as follows: V ₁ = a (2ΔV _x ) + b (2ΔV _y ) + V _T ln2, V ₂ = (a−1) (2ΔV _x ) + (b) -1) (2ΔV _y )
+ V _T ln2, V ₃ = (a-1) (2ΔV _x ) + b (2ΔV _y ) + V _T ln
2. V ₄ = a (2ΔV _x ) + (b−1) (2ΔV _y ) + V _T ln
2. V ₅ = (a − ／) (2ΔV _x ) + (b − ／) (2
ΔV _y ) + V _T ln2, V ₆ = a (2ΔV _x ) + (b − ／) (2ΔV _y ), V ₇ = (a−1) (2ΔV _x ) + (b−1 / 2) (2ΔV
_{y), V 8 = (a} -1/2) (2ΔV x) + b (2ΔV y), V 9 = (a-1/2) (2ΔV x) + (b-1) (2ΔV
_{y), V 10 = (a} -1/2) (2ΔV x) + (b-1/2)
(2ΔV _y ) + V _T ln2, V ₁₁ = a (2ΔV _x ) + (b − ／) (2ΔV _y ), V ₁₂ = (a−1) (2ΔV _x ) + (b−1 / 2) ( 2Δ
V _y ), V ₁₃ = (a − ／) (2ΔV _x ) + b (2ΔV _y ), V ₁₄ = (a − ／) (2ΔV _x ) + (b−1) (2Δ
V _y ) (where a and b are arbitrary constants). 7. The method according to claim 5, wherein a = 1/2, b
= 1/2. A translinear multiplier characterized in that: = 1/2. 8. The method according to claim 5, wherein a = 1 and b = 1
Translinear multiplier characterized by the following. 9. The method according to claim 5, wherein a = 1/2, b
= 1 or b = 0. A translinear multiplier.