JP2888212B2 - Bipolar multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying two input signals, and more particularly to a bipolar multiplier which is preferably formed on a semiconductor integrated circuit, operates at a low voltage, and has excellent linearity. About.

[0002]

2. Description of the Related Art For example, the following publications and documents are referred to as prior art of this kind of bipolar multiplier.

(1) Japanese Patent Publication No. 55-19444 (FIG. 2) (2) K. Kimura, "A Bipolar Very Low-Voltage Multip
lier Core Using a Quadritail Cell ”, IEICE Trans. F
undamentals., vol.E78-A, no.5, pp.560-565, May 1995.

[0004] As a prior art of the bipolar multiplier, for example, Japanese Patent Publication No. 55-19444 discloses FIG.
A bipolar multiplier as shown in FIG. According to the publication, the output current of the differential amplifier composed of the transistors Q11 and Q12 is not directly related to the input current but is related only to the ratio x, and therefore the output current has a linear characteristic. In addition, the document describes that the differential amplifier having no temperature characteristic and having the same structure as the differential amplifier including the transistors Q13 and Q14 can obtain an output signal obtained by linearly multiplying the input signal.

However, in the circuit shown in FIG. 10, only the current distribution in the circuit is shown as a circuit analysis, and it is extremely difficult to understand the operation of the circuit. This is because, in a differential pair, how the current is distributed to the differential input voltage is completely unknown, and nothing is based on the physical operating principle of the transistor. .

Further, in a quadritail cell (multiplier core circuit) in which four transistors are driven by one common constant current source, ordinary circuit analysis is difficult because an emitter resistor is inserted. Master. However, by analogy with the above-mentioned document by the inventor, it can be clearly confirmed that a multiplication characteristic can be obtained.

However, in the circuit shown in FIG. 10, the linearity of the multiplier operation for two input voltages is not ensured.

[0008]

As mentioned above, conventional bipolar multipliers do not achieve sufficient linear operation, but rather sacrifice complete linear operation.

In analog signal processing, a multiplier is regarded as an indispensable basic function block, and as the process becomes finer (finer), the power supply voltage of the LSI is reduced from 5V to 3V or lower. As the voltage has been reduced, the need for low-voltage circuit technology has further increased.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a bipolar multiplier which ensures a predetermined linear input voltage range even during low-voltage operation. I do.

[0011]

In order to achieve the above object, the present invention provides a first differential input signal having a first differential input signal and two output pairs each of which outputs a current having the same value. (Hereinafter referred to as “first VI conversion circuit”), and two pairs of transistors each driven by two pairs of output currents of the first VI conversion circuit,
A second differential input signal is input to each transistor pair of the two pairs of transistors, and output voltages from respective emitters of the two pairs of transistors are used as respective input voltages, and are driven by one common constant current source. A bipolar multiplier comprising four transistors is provided.

In the present invention, preferably, the first
Is characterized by including a differential pair into which an emitter resistor is inserted.

[0013]

According to the present invention, the base of the four transistors first input voltage (V _x) are driven respectively by the two pairs of the output current of the V-I conversion circuit to be applied, a second input voltage By applying (V _y ), an ideal inverse hyperbolic tangent function (tanh ⁻¹ ) circuit can be realized. For the first input voltage (V _x ), a completely linear bipolar multiplier is used. realizable. Further, the emitter output voltages of the two transistors each driven by the output current of the second VI conversion circuit to which the second input voltage (V _y ) is applied are converted to the first VI conversion voltage. An ideal inverse hyperbolic tangent function (tanh ^-1 ) circuit for the second input voltage (V _y ) by applying to the bases of four transistors each driven by two pairs of output currents of the circuit Can be realized, and a completely linear bipolar multiplier can be realized with respect to the first input voltage and the second input voltage.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a bipolar multiplier according to an embodiment of the present invention.

Referring to FIG. 1, as a preferred embodiment, a bipolar multiplier according to the present invention receives a first differential input signal (V _x ) and receives currents (I _x ⁺ ) having the same value as each other. The first current output terminal pair (+, +) for supplying
And a second current-output terminal pair (−, ⁻ ) for supplying currents (I _x ⁻ ) having the same value to each other, and a first voltage-current conversion circuit (hereinafter referred to as “VI conversion circuit”). 11 and VI
The first current output terminal pair (+, +) of the conversion circuit 11 and the second
The first transistor pair (Q5, Q5 ') and the second transistor pair (Q6, Q6') whose emitters are respectively connected to the current output terminal pair (-,-) and whose collectors are both connected to the power supply VCC. And a second differential input signal (V _y ) both between the base terminals of the first transistor pair (Q5, Q5 ′) and between the base terminals of the second transistor pair (Q6, Q6 ′). ) Is applied. Further, these transistors (Q5, Q5 ', Q6, Q6') bias voltage V _R is superimposed on the applied voltage to be input to the bases of.

Further, a third transistor pair (Q1, Q4) and a fourth transistor pair (Q2, Q3) whose emitters are connected in common and connected to a constant current source (I ₀ ) and whose collectors are cross-connected to each other. ), And each base of the third transistor pair (Q1, Q4) includes a first transistor pair (Q5, Q5 ') and a second transistor pair (Q6, Q6,
Q6 '), one of the transistors (Q
5, Q6), respectively, and the commonly connected collector is connected to a power supply VCC via a resistor _RL , while each base of the fourth transistor pair (Q2, Q3) is connected to the first The other pair of transistors (Q5 ', Q6') constituting the transistor pair (Q5, Q5 ') and the second transistor pair (Q6, Q6') are connected to the emitter outputs, respectively. It is connected to the power supply VCC via R _L.

The third transistor pair (Q1, Q2)
4) of the output current (sum I _C1 + I _C4 of the collector current) and the fourth transistor pair (Q2, Q3 sum I _C2 + I _C3 of the output current (collector current of)) is, or the third transistor pair ( Q1, Q4) (collector current sum I)
_C1 + and I _C4), a fourth transistor pair (Q2, Q3) between the output current (the sum of the collector current I _C2 + I _C3), the differential current _{(ΔI = I C1 + I C4} - (I C2 + I C3)) is From these currents, the first differential input voltage (V _x ) and the second
Is obtained by so as to obtain a differential input voltage (V _y) and multiplied by the value (product), in these currents, linearity is compensated for the first differential input voltage (V _x) You.

The embodiment of the bipolar multiplier according to the present invention shown in FIG. 1 will be described in detail below based on circuit analysis.

If the base width modulation is neglected, the relationship between the collector current I _{C of the} transistor and the base-emitter voltage V _BE is expressed by the following equation (1).

[0020]

(Equation 1)

[0021] Here, I _S is the saturation current, V _T is the thermal voltage of the unit transistor, expressed as V _T = kT / q. Here, q is a unit electron charge, k is a Boltzmann constant, and T is an absolute temperature.

First, the inverse hyperbolic tangent (tanh ^-1 ) -hyperbolic tangent (tanh) conversion operation will be described.

VI conversion circuit (voltage-current conversion circuit) 1
When the transistors (Q5, Q6) are driven by the differential output current of 1, the following expressions (2) and (3) are established.

[0024] ^{_{I x + = I 0x + G}} x V x = I S exp (V BE5 / V T) ... (2) I x - = I 0x -G x V x = I S exp (V BE6 / V T) … (3)

[0025] Here, 2G _x is the conductance of the V-I conversion circuit ^{_{11 (ΔI = I x + -I}} x - = 2G x V x).
From the above equations (2) and (3), the differential output current (ΔI) is ΔI
= I _x ⁺ -I _x ^- = expressed as 2G _x.

Therefore, the base-emitter voltages V _{BE1 to} V _BE4 of the four transistors Q1, Q2, Q3, Q4 of the quadritail cell whose emitters are commonly connected, which constitute the multiplier core circuit, have the common emitter Assuming that the voltage is V _E , the following equations (4), (5), (6), and (7)
It is represented by

[0027]

(Equation 2)

By substituting the above equations (4) to (7) into the above equation (1), the collector currents of the transistors Q1, Q2, Q3, and Q4 are given by the following equations (8), (9), (9) 10), (1)
1).

[0029]

(Equation 3)

[0030] Since the transistors Q1 Q4 are driven by a common constant current source I ₀ following equation (12) holds (where, alpha _F DC current amplification factor).

I _C1 + I _C2 + I _C3 + I _C4 = α _F I ₀ (12)

Therefore, from the above equations (8) to (11)
Into the above equation (12), the differential output current ΔI = I _C1 + I _C4 − (I _C2 + I _C3 ) of the quadritail cell is expressed by the following equation (13).

[0033]

(Equation 4)

[0034] Therefore, completely the linear operation for the first input voltage V _x. For example, in a frequency mixer,
Since linearity is not required for the local input and linearity is required for the radio frequency input, the first input voltage V _x is used as the radio frequency input, and the second input voltage V _y is used as the local input. Just do it.

Further, as can be seen from the above equation (12),
Conversely hyperbolic tangent for the second input voltage V _y (tan
h ^-1) - if Hodokose the hyperbolic tangent (tanh) conversion, may be a perfectly linear operation with respect to the second input voltage V _y.

FIG. 2 shows a second VI conversion circuit (voltage-voltage
Output current I of the current conversion circuit 12) _y ⁺, I_y ^-At Transi
When the stars Q7 and Q8 are driven, the following equations (14) and (15) are obtained.
Holds.

[0037] ^{_{I y + = I 0y + G}} y V y = I S exp (V BE7 / V T) ... (14) I y - = I 0y -G y V y = I S exp (V BE8 / V T) … (15)

Here, 2G _y is the conductance of the VI conversion circuit 12. Equation (14), from (15), the differential output current ([Delta] I) is ΔI = I _y ⁺ -I _y ^- expressed as = 2G _y.

In this case, the differential output current ΔI = I _C1 + I _C4 − (I _C2 +) of the bipolar multiplier shown in FIG.
I _C3 ) is similarly obtained and is expressed by the following equation (16).

[0040]

(Equation 5)

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically explain the above-described embodiment of the present invention, an embodiment of the present invention will be described below. That is, in the bipolar multiplier shown in FIGS. 1 and 2, for example, the circuit shown in FIG. 3 is used as the VI conversion circuit 11 which actually operates linearly.

Referring to FIG. 3, the operation of the VI conversion circuit which operates linearly will be described.

[0043] Enter the differential input voltage V _x, of the two pairs of output currents I ^+, I ⁺ and ^{I -, I} - ^V-I conversion circuit 11 for outputting a
Are two transistors Q sharing an emitter resistance _Rx.
The constant current source I _0x is connected to the collectors of the first and second transistors Q 1 and Q 2, respectively, and driven by the same current I _0x.
The emitters of transistors Q1 and Q2 are respectively connected to the input terminals (transistors Q3 and Q4) of a current mirror circuit having transistors Q9 and Q10 in an emitter follower configuration.
Each of the two output terminals of the current mirror circuit from (the transistors Q5, Q6, and Q7, Q8), the output current I ^+, I ^+, and ^I -, I ^- is taken out.

In the VI converter of FIG. 3, the base-emitter voltages V _BE of the two transistors Q1 and Q2 are equal to each other, and the differential input voltage V _x is shifted by the base-emitter voltage V _BE. Therefore, since the voltage is directly applied to the emitter resistance _Rx , a floating resistance is equivalently realized.

[0045] Thus, in the linearity of the emitter resistors R _x, linear operation of the V-I converter is dominantly determined, output current, for example, ^{_{I - = I 0x -V x /}} R x, I + = I
Given by _0x + V _x / R _x.

Further, the emitter follower transistor (Q
9, Q10) are provided in the output pair, and a plurality of output currents having the same current value are output by increasing the number of output transistors to Q6 and Q8.

Next, the measured values actually obtained are shown to clarify the effectiveness of the present invention.

FIG. 4 shows a linearly operating VI shown in FIG.
6 shows an actual measurement value of the transfer characteristic of the conversion circuit. In FIG. 3, power supply voltage VCC = 1.9 V, R _x = 10 kΩ, I _0x ≒ 50
μA, and the load resistance inserted between the transistors Q5 and Q7 and the power supply VCC is 18 kΩ. When the value of the input voltage Vx is within the range of 800 mV _PP , the total distortion is 0.1% or less at an input signal frequency of 1 kHz.

Next, FIG. 5 shows the measured values of the transfer characteristics of the bipolar multiplier shown in FIG. 2 using two VI conversion circuits which operate linearly as shown in FIG. In FIG. 2, the power supply voltage VCC is 1.9 V, I ₀ 0100 μA, and the load resistance R _{L is} 8.2 kΩ. Within the input voltage range in which the used VI conversion circuit operates linearly, the transfer characteristic of the bipolar multiplier shown in FIG. 2 also operates linearly, and an ideal multiplication characteristic is obtained.

In the present embodiment, it is capable low voltage operation can be achieved perfectly linear operation for one of the signal input voltage V _x (see equation (12)) with a simple circuit configuration.
As a result, a bipolar multiplier having a completely linear input voltage range close to 1 V _PP at a low voltage of about 1.9 V with respect to one of the signal inputs can be realized.

Next, another embodiment of the present invention will be described with reference to FIG.

As described in the above embodiment, a completely linear operation is desired for the VI conversion circuit in the multiplier. However, in the case where the circuit is greatly simplified, even if the linear operation is somewhat sacrificed, a VI conversion circuit having a non-linear operation with practically no problem is often sufficient.

Therefore, in the present embodiment, as shown in FIG. 6, the first input voltage V _x is input, and the output current I _x ⁺ ,
^{_{I x +, I x -,}} I x - a transistor Q5, Q5 ', Q6,
As a VI conversion circuit supplied to Q6 ', a pair of differential transistors Q7 and Q having an extended linear input voltage range by emitter degeneration through an emitter resistor _Rx.
8, Q9 and Q10 are connected in parallel.
Differential transistor pair Q7, Q8, and Q9, Q10 inputs the first input signal voltage V _x between the base terminal, a common connection point of the emitters of the transistors Q7, Q9, and Q8,
The common connection point of the emitters of Q10 is connected to a constant current source having a current value of 2I _0x .

[0054] In this case, the first input signal V _x, the linearity degree of the Gilbert multiplier using Gilbert gain cell to the pre-distortion circuit.

FIG. 7 shows still another embodiment of the present invention.
Differences between the present embodiment, the embodiment shown in FIG. 6 receives a first input voltage V _x, the output current ^{_{I x +, I x +,}} I x -, I x
^- The transistors Q5, Q5 ', Q6, Q6 ' as V-I conversion circuit supplied to a differential transistor pair Q7 expanded linear input voltage range has an emitter resistor R _x, Q
8, Q9 and Q10, and transistors Q7 and Q
9 and a common connection point of the emitters of the transistors Q8 and Q1.
0 The common connection point of the emitters are connected to each other via two resistors connected in series, the common connection point of two resistors RE _x is connected to a constant current source of a current value 4I _0x.

Next, still another embodiment of the present invention will be described with reference to FIG.

[0057] In this embodiment, as shown in FIG. 8, enter the first input voltage V _x, the output current ^{_{I x +, I x +,}} I x -, I x
^- The transistors Q5, Q5 ', Q6, Q6 ' as V-I conversion circuit supplied to, and emitter-degeneration via an emitter resistor R _x, differential transistor pair Q7 enlarging a linear input voltage range, Q8 and Q9,
Q10 is connected in parallel. Differential transistor pair Q7, Q8, and Q9, Q10 inputs the first input voltage V _x between the base terminal, a common connection point of the emitters of the transistors Q7, Q9, and Q8, the common connection point of the emitter of Q10 is It is connected to a constant current source having a current value of 2I _0x . Enter the second input voltage V _y, output current I _y ^+, I _y ^- V a supplied to the transistors Q13, Q14
The -I conversion circuit is composed of a pair of differential transistors Q11 and Q12 whose emitters are degenerated via an emitter resistor _Rx to expand the linear input voltage range. Differential transistor pair Q11, Q12 inputs the second input voltage V _y between the base terminal, the transistor Q13,
The common connection point of the emitters of Q14 is connected to a constant current source having a current value of 2I _0y .

[0058] In this case, the first input voltage V _x and second
For any input voltage V _y of the linearity degree of the Gilbert multiplier using Gilbert gain cell to the pre-distortion circuit.

FIG. 9 shows still another embodiment of the present invention.
9, differences between the present embodiment, and the embodiment shown in FIG. 8 receives the first input voltage V _x, the output current ^{_{I x +, I x +,}} I x - , I _x ^- to transistors Q5, Q5 ',
A VI conversion circuit for supplying Q6 and Q6 'includes differential transistor pairs Q7, Q8 and Q9, Q10 having an emitter resistor _Rx and having a linear input voltage range expanded,
The common connection point of the emitters of the transistors Q7 and Q9 and the common connection point of the emitters of the transistors Q8 and Q10 are as follows:
Are connected to each other via two resistors connected in series, the common connection point of the two resistors RE _x is with being connected to the constant current source of a current value 4I _0x, the second input voltage V _y type, output current I _y ^+, I _x ^- the transistors Q13, Q
14 as the VI conversion circuit supplied to the emitter resistor R
a differential transistor pair Q11 and Q12 having a linear input voltage range expanded with _y . The transistors Q12 and Q13 have emitters connected to each other through two serially connected resistors, and two resistors RE. _This means that the common connection point of _y is connected to a constant current source having a current value of 4I _0y .

[0060]

As described above, according to the present invention,
This has the effect of enabling low-voltage operation and realizing complete linear operation with respect to one signal input or both signal inputs with a simple circuit configuration. Thus, according to the present invention, for the one signal input V _x, at a low voltage of about 1.9V, 1V _PP with perfectly linear input voltage range close, bipolar multiplier can be realized. This is because an inverse hyperbolic tangent-hyperbolic tangent conversion operation is realized for one signal input.

[Brief description of the drawings]

FIG. 1 is a first view of a bipolar multiplier according to the present invention.
It is a figure for explaining an embodiment.

FIG. 2 shows a second embodiment of the bipolar multiplier according to the present invention.
It is a figure for explaining an embodiment.

FIG. 3 is a diagram showing an example of a specific circuit configuration of a VI conversion circuit as an embodiment of the bipolar multiplier according to the present invention.

FIG. 4 is a characteristic diagram showing measured values of transfer characteristics of the VI conversion circuit shown in FIG. 3;

FIG. 5 is a characteristic diagram showing measured values of transfer characteristics of the bipolar multiplier shown in FIG. 2, realized using the VI conversion circuit shown in FIG. 3;

FIG. 6 is a diagram for explaining another embodiment of the bipolar multiplier according to the present invention.

FIG. 7 is a diagram for explaining another embodiment of the bipolar multiplier according to the present invention.

FIG. 8 is a view for explaining still another embodiment of the bipolar multiplier according to the present invention.

FIG. 9 is a view for explaining still another embodiment of the bipolar multiplier according to the present invention.

FIG. 10 is a diagram showing an example of a circuit configuration of a conventional bipolar multiplier.

[Explanation of symbols]

11 V-I conversion circuit Q1~Q10 bipolar transistor V _x, V _y first, second input voltage I _0, I _0x constant current source

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03F 3/68

Claims (8)

(57) [Claims] A first differential input signal having two input pairs each of which outputs a current having an equal value to each other;
A voltage-current conversion circuit (referred to as a “first VI conversion circuit”), and two pairs of transistors each driven by two pairs of output currents of the first VI conversion circuit, A second differential input signal is input to each transistor pair of the two pairs of transistors, and output voltages from respective emitters of the two pairs of transistors are used as respective input voltages, and are driven by one common constant current source. A bipolar multiplier comprising four transistors. 2. A second voltage-current conversion circuit (hereinafter, referred to as a "second VI conversion circuit") to which a second differential input signal is input.
2. The bipolar multiplier according to claim 1, further comprising a pair of transistors driven by the respective output currents. 3. The first VI conversion circuit according to claim 1, further comprising a differential pair having an emitter resistor inserted.
The described bipolar multiplier. 4. The bipolar multiplier according to claim 1, wherein said four transistors driven by said one common constant current source have collectors of respective transistor pairs cross-connected. 5. A power supply system comprising: a first output pair receiving a first differential input voltage and outputting currents of equal values; and a second output pair outputting currents of equal values. First
A voltage-current conversion circuit (VI conversion circuit), and first and second transistor pairs each having an emitter connected to the first and second output pairs of the first VI conversion circuit. A second differential input voltage signal is input between the respective base terminals of the first and second transistor pairs, the emitters are connected in common, connected to a constant current source, and the collectors are cross-connected to each other. A third transistor pair, wherein the base of each of the third transistor pairs is the first transistor pair.
And the base of each of the fourth transistor pair is connected to the emitter of one of the transistors constituting the second transistor pair.
And the output current of the third or fourth transistor pair, or the output of the third and fourth transistor pairs, respectively connected to the emitters of the other transistor constituting the second transistor pair. A bipolar multiplier, wherein a value obtained by multiplying the first differential input voltage and the second differential input voltage is obtained from a current difference current. 6. A first output pair which receives a first differential input voltage and outputs currents having the same value, and a second output pair which outputs currents having the same value. First
(Hereinafter referred to as a “first VI conversion circuit”), and a second voltage-current conversion circuit (“a second VI conversion circuit”) to which a second differential input voltage is input. "), A first and second transistor pair having an emitter connected to the first and second output pairs of the first VI conversion circuit, respectively, and A third transistor pair having an emitter connected to the output pair, an output voltage from the emitter of the third transistor pair being input between respective base terminals of the first and second transistor pairs; An emitter is commonly connected to a constant current source, and a collector includes a fourth and fifth transistor pair cross-connected to each other. The base of each of the fourth transistor pair is connected to the first transistor pair.
And the base of each of the fifth transistor pair is connected to the emitter of one of the transistors forming the second transistor pair.
And the output current of the fourth or fifth transistor pair, or the output of the third and fourth transistor pairs, respectively connected to the emitters of the other transistor constituting the second transistor pair. A bipolar multiplier, wherein a value obtained by multiplying the first differential input voltage and the second differential input voltage is obtained from a current difference current. 7. The VI conversion circuit applies a first differential input voltage to a bipolar transistor differential pair driven by a constant current source, and applies a current to the differential pair via an emitter resistor. 7. The bipolar multiplier according to claim 1, wherein a mirror circuit is connected, and an output current is taken out of the current mirror circuit. 8. The bipolar multiplier according to claim 5, wherein said VI conversion circuit comprises two pairs of differential transistors whose emitters are commonly connected via a resistor.