AU712618B2 - Bipolar multiplier using quadritail cell - Google Patents

Description

S F Ref: 372681

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFCATION FOR A STANDARD PATENT

ORIGINAL

.c 0* 00 0 0 Name and Address of Applicant: Actual Inventor(s): Address for Service: Invention Title: NEC Corporation 7-1, Shiba Minato-ku Tokyo

JAPAN

Katsuji Kimura Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Bipolar Multiplier Using Quadritail Cell The following statement is a full description of this invention, including the best method of performing it known to me/us:- 5845 BIPOLAR MULTIPLIER USING QUADRITAIL

CELL

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier circuit for multiplying two input signals and more particularly, to a bipolar multiplier having an improved linearity within a wide input voltage range, which is preferably formed on a bipolar semiconductor integrated circuit device and which is operable at a low supply voltage.

2. Description of the Prior Art A conventional bipolar multiplier is shown in Fig. 1, which was disclosed in the Japanese Examined Patent Publication No. 55-19444 published in 1980.

15 In Fig. i, two bipolar transistors QIll and Q112 whose emitters are coupled together constitute a differential amplifier.

coupled emitters of the transistors QIll and Q112 are connected through an emitter resistor to a first end of a constant current t sink 101 sinking a constant current 12. A second end of the current sink 101 is connected to the ground.

Two bipolar transistors Q113 and Q114 whose emitters are coupled together constitute another differential amplifier. The coupled emitters of the transistors Q113 and Q114 are connected through an emitter resistor to the first end of the constant -1current sink 101.

Collectors of the transistors Q111 and Q114 are coupled together to be connected to a first output terminal 102. Collectors of the transistors Q112 and Q113 are coupled together to be connected to a second output terminal 103.

Four bipolar transistors Q115, Q116, Q117, and Q118 constitute a voltage-current converter for converting a first input signal voltage V 1 into four input signal currents proportional to the voltage VI. These four bipolar transistors Q115, Q116, Q117, and Q118 further supply the input signal currents thus generated to the transistors Q111, Q112, Q113, and Q114, respectively.

Emitters of the bipolar transistors Q115 and Q116 are coupled together to be connected through an emitter resistor to a first end of a constant current sink 104 sinking a constant current Ii. A second end of the current sink 104 is connected to the ground. Emitters of the bipolar transistors Q117 and Q118 are coupled together to be connected through an emitter resistor to the first end of the constant current sink 104.

20 Bases of the transistors Q115 and Q116 are coupled together. Bases of the transistors Q117 and Q118 are coupled together. The first input signal voltage V, is applied across the coupled bases of the transistors Q115 and Q116 and those of the transistors Q117 and Q118.

A collector of the transistor Q115 is connected to a base of the transistor Q111. A collector of the transistor Q116 is connected to a base of the transistor Q113. A collector of the transistor Q117 is connected to a base of the transistor Q112.

A collector of the transistor Q118 is connected to a base of the transistor Q114.

Four bipolar transistors Q119, Q120 Q121, and Q122 serves to apply a second input signal voltage V 2 to the transistors Q111, Q112, Q113, and Q114, respectively.

Emitters of the transistors Q119, Q120, Q121, and Q122 are connected to the bases of the transistors Qlll, Q112, Q113, and Q114, respectively. Bases of the transistors Q119 and Q120 are coupled together. Bases of the transistors Q121 and Q122 are coupled together. The second input signal voltage V 2 is applied 15 across the coupledbases of the transistors Q119 and Q120 and those of the transistors Q121 and Q122. Collectors of the transistors Q119, Q120, Q121, and Q122 are applied with a power supply voltage.

In Fig. 1, the characterx denotes the rate of the constant current Ii flowing through the emitter resistor for the 20 transistors Q115 and Q116. Similarly, the character y denotes the rate of the constant current I2 flowing through the emitter resistor for the transistors Q111 and Q112. The rates of x and y vary dependent upon the applied first and second input signal voltages Vi and V 2 respectively.

In this case, the currents flowing through the transistors Qll1, Q112, Q113, Q114, Q115, Q116, Q117, and Q118 are expressed as shown in Fig. 1, respectively, where a and b are positive constants.

Here, the collector current ayI 2 is defined as I, i.e., ayI 2 and the current yl2 flowing thorough the emitter resistor for the transistors Q111 and Q112 is defined as Ie, y2 Ie. Then, Ic (1 x)Ie is established.

This means that the output current Ic of the differential amplifier comprised of the transistors Q111 and Q112 is independent of the input current (x/2)I1 and that it varies dependent upon the rate x only. Therefore, the output current Ic 99 15 has a linear characteristic and no temperature dependence.

9 9 The same reason is applicable to the differential amplifier comprised of the transistors Q113 and Q114.

As a result, the conventional bipolar multiplier of Fig.

1 is capable of multiplication of the first and second input signal 99* 20 voltages Vi and V 2 However, the Japanese Examined Patent Publication No.

S* 55-19444 only disclosed the current distribution in the conventional multiplier of Fig. 1 as the explanation about the circuit analysis. Therefore, the circuit operation of the conventional multiplier of Fig. 1 is extremely difficult to be understand. The reason is that the current distribution is not clear in each of the differential pairs of the transistors Q111 and Q112 and Q113 and Q114; in other words, the circuit analysis in the conventional multiplier of Fig. 1 is not based on the physical principle of the bipolar transistors.

Further, the transistors Qll, Q112, Q113, and Q114 are driven by the single constant current sink 101 and therefore, the subcircuit comprised of the transistors Q111, Q112, Q113, and Q114 may be termed the "quadritail cell" or "multiplier core". The circuit analysis of this "quadritail cell" or "multiplier core" is extremely difficult, because of the existence of the emitter resistors.

With reference to an article written by the inventor, 15 Kimura, IEICE Trans. Fundamentals, Vol. E78-A, No. 5, pp. 560 565, issued in May 1995, entitled "A Bipolar Very Low-Voltage Multiplier Core Using a Quadritail Cell", it is certain that the conventional multiplier of Fig. 1 is capable of the multiplication behavior of the first and second input signal voltages VI and V 2 20 as disclosed in the Japanese Examined Patent Publication No.

55-19444.

a 9* *aa.

a a a.

ar a.

However, the conventional multiplier of Fig. 1 does not have the satisfactory linearity in multiplication behavior.

On the other hand, a multiplier is an essential, basic function block in analog signal applications. Recently, fabrication processes for large-scale integrated circuit devices (LSIs) have been becoming finer and finer and as a result, the supply voltage for the LSIs has been decreasing from 5 V to 3 V, or lower. This tendency has been increasing the necessity for the low-voltage circuit technique more and more.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multiplier capable of completely linear operation within the entire operable input range with respect to one of two input signals to be multiplied.

Another object of the present invention is to provide a S 15 multiplier capable of completely linear operation within the Se..entire operable input range with respect to both input signals to be multiplied.

Still another object of the present invention is to provide a multiplier capable of operation at a low power supply 4**e 20 voltage such as approximately 1.9 V with respect to at least one of two input signals to be multiplied.

CThe above objects together with others not specifically a mentioned will become clear to those skilled in the art from the following description.

-6i According to a first aspect of the present invention, a bipolar multiplier is provided.

This multiplier includes a quadritail cell formed by emitter-coupled first, second, third, and fourth bipolar transistors driven by a single constant current source/sink, (b) a voltage-current converter for converting an applied first initial input voltage to a first pair of output currents and a second pair of output currents, a first transistor pair of fifth and sixth bipolar transistors driven by the first pair of output currents, and generates a first pair of output voltages, respectively, and a second transistor pair of seventh and eighth bipolar transistors driven by the second pair of output currents, and generates a second pair of output voltages, respectively.

15 Collectors of the first and fourth transistors of the quadritail cell are coupled together to form a first output terminal. The first and fourth transistors constitute a differential pair.

Collectors of the second and third transistors of the 5555 20 quadritail cell are coupled together to form a second output terminal. The second and third transistors constitute another S"differential pair.

A second initial input voltage is applied across bases of the fifth and seventh transistors and across bases of the sixth -7and eighth transistors, respectively.

The first pair of output voltages from the first transistor pair of fifth and sixth transistors are differentially applied across bases of the first and fourth transistors of the quadritail cell.

The second pair of output voltages from the second transistor pair of seventh and eighth transistors are differentially applied across bases of the second and third transistors of the quadritail cell.

An output of the multiplier including the multiplication result of the first and second initial input voltages is derived from at least one of the first and second output terminals.

With the multiplier according to the first aspect of the present invention, a first input voltage is converted to the first S 15 pair of differential output currents and the second pair of 0* differential output currents by the voltage-current converter.

The first transistor pair of fifth and sixth transistors are respectively driven by the first pair of differential output

V.

currents thus generated. The second transistor pair of seventh '*9:6 020 and eighth transistors are respectively driven by the second 00 0 differential output currents thus generated. A second input ee :voltage is applied across bases of the fifth and seventh transistors and across bases of the sixth and eighth transistors, respectively.

-8-

I

Thus, the first pair of output voltages, which are generated by the first transistor pair of fifth and sixth transistors, have a value proportional to an arc hyperbolic tangent (tanh- 1 of the first initial input voltage. The second pair of output voltages, which are generated by the second transistor pair of seventh and eighth transistors, have a value proportional to an tanh 1 of the first input voltage.

On the other hand, the first and fourth transistors of the quadritail cell, which constitute a differential transistor pair, has a hyperbolic tangent (tanh) transfer characteristic with respect to the differentially-applied first pair of output voltages. Similarly, the second and third transistors of the quadritail cell, which constitute another differential transistor pair, has a tanh transfer characteristic with respect 15 to the differentially-applied second pair of output voltages.

aa Therefore, the first initial input voltage is tanh- 1 converted by the voltage-current converter, and then, it is tanh-converted by the differential pair of the first and fourth transistors of the quadritail cell and by the differential pair a a 20 of the second and third transistors thereof.

a Because the output of the multiplier including the a multiplication result of the first and second initial input voltages is derived from at least one of the first and second output terminals, the multiplication operation of the multiplier -9- I j according to the first aspect is completely linear with respect to the first initial input voltage.

This means that this multiplier is capable of completely linear operation within the entire operable input range with respect to one of two input signals to be multiplied.

Further, the tanh conversion of the first input voltage is performed with the use of the V-I converter, the first transistor pair of the fifth and sixth transistors, and the second transistor pair of the seventh and eighth transistors.

Accordingly, the necessary power supply voltage can be decreased, resulting in that the multiplier according to the first aspect is operable at a low supply voltage such as approximately 1.9 V.

In a preferred embodiment of the multiplier according to the first aspect, the V-I converter includes a differential pair 0S 15 of ninth and tenth bipolar transistors and an emitter resistor connected to emitters of the ninth and tenth transistors.

In this case, it is preferred that the V-I converter further includes first and second current mirror circuits. The first pair of output currents and the second pair of output S 20 currents are derived through the first and second current mirror circuits, respectively.

It is preferred that each of the first and second current mirror circuits has an emitter-follower bipolar transistor.

mirror circuits has an emitter-follower bipolar transistor.

I

In another preferred embodiment of the multiplier according to the first aspect, the V-I converter includes a differential pair of ninth and tenth bipolar transistors and serially-connected first and second emitter resistors. The first and second emitter resistors are connected to emitters of the ninth and tenth transistors, respectively.

In still another preferred embodiment of the multiplier according to the first aspect, the V-I converter includes a differential pair of ninth and tenth bipolar transistors and a differential pair of eleventh and twelfth bipolar transistors connected in parallel, and serially-connected first and second emitter resistors. The first and second emitter resistors are connected to emitters of the ninth and tenth transistors and emitters of the eleventh and twelfth transistors, respectively.

g 15 According to a second aspect of the present invention, a ae another bipolar multiplier is provided, which is equivalent to one obtained by adding another V-I converter for converting the applied second initial input voltage to a third pair of output S- currents, and a third transistor pair of ninth and tenth 20 bipolar transistors driven by the third pair of output currents, and generate a third pair of output voltages, respectively.

The third pair of output voltages from the third a. a, transistor pair are differentially applied across bases of the fifth and sixth transistors and across bases of seventh and eighth -11transistors.

With the multiplier according to the second aspect of the present invention, the second initial input voltage is converted to the third pair of differential output currents by the corresponding V-I converter. The third transistor pair of ninth and tenth transistors are respectively driven by the third pair of differential output currents thus generated.

Thus, the third pair of output voltages, which are generated by the third transistor pair of ninth and tenth transistors, have a value proportional to an tanh 1 of the second initial input voltage.

Therefore, because of the same reason as that of the first initial input voltage, the multiplication operation of the multiplier according to the second aspect is completely linear 15 with respect to the second initial input voltage also.

This means that this multiplier is capable of completely linear operation within the entire operable input ranges with respect to both of two input signals to be multiplied.

Further, since the tanh conversion of the second initial 20 input voltage is performed with the use of the corresponding

V-I

converter and the third transistor pair of ninth and tenth transistors, the necessary power supply voltage can be decreased.

As a result, the multiplier according to the second aspect is operable at a low supply voltage such as approximately 1. 9 V with -12-

I

respect to the first and second initial input voltages.

In the multiplier according to the second aspect, the first V-I converter may be configured in the same way as that of the first aspect.

In a preferred embodiment of the multiplier according to the second aspect, the second V-I converter includes a differential pair of eleventh and twelfth bipolar transistors and an emitter resistor connected to emitters of the The first and second emitter resistors are connected to emitters of the eleventh and twelfth bipolar transistors, respectively.

In another preferred embodiment of the multiplier according to the second aspect, the second V-I converter includes a differential pair of eleventh and twelfth bipolar transistors and a differential pair of thirteenth and fourteenth bipolar S* 15 transistors connected in parallel, and serially-connected first 4, 40, and second emitter resistors. The first and second emitter resistors are connected to emitters of the eleventh and twelfth transistors and emitters of the thirteenth and fourteenth

S.

transistors, respectively.

.555 BRIEF DESCRIPTION OF THE DRAWINGS In order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings.

-13i Fig. 1 is a circuit diagram of a conventional bipolar multiplier.

Fig. 2 is a circuit diagram of a bipolar multiplier according to a first embodiment of the present invention.

Fig. 3 is a circuit diagram of a bipolar multiplier according to a second embodiment of the present invention.

Fig. 4 is a circuit diagram of a voltage-current converter used in the multiplier according to the first and second embodiments.

Fig. 5 is a graph showing the measured dc transfer characteristics of the voltage-current converter shown in Fig.

4.

Fig. 6 is a graph showing the measured dc transfer characteristics of the bipolar multiplier according to the second embodiment of Fig. 4.

Fig. 7 is a circuit diagram of a bipolar multiplier according to a third embodiment of the present invention.

C

Fig. 8 is a circuit diagram of a bipolar multiplier

S.

S..according to a fourth embodiment of the present invention.

g e.

Fig. 9 is a circuit diagram of a bipolar multiplier according to a fifth embodiment of the present invention.

S SFig. 10 is a circuit diagram of a bipolar multiplier according to a sixth embodiment of the present invention.

-14- DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below while referring to the drawings attached.

FIRST EMBODIMENT A bipolar multiplier according to a first embodiment is shown in Fig. 2.

As shown in Fig. 2, this multiplier includes a quadritail cell 10, a voltage-current converter circuit 11, a balanced transistor pair 13 comprised of npn bipolar transistors Q5 and and a balanced transistor pair 14 comprised of npn bipolar transistors Q6 and Q6'.

The quadritail cell 10 is formed by four npn bipolar transistors Ql, Q2, Q3, and Q4 whose emitters are coupled together to be connected to one end of a constant current sink 1 sinking a constant current Io. The other end of the current sink 1 is connected to the ground. The emitter areas of the transistors

Q,.

i: Q2, Q3, and Q4 are equal to each other.

The transistors Ql and Q4 constitute a differential transistor pair, and the transistors Q2 and Q3 constitute another o differential transistor pair. Therefore, it can be said that the quadritail cell 10 is a combination of these two differential transistor pairs connected in parallel.

Bases of the transistors Q1 and Q4 are connected to emitters of the transistors Q5 and Q6 of the first transistor pair 13, respectively. Bases of the transistors Q2 and Q3 are connected to emitters of the transistors Q6' and Q5' of the second transistor pair 14, respectively.

Collectors of the transistors Q1 and Q4 are coupled together to be connected to a load resistor 3 with a resistance RL. The other end of the resistor 3 is applied with a power supply voltage Vcc. In other words, the collectors of the transistors Q1 and Q4 are coupled together to be applied with the power supply voltage Vcc through the load resistor 3, respectively.

Collectors of the transistors Q2 and Q3 are coupled together to be connected to a load resistor 4 with the same resistance RL as that of the resistor 3. The other end of the 15 resistor 4 is applied with the power supply voltage Vcc. In other words, the collectors of the transistors Q2 and Q3 are coupled 0* together to be applied with the power supply voltage Vcc through the load resistor 4, respectively.

0 A first output terminal T5 is connected to the connection 0* 20 point of the resistor 3 and the coupled collectors of the transistors Q1 and Q4. A second output terminal T6 is connected 0 to the connection point of the resistor 4 and the coupled collectors of the transistors Q2 and Q3.

-16- The V-I converter circuit 11 has first and second input terminals T1 and T2 and first, second, third, and fourth output terminals lla, llb, llc, and lid. A first input signal voltage Vx, is applied across the input terminals T1 and T2. The first output terminal lla is connected to the emitter of the transistor Q5 and the base of the transistor QI. The second output terminal llb is connected to the emitter of the transistor Q5' and the base of the transistor Q3. The third output terminal llc is connected to the emitter of the transistor Q6 and the base of the transistor Q4. The fourth output terminal lid is connected to the emitter of the transistor Q6' and the base of the transistor Q2.

The V-I converter circuit 11 generates a first pair of differential output currents proportional to the applied first input signal voltage V, and a second pair of differential output 15 currents proportional to the applied first input signal voltage a When the first pair of differential output currents are a defined as I, and where I, and have the same current value and opposite polarities, the second pair of differential output 20 currents can be expressed as I, and Ix-.

The output current I, of the first pair flows into the *Oaaaa converter circuit 11 through the first output terminal lla. The output current of the first pair flows into the converter circuit 11 through the second output terminal llb. The output -17current of the second pair flows into the converter circuit 11 through the third output terminal llc. The output current I, of the second pair flows into the converter circuit 11 through the fourth output terminal lid.

Bases of the transistors Q5 and Q6 of the first transistor pair 13 are coupled together to be connected to a third input terminal T3. Bases of the transistors Q5' and Q6' of the second transistor pair 14 are coupled together to be connected to a fourth input terminal T4. A second input signal voltage Vy is applied across the third and fourth input terminals T3 and T4.

A positive electrode of a constant voltage source 2 supplying a constant voltage VR is connected to the fourth input terminal T4. A negative electrode of the voltage source 2 is connected to the ground. Thus, the constant voltage VR is 15 superposed on the second input signal voltage Vy as a bias voltage, and applied across the third and fourth input terminals T3 and T4 4 Collectors of the transistors Q5, Q5', Q6, and Q6' are applied with the power supply voltage Vcc, respectively.

94« 20 The transistors Q5 and Q6 of the first transistor pair 13 are driven by the first pair of differential output currents 99** S* and Ix- of the V-I converter 11, respectively. The transistors and Q6' of the second transistor pair 14 are driven by the second pair of differential output currents I, and of the V-I -18converter 11, respectively.

Next, the operation of the bipolar multiplier according to the first embodiment is explained in detail below.

Here, supposing that the base-width modulation the Early voltage) is ignored, a collector current Ic of a unit bipolar transistor is typically expressed as the following equation Ic Is exp (VB

VT

In the equation VBE is the base-to-emitter voltage of the transistor, and Is is the saturation current thereof. VT is the thermal voltage defined as VT kT/q, where k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, .0 and q is the charge of an electron.

*0 15 In the following analysis, for the sake of simplification, it is supposed that the common-base current gain factor of the 0 transistor is approximately equal to unity and therefore, the base r* current can be ignored.

*.*The differential output currents I and Ix~ are proportional to the first input signal voltage Vx, they can be expressed as the following equations and respectively.

a.

0 -19- I_ _I II~~ Ix+ o GxV (2) S-=ox GxVx (3) where Iox is a constant and 2Gx is the conductance of the V-I converter circuit 11.

From the equations and the difference AIx of the differential output currents Ix and is expressed as Ax 2Gx (4) On the other hand, since the transistors Q5 and Q6 of the first transistor pair 13 are driven by the first pair of differential output currents Ix and Ix-, respectively, the

OO

S S following equations and are established by using the above e 0 15 equation (1) Sx c s exp VBE5

V

VBE6 x IC6 s exp (6) Sr where Ic5 and Ice are the collector currents of the transistors and Q6, and VBE5 and VBE6 are the base-to-emitter voltages thereof, respectively.

Similarly, since the transistors Q5' and Q6' of the second transistor pair 14 are driven by the second pair of differential output currents I, and respectively, the following equations and are established by using the above equation (1) I =Ics' Is exp B (7) C6' s exp (8) C 'T 6 where Ics, and Ice, are the collector currents of the transistors and Q6', and VBE5' and VBE6' are the base-to-emitter voltages thereof, respectively.

The base-to-emitter voltages VBE5 and VBE6 serves as a first 0 pair of differential output voltages of the first transistor pair 15 13 of the transistors Q5 and Q6. The base-to-emitter voltages 0 and VBE6' serves as a second pair of differential output voltages of the second transistor pair 14 of the transistors Q5' and Q6' If the common emitter voltage of the quadritail cell is defined as VE, the base-to-emitter voltages VBE1, VBE2, VBE3, and 20 VBE4 of the transistors Ql, Q2, Q3, and Q4 of the quadritail cell 0 are expressed as the following equations and respectively.

-21- VBE 1=VR Vy VBE 10,

V

VR Vy -VTeln( XIX

XV

VBE2 VR VBE6 VR -VTo In( 1'S. G. V,- VBE 3 VR VBE VR -VToln( .V VBE 4 VR Vy VBE 6 -1Ox GV VR V-VToln( IS

)V

(9) (1 1) (12) 55

S

*5 S S 5 10 55S555 e Accordingly, by using the above equations and to (12) the collector currents Icl IC2, IC3, and IC4 of the transistors Qi, Q2, Q3, and Q4 are expressed as the following equations (13), and respectively.

S

S C *5

S

S S 555

S

55 S S *5

S

I s exp(VBE1J exp

R+V

Gx Vx (13) -22- 'C2 I s exp (BE2~ =x (K V_ (14) G, V, 'C3 I s exp (BE3J exp 'C4 Is SexpCVBE4D 1 (16) 1 x 2 VT *Since the transistors Q1, Q2f Q3, and Q4 are driven by the common constant current sink 1, the following equation (17) is established I1+IC2 +JC3 C4 aFIO0 (17) where aXF i S the common-base current gain factor.

-23- Here, the differential output current AI of the multiplier of Fig. 2 is def ined as the dif ference between the f irst output current 101 IC1 104) and the second output current 102 12 103), AI (IC 104) (102 103).- Then, by substituting the above equations (14), and (16) into the equation the differential output current AI of the multiplier of Fig. 2 is expressed as the following equation (18a) (-[cl1-C4)-(Ic 2 +IC3) aFIo[I1-exp VYJJ< Is ('Ox L ±exp (VV-)j (18a) *~F1 L 4IKO> .tanh( 2V2 The equation (18a) can be approximated to the following equation (18b) as *G S AIlt CIFIO K0~ D 2. (18b) Ox 2VT -24where IVyI 2

VT.

It is seen from the equation (18b) that the differential output current AI includes the multiplication result of the first and second input signal voltages Vx and Vy and that the multiplication behavior is completely linear with respect to the first input signal voltage Vx.

Additionally, one of the first output current Ioi Ici Ic4) and the second output current Io2 Ic2 IC3) may be used as an output of the multiplier of Fig. 2, because each of them contains the multiplication result as shown in the following equations (18c) and (18d).

I01 (cl+ 'C4) 102 IC2 IC3 1 GS. V1 aFI1O tanh V (18d) 2 ^x (28d *of Fig. 2 is applicable, for example, to a frequencymixer, where the local signal input requires no completely linear behavior and the local signal input requires no completely linear behavior and 1 the radio-frequency signal input requires the completely linear behavior. In this case, the first input signal voltage Vx is used as the radio-frequency signal input and the second input signal Vy is used as the local signal input.

Additionally, if first and second output voltages are defined as Vol and Vo 2 respectively, Vol and Vo2 are expressed as Vol IoI*RL, and Vo 2 I02*RL.

A differential output voltage AVo is defined as AVo Vol Vo2 RL(Iol 102) With the bipolar multiplier according to the first embodiment of Fig. 2, the first input signal voltage V, is converted to the first pair of differential output currents Ix and Ix- and the second pair of differential output currents Ix and Ix by the voltage-current converter circuit 11.

The transistors Q5 and Q6 forming the first transistor pair 13 are respectively driven by the first pair of differential output currents Ix and Ix- thus generated. The transistors and Q6' forming the second transistor pair 14 are respectively driven by the second pair of differential output currents Ix and Ix- thus generated.

Further, the first pair of output voltages of the transistor pair 13 are differentially applied across the bases of the transistors Q1 and Q4. Similarly, the second pair of output a

CS.

a *0c -26voltages of the transistorsQ5' and Q6' are differentially applied across the bases of the transistors Q3 and Q2.

From the above equation it is seen that the difference AIx of the differential output currents I, and Ix- does not contain any hyperbolic tangent (tanh) term of This means that the V-I converter circuit 11 has a tanh 1 function characteristic. Thus, each of the output voltages is proportional to a value of an tanh 1 of the first input signal voltage Vx.

Therefore, the tanh transfer characteristic of the quadritail cell 10 are canceled by the tanh 1 characteristic of the first and second pair of output voltages, respectively.

As a result, the multiplication operation of the multiplier according to the first embodiment of Fig. 2 is completely linear with respect to the first input voltage Vx. This means that this multiplier is capable of completely linear operation within the entire operable input range with respect to one of two input signals to be multiplied.

Additionally, since the tanh 1 conversion of the first input voltage Vx is performed with the use of the V-I converter 20 circuit 11 and the first transistor pair 13 of the transistors and Q6, and the second transistor pair 14 of the transistors and Q6', the necessary power supply voltage can be decreased.

As a result, the multiplier according to the first embodiment is operable at a low supply voltage such as -27approximately 1.9 V.

Next, the V-I converter circuit 11 is explained in detail below.

Fig. 4 shows an example of the V-I converter circuit 11 used in the multiplier according to the first embodiment of Fig.

2. In Fig. 4, this V-I converter circuit 11 has a balanced differential pair of npn bipolar transistors Q21 and Q22 whose emitter areas are equal to each other.

Emitters of the transistors Q21 and Q22 are coupled together through a common emitter resistor R21 having a resistance Rx. The emitter of the transistor Q21 is further connected to the ground through a first current mirror circuit 21 formed by npn bipolar transistors Q23, Q25, Q26, and Q29. The emitter of the transistor Q22 is further connected to the ground through a second current mirror circuit 22 formed by npn bipolar transistors Q24, Q27, Q28, and *0 Each of the first and second current mirror circuits 21 and 22 is here a type of an emitter-follower-augmented current mirror. It is needless to say that any other type of current mirror 00* 20 circuits may be used.

The first and second current mirror circuits 21 and 22 serve as active loads of the transistors Q21 and Q22, respectively.

The first pair of differential output currents with the same current value I, are derived from the first current mirror circuit -28- 21. The second pair of differential output currents with the same current value are derived from the second current mirror circuit 22.

A collector of the transistor Q21 is applied with a power supply voltage Vcc through a constant current source 21 supplying a constant current Iox. The transistor Q21 is driven by the constant current Iox.

A collector of the transistor Q22 is applied with the same power supply voltage Vcc through a constant current source 22 supplying the same constant current 0x, as that of the current source 21. The transistor Q22 is driven by the constant current Iox.

A base of the transistor Q21 is connected to the input terminal Tl. Abase of the transistor Q22 is connected to the input 15 terminal T2. A first input voltage Vx is differentially applied a across the input terminals T1 and T2.

4* A current i will flow through the emitter resistor R21 according to the value of the first input voltage Vx.

In the first current mirror circuit 21, bases of the a S transistors Q23, Q25, and Q26 are coupled together. Emitters of the transistors Q23, Q25, and Q26 are connected to the ground.

aS A collector of the transistor Q23 is connected to the emitter of the transistor Q21. Collectors of the transistors Q25 and Q26 are connected to the first and second output terminals lla and llb, -29respectively. The transistor Q29 serves as an emitter-follower transistor.

In the second current mirror circuit 22, bases of the transistors Q24, Q27, and Q28 are coupled together. Emitters of the transistors Q24, Q27, and Q28 are connected to the ground.

A collector of the transistor Q24 is connected to the emitter of the transistor Q22. Collectors of the transistors Q27 and Q28 are connected to the third and fourth output terminals llc and lid, respectively. The transistor Q30 serves as an emitter-follower transistor.

The emitter areas of the transistors Q23, Q24, Q25, Q26, Q27, Q28, Q29, and Q30 are equal to each other.

With the V-I converter circuit shown in Fig. 4, since the transistors Q21 and Q22 are driven by the same constant current Iox, the base-to-emitter voltages VBE21 and VBE22 are equal to each other, thereby shifting the voltages at the input terminals T1 and T2 by the equal voltages VBE2 1 and VBE22, respectively. Therefore, the first input signal voltage V, is applied across the emitter resistor R21. This means that the emitter resistor R21 serves as 20 a "floating resistor".

Accordingly, the current i is expressed as i 1- (19)

R

Thus, the output currents Ix and Ix- outputted from the first and second current mirror circuits 21 and 22 are given by the following equations (20) and respectively.

x= i

R,

x- =ox -i =Iox x (21) Rx If the conductance of (1/Rx) is defined as Gx in the equations (20) and the above equations and are obtained.

It is seen from the equations (20) and (21) that the linearity of the V-I converter circuit 11 is dominantly determined by the linearity of the emitter resistor R21.

With the V-I converter circuit 11 shown in Fig. 4, the transistors Q21 and Q22 constituting the differential pair are respectively driven by the corresponding constant current sources 21 and 22, respectively. Therefore, the voltage applied across the emitter resistor R21 is equal to the first input voltage Vx, S 20 which means that the resistor R21 is equivalent to a "floating resistor".

-31- ~ji li^_ Also, the current i flowing through the resistor R21 is taken out with the use of the first and second current mirror circuits, without logarithmically compression nor exponentially expansion. As a result, a completely or perfectly linear conversion operation can be obtained within a specific voltage range of the input voltage Vx with a simple circuit configuration.

Further, no circuit for logarithmically compressionand exponentially expansion is required and therefore, the necessary power supply voltage Vcc can be decreased. Thus, the converter circuit 11 of Fig. 4 is operable at a low supply voltage such as approximately 1.9 V.

Fig. 5 shows the dc transfer characteristics of the converter circuit llof Fig. 4, which was obtained by inventor's tests. In Fig. 5, the differential output current of the circuit 4* 15 11 is indicated in voltage. The testing condition is as follows.

0 The power supply voltage Vcc is 1. 9V, the driving current Io. is approximately 50 pA, the load resistance is 18 kQ. The 0 voltage applied across the resistor R21 is 1.4V.

It is seen from Fig. 5 that the linear input voltage range See" 20 is approximately equal to 800 mVpp, and that the Total Harmonic Distortion (THD) at 1 kHz of the frequency of Vx is equal to 0.1 **ee: or less.

SECOND EMBODIMENT -32- A bipolar multiplier according to a second embodiment is shown in Fig. 3, which is equivalent to one obtained by adding a second V-I converter 12 for converting the applied second input voltage Vy to a third pair of differential output currents Iy' and Iy-, and a third transistor pair 15 of npn bipolar transistors Q7 and Q8 driven by the third pair of differential output currents Iy and Iy-, respectively.

Therefore, the description relating to the same configuration is omitted here by adding the same reference numerals/characters as those in the multiplier according to the first embodiment of Fig. 2 for the sake of simplification of description.

The second V-I converter circuit 12 has the third and fourth input terminals T3 and T4 and fifth and sixth output 9• 15 terminals 12a and 12b. The second input signal voltage Vy is applied 9.

across the input terminals T3 and T4. The fifth output terminal 12a is connected to the emitter of the transistor Q7 and the bases of the transistors Q5' and Q6'. The sixth output terminal 12b is connected to the emitter of the transistor Q8 and the bases of the transistors Q.

9 9 The second V-I converter circuit 12 generates the third "C pair of differential output currents proportional to the applied second input voltage Vy.

second input voltage V,.

-33ii The third pair of differential output currents are expressed as Iy and Iy-, where Iy and Iy- have opposite polarities.

The output current Iy of the third pair flows into the second converter circuit 12 through the fifth output terminal 12a.

The output current Ix- of the third pair flows into the second converter circuit 12 through the sixth output terminal 12b.

An emitter of the transistor Q7 is connected to the bases of the transistors Q5' and Q6'of the second transistor pair 14.

An emitter of the transistor Q8 is connected to the bases of the transistors Q5 and Q6 of the first transistor pair 13. Collectors of the transistors Q7 and Q8 are applied with a power supply voltage Vcc'. Bases of the transistors Q7 and Q8 are coupled together to be applied with the power supply voltage Vcc'.

The transistors Q7 and Q8 of the third transistor pair 15 15 are driven by the third pair of differential output currents I y and Iy, respectively. Therefore, the following equations (22) and (23) are established in the same way as that of the transistors Q5 and Q6 20 I7 JOy Gy V= Is exp (22) *r 6@

S

S.

S

S

S.

S..

S S S S .5

*S

S

S S

S

S

S.

yI Ic8 Oy Gy V Is exp (BE8 v

T

(23) -34where Ic7 and Ic8 are the collector currents of the transistors Q7 and Q8, VBE7 and VBES are the base-to-emitter voltages thereof, respectively, Ioy is a constant, and 2GY is a conductance of the second V-I converter circuit 12.

From the equations (22) and the difference AIY of the differential output currents Iy and Iy- is expressed as Al 2G V (24) Then, in the similar way as that of the first embodiment, the differential output current AI of the multiplier of Fig. 3 is expressed as the following equation .'6j A/ (CI 1C4 -(IC2 -Tc3) is seen from the equation (25) that the differential output current AI includes the multiplication result of the first second input signal voltages Vx and Vy, and that the multiplication behavior is completely linear with respect to both of the first and second input signal voltage Vx and Vy.

With the bipolar multiplier according to the second embodiment of Fig. 3, since the second input voltage Vy is converted to the third pair of differential output currents Iy and Iy-, the third differential output voltage has a value proportional to an tanh-1 of the second initial input voltage. The tanh-l-converted second input voltage Vy is then differentially inputted into the quadritail cell through the first transistor pair of the transistors Q5 and Q6 and the second transistor pair of the transistors Q5' and Q6'.

As a result, the multiplication operation of the multiplier according to the second embodiment is completely linear with respect to the first and second input voltages Vx and Vy. This means that this multiplier is capable of completely linear operation within the entire operable input range with respect to 0 6 15 both two input signals to be multiplied.

Further, the tanh 1 conversion of the first and second input voltages Vx and Vy are performed with the use of the first and second V-I converter circuits 11 and 12, and the first transistor pair of the transistors Q5 and Q6, the second transistor 20 pair of the transistors Q5' and Q6', and the third transistor pair of the transistors Q7 and Q8. Consequently, the multiplier according to the second embodiment is operable at a low supply voltage such as approximately 1.9 V for Vcc and 2.8 V for Vcc' Fig. 6 shows the dc transfer characteristics of the -36multiplier according to the second embodiment of Fig. 3 with Vy as a parameter where Vy 0, 200 mV, or 400 mV, which was obtained by inventor's tests. In Fig. 6, the differential output current of the multiplier is indicated in voltage. The testing condition is as follows.

The power supply voltage Vcc is 1.9 V, Vcc' is 2.8 V, the driving current I0x is approximately 100 iA, the load resistance RL is 8.2 kQ.

It is seen from Fig. 6 that the multiplication operation of the multiplier according to the second embodiment is completely linear with respect to the first and second input voltages Vx and Vy, thereby realizing an ideal multiplication characteristics.

THIRD EMBODIMENT It is preferred that the V-I converter circuit 11 in the :Y 15 multiplier according to the first embodiment of Fig. 2 is capable of completely-linear multiplication operation. However, if the i. circuit configuration is drastically simplified, the linear operation may be degraded until at a level where the severe

C.

C

linearity is not necessary during the practical operation.

C.

20 A bipolar multiplier according to a third embodiment of Fig. 7 is applicable to such cases.

The multiplier according to a third embodiment of Fig.

7 has the same configuration as that of the multiplier according -37to the first embodiment of Fig. 2, except for the configuration of the V-I converter 11. Therefore, for the sake of simplification, the description relating to the same configuration is omitted here by adding the same reference numerals/characters as those in the multiplier according to the first embodiment of Fig. 2.

As shown in Fig. 7, the V-I converter 11 includes a differential pair of npn bipolar transistors Q37 and Q38, and another differential pair of npn bipolar transistors Q39 and connected in parallel to the differential pair of the transistors Q37 and Q38.

Emitters of the transistors Q37 and Q38 are coupled together through a common emitter resistor R31 with a resistance Rx. Emitters of the transistors Q39 and Q40 are coupled together through the common emitter resistor R31. The resistor R31 serves 15 to expand the linear input voltage range of Vx due to the emitter degeneration.

The coupled emitters of the transistors Q37 and Q39 are connected to the ground through a constant current sink 31 sinking a constant current 2Iox. The transistors Q37 and Q39 are driven 20 by the current sink 31. The coupled emitters of the transistors Q38 and Q40 are connected to the ground through a constant current sink 32 sinking the same constant current 2Iox as that of the 0* current sink 31. The transistors Q38 and Q40 are driven by the current sink 32.

-38- The first input signal voltage Vx is applied across bases of the transistors Q37 and Q38 and across the bases of the transistors Q39 and Q40 through the first and second input terminals T1 and T2.

A collector of the transistor Q37, which serves as the first output terminal lla, is connected to the emitter of the transistor Q5. A collector of the transistor Q40, which serves as the third output terminal llc, is connected to the emitter of the transistor Q6. A collector of the transistor Q39, which serves as the second output terminal lla, is connected to the emitter of the transistor Q5'. A collector of the transistor Q38, which serves as the fourth output terminal lld, is connected to the emitter of the transistor Q6' With the multiplier according to the third embodiment of 15 Fig. 7, the transistors Q37, Q38, Q39, and Q40 constituting the *0

S.

respective differential pairs have the V-I conversion function and the tanh 1 conversion function and therefore, the same 0 advantage as those in the first embodiment is obtained, except that the linearity of the multiplication operation is 20 approximately equal to that of the well-known Gilbert multiplier using the well-known Gilbert gain cell as the predistortion circuit.

0*

EMBODIMENT

FOURTH EMBODIMENT -39- A bipolar multiplier according to a fourth embodiment is shown in Fig. 8, which is the same in configuration as the multiplier according to the third embodiment of Fig. 7, except for the configuration of the V-I converter 11.

As shown in Fig. 8, the V-I converter 11 includes a differential pair of npn bipolar transistors Q47 and Q48, and another differential pair of npn bipolar transistors Q49 and connected in parallel to the differential pair of the transistors Q47 and Q48.

Emitters of the transistors Q47 and Q48 are coupled together through two common emitter resistors R41 and R42 with a same resistance The resistors R41 and R42 are connected in series. Emitters of the transistors Q49 and Q50 are coupled together through the common emitter resistors R41 and R42. The resistors R41 and R42 serve to expand the linear input voltage range of Vx due to the emitter degeneration.

The connection point of the resistors R41 and R42 is connected to the ground through a constant current sink 41 sinking :i a constant current 4Iox. The transistors Q37, Q38, Q39, and are driven by the common current sink 41.

The first input signal voltage Vx is applied across bases of the transistors Q47 and Q48 and across the bases of the transistors Q49 and Q50 through the first and second input t terminals T1 and T2.

A collector of the transistor Q47, which serves as the first output terminal lla, is connected to the emitter of the transistor Q5. A collector of the transistor Q50, which serves as the third output terminal lic, is connected to the emitter of the transistor Q6. A collector of the transistor Q49, which serves as the second output terminal lla, is connected to the emitter of the transistor Q5'. A collector of the transistor Q48, which serves as the fourth output terminal lid, is connected to the emitter of the transistor Q6' With the multiplier according to the fourth embodiment of Fig. 8, the transistors Q47, Q48, Q49, and Q50 constituting the respective differential pairs have the V-I conversion function and the tanh 1 conversion function and therefore, the same advantage as those in the first embodiment is obtained. The linearity of the multiplication operation is approximately equal to that of the well-known Gilbert multiplier using the well-known Gilbert gain cell as the predistortion circuit with respect to the first and second input signal voltages Vx and Vy.

FIFTH EMBODIMENT A bipolar multiplier according to a fifth embodiment is shown in Fig. 9, which corresponds to one obtained by adding the second V-I converter circuit 12 and the third transistor pair to the multiplier according to the third embodiment of Fig. 7.

In other words, the bipolar multiplier according to the fifth -41embodiment of Fig. 9 corresponds to one where the first and second V-I converter circuits 11 and 12 in the multiplier according to the second embodiment of Fig. 3 are embodied.

Specifically, the second V-I converter circuit 12 includes a differential transistor pair of npn bipolar transistors Q51 and Q52, and a common emitter resistor R51. The third transistor pair 15 is formed by npn bipolar transistors Q7 and Q8.

An emitter of the transistor Q51 is connected to the ground through a constant current sink 51 sinking a constant current 2Io.

An emitter of the transistor Q52 is connected to the ground through a constant current sink 52 sinking the same constant current 210 as that of the current sink 51. The emitters of the transistors Q51 and Q52 are coupled together through the emitter resistor R51.

The transistors Q51 and Q52 are driven by the same constant currents 2Io, respectively. The resistor R51 serves to expand the linear input voltage range of V, due to the emitter degeneration.

Bases of the transistors Q51 and Q52 are connected to the third and fourth input terminals T3 and T4, respectively. The second input voltage Vy is applied across the bases of the transistors through the terminals T3 and T4.

A collector of the transistor Q51 is connected to an emitter of the transistor Q7 of the third transistor pair 15. A 0 collector of the transistor Q52 is connected to an emitter of the -42transistor Q8 of the third transistor pair With the multiplier according to the fifth embodiment of Fig. 9, the transistors Q51 and Q52 constituting the second V-I converter circuit 12 have the V-I conversion function and the tanh 1 conversion function and therefore, the same advantage as those in the third embodiment of Fig. 7 is obtained.

The linearity of the multiplication operation is approximately equal to that of the well-known Gilbert multiplier using the well-known Gilbert gain cell as the predistortion circuit with respect to both of the first and second input voltages Vx and Vy.

SIXTH EMBODIMENT A bipolar multiplier according to a sixth embodiment is shown in Fig. 10, which corresponds to one obtained by adding the second V-I converter circuit 12 and the third transistor pair to the multiplier according to the fourth embodiment of Fig. 8.

In other words, the bipolar multiplier according to the sixth S embodiment of Fig. 10 corresponds to one where the first and second V-I converter circuits 11 and 12 in the multiplier according to the second embodiment of Fig. 3 are embodied.

Specifically, the second V-I converter circuit 12 includes a differential transistor pair of npn bipolar transistors Q61 and Q62, and common emitter resistors R61 and R62.

The third transistor pair 15 is formed by npn bipolar transistors -43- Q7 and Q8.

Emitters of the transistors Q61 and Q62 are coupled together through serially-connected emitter resistors R61 and R62.

The connection point of the resistors R61 and R62 is connected to the ground through a constant current sink 61 sinking a constant current 4Ioy. The transistors Q61 and Q62 are driven by the same constant current 41 oy, respectively. The resistors R61 and R62 serve to expand the linear input voltage range of Vy due to the emitter degeneration.

Bases of the transistors Q61 and Q62 are connected to the third and fourth input terminals T3 and T4, respectively. The second input voltage Vy is applied across the bases of the transistors Q61 and Q62 through the terminals T3 and T4.

A collector of the transistor Q61 is connected to an emitter of the transistor Q7 of the third transistor pair 15. A collector of the transistor Q62 is connected to an emitter of the transistor Q8 of the third transistor pair With the multiplier according to the sixth embodiment of Fig. 10, the transistors Q61 and Q62 constituting the second V-I converter circuit 12 have the V-I conversion function and the tanh 1 conversion function and therefore, the same advantage as S; those in the fourth embodiment of Fig. 8 is obtained.

The linearity of the multiplication operation is approximately equal to that of the well-known Gilbert multiplier -44using the well-known Gilbert gain cell as the predistortion circuit with respect to both of the first and second input voltages Vx and Vy.

While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.

a a a a *aa.

a a.

a.* a a g a a a a a a oo* go

Claims (10)

1. A bipolar multiplier comprising: a quadritail cell formedby emitter-coupled first, second, third, and fourth bipolar transistors driven by a single constant current source/sink; collectors of said first and fourth transistors being coupled together to form a first output terminal; said first and fourth transistors constituting a differential pair; collectors of said second and third transistors being coupled together to form a second output terminal; said second and third transistors constituting another differential pair; a voltage-current converter for converting an applied first initial input voltage to a first pair of output currents and a second pair of output currents; a first transistor pair of fifth and sixth bipolar transistors driven by said first pair of output currents, respectively; said first transistor pair generating a first pair of output voltages; and a second transistor pair of seventh and eighth bipolar transistors driven by said second pair of output currents, -46- j respectively; said second transistor pair generating a second pair of output voltages; a second initial input voltage being applied across bases of said fifth and seventh transistors and across bases of said sixth and eighth transistors, respectively; said first pair of output voltages from said first transistor pair of fifth and sixth transistors being differentially applied across bases of said first and fourth transistors of said quadritail cell; said second pair of output voltages from said second transistor pair of seventh and eighth transistors being differentially applied across bases of said second and third transistors of said quadritail cell; and an output of said multiplier including the multiplication result of said first and second initial input voltages being derived from at least one of said first and second output terminals.

2. A multiplier as claimed in claim 1, wherein said V-I converter includes a differential pair of ninth and tenth bipolar :transistors and an emitter resistor connected to emitters of said ninth and tenth transistors. -47- 0

3. A multiplier as claimed in claim 2, wherein said V-I converter further includes first and second current mirror circuits; said first pair of output currents and said second pair of output currents are derived through said first and second current mirror circuits, respectively.

4.A multiplier as claimed in claim 3, wherein each of said first and second current mirrors includes an emitter follower bipolar transistor. multiplier as claimed in claim 1, wherein each of said V- I converter includes a differential pair of ninth and tenth bipolar transistors and serially-connected first and second emitter resistors; and wherein said first and second emitter resistors are connected to emitters of said ninth and tenth transistors, respectively. e* e 6

6.A multiplier as claimed in claim 1, wherein each of said V- 6 I converter includes a differential pair of ninth and tenth bipolar transistors, a differential pair of eleventh and twelfth bipolar transistors connected in parallel, and serially-connected first and second emitter resistors; -48- and wherein said first and second emitter resistors are connected to emitters of said ninth and tenth transistors and emitters of said eleventh and twelfth transistors, respectively.

7. A bipolar multiplier comprising: a quadritail cell formed by emitter-coupled first, second, third, and fourth bipolar transistors driven by a single constant current source/sink; collectors of said first and fourth transistors being coupled together to form a first output terminal; said first and fourth transistors constituting a differential pair; collectors of said second and third transistors being coupled together to form a second output terminal; said second and third transistors constituting another differential pair; a first voltage-current converter for converting ai *applied first initial input voltage to a first pair of output currents and a second pair of output currents; a first transistor pair of fifth and sixth bipolar transistors driven by said first pair of output currents, 'U :.:[*respectively; said first transistor pair generating a first pair of output voltages; and e -49- N a second transistor pair of seventh and eighth bipolar transistors driven by said second pair of output currents, respectively; said second transistor pair generating a second pair of output voltages; a second V-I converter for converting an applied second initial input voltage to a third pair of output currents; a third transistor pair of ninth and tenth bipolar transistors driven by said third pair of differential output currents, respectively; said third transistor pair generating a third pair of output voltages; said first pair of output voltages from said first transistor pair of fifth and sixth transistors being differentially applied across bases of said first and fourth transistors of said quadritail cell; 0 0* said second pair of output voltages from said second S• transistor pair of seventh and eighth transistors being differentially applied across bases of said second and third transistors of said quadritail cell; said third pair of output voltages from said third transistor pair being differentially applied across bases of said 0 fifth and sixth transistors and across bases of said seventh and eh t s o a 0 eighth transistors; and an output of said multiplier including the multiplication result of said first and second initial input voltages being derived from at least one of said first and second output terminals.

8. A multiplier as claimed in claim 7, wherein said first V-I converter includes a differential pair of ninth and tenth bipolar transistors and an emitter resistor connected to emitters of said ninth and tenth transistors.

9. A multiplier as claimed in claim 8, wherein said first V-I converter further includes first and second current mirror circuits; said first pair of output currents and said second pair of output currents are derived through said first and second current mirror circuits, respectively. multiplier as claimed in claim 9, wherein each of said first and second current mirrors includes an emitter follower bipolar S transistor. converter includes a differential pair of eleventh and twelfth t -51- emitter resistors; and wherein said first and second emitter resistors are connected to emitters of said eleventh and twelfth transistors, respectively.

12.A multiplier as claimed in claim 7, wherein said first V-I converter includes a differential pair of eleventh and twelfth bipolar transistors, a differential pair of eleventh and twelfth bipolar transistors connected in parallel, and serially- connected first and second emitter resistors; and wherein said first and second emitter resistors are connected to emitters of said ninth and tenth transistors and emitters of said eleventh and twelfth transistors, respectively.

13. A bipolar multiplier substantially as described herein with reference to Figs 2,4 and 5; Figs 3,4 and 6; Fig. 7; Fig 8; Fig 9; or Fig. 10 of the accompanying drawings. DATED this TENTH day of MARCH 1997 NEC Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON S S -52-