JPH1069427A - Data distribution processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a slow processing device to process data by increasing the data processing speed and processing the data requiring high processing speeds in parallel to each other. SOLUTION: A selector 12 inputs the data (a') or (c') to a processing device 11a by setting a select signal 2a at an active level when the processed data 1 are equal to the data (a) or (c). The device 11 processes the input data and outputs them to the processing data 3 as the data (a") or (c"). Then the selector 12 inputs the data (b') or (d') to a processing device 11b by setting a select signal 2b at an active level when the data 1 are equal to the data (b) or (d). The device 11b processes the input data and outputs them to the data 3 as the data (b") or (d"). Then the data 3 are outputted to a common bus 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data distribution processing method, and more particularly to a data distribution processing method for improving the processing capability of a computer.

[0002]

2. Description of the Related Art A conventional data distribution processing system is disclosed in
Japanese Unexamined Patent Publication No. 127987 proposes the one shown in FIG. Referring to FIG. 7, a plurality of divided memories 5
In the data reading method for sequentially reading data stored in the memory 530 to 533 using the address counters 520 to 523, selection of data to be read from the memories 530 to 533 is performed by selection by the multiplexer 540 controlled by the memory controller 510 This is realized by a combination with the control in which the memory control unit 510 sequentially enables each memory by the output permission signal / OE, thereby reducing the size of the multiplexer. Further, by converting an address from the CPU into an address common to each memory and an address for selecting each memory, the memory can be divided into an arbitrary number of banks to enable high-speed data reading.

[0003]

Since the above-mentioned conventional data distribution processing method is limited to data reading,
There is a problem that it does not contribute to improvement of data processing itself.

[0004] It is an object of the present invention to improve the processing speed by performing parallel processing, and to perform data processing requiring high-speed processing with a lower-speed processing device. It is to provide a data distribution processing method.

[0005]

According to the data distribution processing method of the present invention, parallel processing is performed on serial data using a plurality of processing devices, and thereafter, the processing data is converted into serial data on a common bus. Output.

According to the data distribution processing method of the present invention, parallel processing is performed on serial data using a plurality of processing devices, and thereafter, the processing data is output to a common memory area as serial data. Is also good.

In the data distribution processing method of the present invention, parallel processing is performed on serial data using a plurality of processing devices, and thereafter, the processing data is output as serial data to a common file. Good.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing a first embodiment of the present invention. Two processing devices 1 for processing data
1a and 11b, a selector 12 for inputting the processed data 1 to the processing devices 11a and 11b,
It comprises a select signal 2a and a select signal 2b output from the selector 12. 3 is processing data,
13 is a common bus.

Next, the operation will be described with reference to FIGS. FIG. 2 is a time chart showing the operation of the first embodiment of the present invention. When the data of the data to be processed 1 is “a” or “c”, the selector 12 sets the select signal 2a to the active level and inputs the data to the processing device 11a as the data “a ′” or “c ′”. When data is input, the processing device 11a processes the data and outputs the processed data 3 as data "a" or "c". When the data of the data to be processed 1 is "b" or "d", the selector 12 sets the select signal 2b to the active level to input the data "b '" or "d'" to the processing device 11b. When the data is input, the processing device 11b processes the data and outputs the processed data 3 as data "b" or "d". The processing data 3 is output to a common bus 13.

FIG. 3 is a block diagram showing a second embodiment of the present invention. Three processing devices 1 for processing data
1a, 11b, 11c and processing devices 11a, 11
The selector 12 includes a selector 12 for inputting the processed data 1 to b and 11c, and select signals 2a, 2b and 2c output from the selector 12. 3 is processing data, 13 is a common bus.

Next, the operation will be described with reference to FIGS. FIG. 4 is a time chart showing the operation of the second embodiment of the present invention. When the data of the data to be processed 1 is “a” or “d”, the selector 12 sets the select signal 2a to the active level to input the data to the processing device 11a as data “a ′” or “d ′”. When the data is input, the processing device 11a processes the data and outputs the processed data 3 as data "a""or" d "". When the data of the data to be processed 1 is "b" or "e", the selector 12 sets the select signal 2a to the active level to input the data as "b '" or "e'" to the processing device 11a. When the data is input, the processing device 11a processes the data and outputs the processed data 3 as data "b""or" e "". Further, when the data of the data to be processed 1 is "c" or "f", the selector 12 sets the select signal 2c to the active level to input the data to the processing device 1c as data "c '" or "f'". When the data is input, the processing device 11c processes the data and outputs the processed data 3 as the data "c" or "f". The processing data 3 is output to a common bus 13.

FIG. 5 is a block diagram showing a third embodiment of the present invention. Two processing devices 1 for processing data
1a and 11b, a selector 12 for inputting the processed data 1 to the processing devices 11a and 11b,
It comprises a select signal 2a and a select signal 2b output from the selector 12. 3 is processing data,
14 is a common memory area.

Next, the operation will be described. As in the first embodiment, the selector 12 outputs the select signals 2a, 2a,
b, data is input to the processing devices 11a and 11b. When the data is input, the processing devices 11a and 11b process the data and output the data to the processing data 3. The processing data 3 is output to the common memory area 14.

FIG. 6 is a configuration diagram showing a fourth embodiment of the present invention. Two processing devices 1 for processing data
1a and 11b, a selector 12 for inputting the processed data 1 to the processing devices 11a and 11b,
Select signals 2a and 2b output from selector 12
It is composed of 3 is processing data, 15 is a common file.

Next, the operation will be described. As in the first embodiment, the selector 12 outputs the select signals 2a, 2a,
b, data is input to the processing devices 11a and 11b. When the data is input, the processing devices 11a and 11b process the data and output the data to the processing data 3. The processing data 3 is output to a common file 15.

In the first, third, and fourth embodiments, two select signals and two processing devices are provided.
In the second embodiment, an example in which three select signals and three processing devices are provided has been described. However, by having four or more select signals and four or more process devices, the processing can be further speeded up.

[0018]

As described above, according to the present invention, the processing speed is improved by performing the parallel processing, and the data processing requiring high-speed processing is processed by a lower-speed processing device. This has the effect of performing the following.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment.

FIG. 2 is a time chart showing the operation of the first embodiment.

FIG. 3 is a configuration diagram showing a second embodiment.

FIG. 4 is a time chart showing the operation of the second embodiment.

FIG. 5 is a configuration diagram showing a third embodiment.

FIG. 6 is a configuration diagram showing a fourth embodiment.

FIG. 7 is a configuration diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 processed data 2a select signal 2b select signal 2c select signal 3 processed data 11a processing device 11b processing device 11c processing device 12 selector 13 common bus 14 common memory area 15 common file

Claims (6)

[Claims] 1. A data distribution processing method comprising: performing parallel processing on serial data using a plurality of processing devices; and outputting the processed data to a common bus as serial data. 2. A data distribution processing method, wherein parallel processing is performed on serial data using a plurality of processing devices, and thereafter, the processing data is output as serial data to a common memory area. 3. A data distribution processing method wherein parallel processing is performed on serial data using a plurality of processing devices, and thereafter, the processing data is output as serial data to a common file. 4. A plurality of parallel-connected processing devices that receive serial data, distribute the serial data to the processing devices, and output data processed in parallel by the processing devices as serial data to a common bus. A data distribution processing method, comprising: 5. A plurality of processing devices connected in parallel with serial data as input, and the serial data is distributed to the processing devices, and data processed in parallel in the processing devices is stored as serial data in a common memory area. And a selector for outputting the data. 6. A plurality of parallel-connected processing devices that receive serial data, distribute the serial data to the processing devices, and output data processed in parallel by the processing devices as serial data to a common file. A data distribution processing method, comprising: