JPH1065638A - Intermediate repeating device and its warning transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer instantaneous transmission line warning to an intermediate repeating device in a downstream without affecting the fault of a signal cutoff to the intermediate repeating device in the downstream when a received signal input is cutoff in the intermediate repeating device used in a digital trunk transmission system. SOLUTION: Since a transmission signal TS is generated in synchronizing with an internal clock IC generated in a phase synchronous oscillator 15, a transmission clock and a frame to the downstream transmission line is not cut off even if the input of a reception signal RS is cutoff. Thus, they can be transferred to the downstream transmission line even on the instantaneous cutoff of the reception signal RS. A frame synchronous circuit 13 and a code error detection circuit 14 are operated in synchronizing with the received transmission line clock PC. Thus, warning to the reception signal RS can be detected even if the phase synchronous oscillator 15 breaks down.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an intermediate repeater used in a digital backbone transmission system, and more particularly to a method for transferring alarm information.

[0002]

2. Description of the Related Art A digital backbone transmission system of this type includes two terminal stations arranged opposite to each other and at least one intermediate repeater provided between the two terminal stations. Have. In other words, the intermediate relay device relays the input data signal (received signal) received from one terminal device via the upstream transmission line, and outputs the output data signal (transmission signal) via the downstream transmission line. It transmits to the other terminal device side. Each of the input data signal (received signal) and the output data signal (transmitted signal) is composed of a plurality of frames, and an overhead OH is set at a predetermined position of each frame.
Is inserted.

The intermediate repeater synchronizes the frame with the input data signal (received signal) from the upstream transmission path, separates the received overhead from the input data signal (received signal), reproduces the signal frame, and performs the reception overhead. Inserts a transmission overhead into the separated input data signal and sends an output data signal (transmission signal) to the downstream transmission path. Further, the intermediate repeater monitors disconnection of an input data signal (received signal), loss of frame synchronization, and transmission line error,
When an abnormality is detected, the alarm is transferred to the downstream transmission line by including an identification number for identifying the intermediate relay device and the content of the alarm in the transmission overhead.

A conventional intermediate repeater has a clock extracting circuit for extracting a transmission line clock from an input data signal (received signal), and a fixed oscillator for oscillating a fixed frequency local clock. Signal), the transmission line clock is switched to the local
The output data signal (transmission signal) is transmitted by switching to the clock. Here, in order to stabilize the digital backbone transmission system, the input data signal (received signal)
If the disconnection continues for a certain period of time or more, the transmission line clock is switched to the local clock. Therefore, the instantaneous interruption of the input data signal cannot be transferred to the downstream transmission path. Also,
During the period from when the input data signal (received signal) is cut off to when it is switched to the local clock, the clock transmitted to the downstream transmission line is cut off.

Various prior arts for solving this problem have been proposed. For example, Japanese Patent Publication No. 63-51426 (hereinafter referred to as prior art 1) discloses that when a failure occurs in a transmission line, a signal of a unique free-running frequency is output from a repeater in a failure section to cause a failure. A "digital relay transmission line" is disclosed, in which a section can be measured from the end of a transmission line to improve the reliability of monitoring the transmission line and achieve economical use. The digital relay transmission line of the prior art 1 uses a repeater having a timing recovery circuit and an identification recovery circuit. The timing recovery circuit includes a timing extraction circuit that extracts timing from an input signal of the repeater, and a phase-locked oscillator that generates a clock synchronized with the timing signal extracted by the timing extraction circuit. The identification reproduction circuit performs the identification reproduction of the output signal from the equalization amplifier using the output clock from the timing reproduction circuit.

Next, the operation of the digital relay transmission line of the prior art 1 will be described. Normally, an internal clock synchronized with the transmission line clock extracted by the timing extraction circuit is generated by the phase-locked oscillator, and a signal subjected to identification and reproduction using the internal clock is output to the downstream transmission line.
If the repeater input level drops or the input is disconnected,
An abnormality is detected by an input signal abnormality detection circuit, and the phase-locked oscillator is controlled to run by itself. By using the free-running clock of the phase-locked oscillator to discriminate and reproduce the noisy output from the equalizing amplifier, a random signal is generated and output to the downstream transmission line. The free-running frequency is set to a unique frequency that is different for each repeater. The terminal identifies the frequency of the clock extracted from the received signal at the terminal station, identifies the repeater that has detected an abnormality, and specifies the faulty relay section. .

Japanese Patent Laid-Open No. 1-218143 (hereinafter referred to as Prior Art 2) discloses that a frame of a fixed pulse pattern signal is phase-synchronized with a frame of an input signal, and a frame synchronization bit signal is inserted into an output signal. The "intermediate repeater" is designed to prevent the fault from spreading to intermediate repeaters after the faulty relay section
Is disclosed. The intermediate repeater of Prior Art 2 includes a receiving circuit for receiving an input signal from an upstream transmission line, a phase-locked oscillator for generating an internal clock synchronized with the transmission line clock extracted by the receiving circuit, and a frame synchronization circuit. A code error detection circuit for detecting a code error of a received signal, an AIS signal generation circuit, a signal switching control circuit and a signal switching circuit for switching a signal to an AIS based on input disconnection and frame loss detection information, and a frame signal. And a signal insertion circuit for inserting overhead.

Next, the operation of the intermediate repeater according to the prior art 2 will be described. In a normal state, a clock synchronized with the transmission line clock extracted by the receiving circuit is generated by an internal phase-locked oscillator, and frame synchronization, code error detection, frame signal insertion, and overhead insertion are performed using the internal clock. At the time of input disconnection and loss of frame synchronization, the phase-locked oscillator enters a free-running state, and performs frame signal insertion, overhead insertion and AIS generation by this free-running clock, and switches to an AIS signal by a signal switching circuit to output a signal. .

[0009]

However, the above prior arts 1 and 2 have the following problems, respectively.

In the prior art 1, each repeater has a phase-locked oscillator having a free-running frequency unique to the repeater, and evaluates a fault detection repeater by frequency identification. The free-running frequency of each repeater needs to be set so as not to overlap, including the frequency deviation including the environmental change and the aging change of the phase-locked oscillator. The frequency accuracy of a normal transmission line clock must be very high, about ± several tens ppm. For this reason, the same accuracy is required for the free running frequency, and the free running frequency must be set within this frequency range. Therefore, an oscillator having a very high free-running frequency accuracy and a very accurate frequency adjustment for each repeater are required. For this reason, there is a problem that the addition of a circuit for improving the free-running frequency accuracy of the oscillator leads to an increase in the size and cost of the oscillator, and a difficulty in manufacturing that the frequency adjustment becomes difficult.

On the other hand, in the prior art 2, since the frame synchronization circuit and the code error detection circuit are also operated by the internal clock generated by the phase locked oscillator, when the phase locked oscillator fails, the frame synchronization of the received signal is reduced. There is a problem that monitoring of a code error cannot be performed. Further, in the prior art 2, there is a problem in that when a transmission line failure and an oscillator failure overlap, a correct alarm of an input signal abnormality in the own repeater cannot be taken out from the own device.

An object of the present invention is to solve the above-mentioned problems, and to provide an intermediate repeater used in a digital backbone transmission system with a disconnection of a signal to a downstream intermediate repeater even when a received signal is disconnected. Without spreading the failure of
It is another object of the present invention to enable an instantaneous transmission line alarm to be transferred to a downstream transmission line.

[0013]

SUMMARY OF THE INVENTION In order to solve the above problems, an intermediate repeater according to the present invention receives a signal transmitted from an upstream transmission line as a reception signal, and transmits a transmission signal to a downstream transmission line. An input disconnection detection circuit for detecting an input disconnection of the received signal and outputting an input disconnection detection signal when the input disconnection of the received signal is detected; and extracting a transmission line clock from the received signal. A clock extraction circuit for synchronizing with the transmission line clock, synchronizing the received signal with a frame, outputting a frame-synchronized signal, and outputting a frame-losing signal when the frame synchronization is lost. A circuit for detecting a code error of the signal after the frame synchronization and outputting a code error detection signal when detecting a code error of the signal after the frame synchronization; A phase-locked oscillator for generating an internal clock synchronized with the transmission line clock; a signal after the frame synchronization is written in synchronization with the transmission line clock, and a signal written in synchronization with the internal clock is read out A buffer circuit for transferring the signal after frame synchronization from the transmission line clock to the internal clock by reading out the signal as a synchronized signal; and transmitting a transmission frame signal and an overhead insertion pulse in synchronization with the internal clock. A frame counter to be generated; responsive to the transmission frame signal, holding each of the transmission path alarms of the input disconnection detection signal, the frame loss of synchronization signal, and the code error detection signal for one frame of the transmission frame signal. An alarm holding circuit for outputting an alarm signal; synchronizing with the internal clock, In response to the over arm signal, and alarm transfer information generation circuit for generating alarm transfer information obtained by adding the identification ID of the relay relaying device to the alarm signal;
And an overhead insertion circuit for inserting an overhead including the alarm transfer information into the read signal in response to the overhead insertion pulse, and transmitting the transmission signal to the downstream transmission path.

[0014]

The fault contents and the intermediate repeater identification ID information are inserted into the alarm transfer information inserted into the overhead of the transmission signal.
As a result, the terminal equipment can evaluate the faulty intermediate repeater only by extracting the overhead information from the received signal and judging the content of the information bit, and the free running frequency of the phase locked oscillator of the repeater can be evaluated. There is no need to recognize

The frame synchronization circuit and the code error detection circuit for the received signal of the intermediate repeater are operated in synchronization with the received transmission line clock. A buffer circuit is provided immediately before an overhead insertion circuit that performs transmission frame generation and overhead insertion, and the buffer circuit performs switching to an internal clock generated by a phase-locked oscillator. As a result, even when a failure occurs in the phase-locked oscillator, it becomes possible to monitor the frame synchronization and the code error with respect to the received signal.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of an intermediate repeater according to an embodiment of the present invention. The illustrated intermediate relay device is a device that receives a signal transmitted from an upstream transmission line as a reception signal RS and transmits a transmission signal RR to a downstream transmission line,
An input disconnection detection circuit 11, a clock extraction circuit 12, a frame synchronization circuit 13, a code error detection circuit 14, a phase locked oscillator (PLO) 15, a buffer circuit 16, a frame counter 17, an alarm holding circuit 18, , An alarm transfer information generation circuit 19 and an overhead insertion circuit 20.

The input disconnection detection circuit 11 detects an input disconnection of the received signal RS, and outputs an input disconnection detection signal IB when the input disconnection of the received signal RS is detected. Clock extraction circuit 12
Extracts the transmission line clock PC from the received signal RS.
The frame synchronization circuit 13 synchronizes with the transmission line clock PC, synchronizes the received signal RS with the frame, outputs the frame-synchronized signal FS, and outputs the frame-out-of-frame signal FP when the frame synchronization is lost. . The code error detection circuit 14 detects a code error of the signal FS after frame synchronization, and outputs a code error detection signal CE when detecting a code error of the signal FS after frame synchronization. The phase locked oscillator 15 generates an internal clock IC synchronized with the transmission line clock PC. The buffer circuit 16 writes the signal FS after the frame synchronization in synchronization with the transmission path clock PC, and reads out the signal written in synchronization with the internal clock IC as the read signal OS, thereby obtaining the signal FS after the frame synchronization. On the other hand, the transfer from the transmission line clock PC to the internal clock IC is performed. Frame counter 1
7 generates a transmission frame TS and an overhead insertion pulse OI in synchronization with the internal clock IC. In response to the transmission frame TF, the alarm holding circuit 18 holds the transmission line alarms of the input disconnection detection signal IB, the frame out-of-synchronization signal FP, and the code error detection signal CE for one frame of the transmission frame TF. The signal AI is output. The alarm transfer information generation circuit 19 synchronizes with the internal clock IC, and generates alarm transfer information AT in which the identification ID of the relay relay device is added to the alarm signal AI in response to the transmission frame TF. In response to the overhead insertion pulse OI, the overhead insertion circuit 17 inserts the overhead including the alarm transfer information AT into the read signal OS, and sends out the transmission signal TS to the downstream transmission path.

Next, the operation of the intermediate repeater shown in FIG. 1 will be described. First, the operation when the reception signal RS is normal will be described. In this case, an internal clock IC synchronized with the transmission line clock PC extracted by the clock extraction circuit 12 is generated by the phase-locked oscillator 15, and the frame circuit-synchronized signal FS is generated by the buffer circuit 16 from the transmission line clock OC. Change to the internal clock IC. In response to the internal clock IC, the frame counsel 17 generates a transmission frame and sends the transmission signal TS to the downstream transmission path.

Next, the operation when an alarm is detected will be described. Input disconnection detection circuit 11, frame synchronization circuit 1
3, and the input is cut off by the error detection and detection circuit 14, respectively.
When frame synchronization loss and code error are detected, the alarm holding circuit 18 holds the alarm signal AI for one transmission frame.

FIG. 2 shows a partial configuration of the alarm holding circuit 18. For example, the illustrated alarm holding circuit 18 is a circuit for disconnecting the input, but the circuits for de-synchronization and the code error have the same configuration. Alarm holding circuit 1 shown
8 is a holding circuit 18-1 and a flip-flop 18-2.
, Input terminals 18-1 and 18-4, and output terminal 18
-5. The holding circuit 18-1 holds the input disconnection detection signal IB input from the input terminal 18-3 as a first alarm signal. In response to the transmission frame TF from the input terminal 18-4, the first alarm signal held in the holding circuit 18-1 is read out by the flip-flop 18-2 and the first alarm signal held in the holding circuit 18-1.
Is reset.

FIG. 3 shows that the input signal detection circuit 11
The operation when the input disconnection is detected is shown. In FIG. 3, the output of the input disconnection detection circuit 11 (input disconnection detection signal IB) is shown on the first row, the output of the frame counter 17 (transmission frame TF) is shown on the second row, and the alarm is shown on the third row. The output of the holding circuit 18 (alarm signal AI) is shown on the fourth line, the output of the alarm transfer information generation circuit 19 (alarm transfer information AT) is shown on the fourth line, and the output of the overhead insertion circuit 20 (transmission signal TS) is shown on the fifth line. ).

As shown in FIG. 3, the alarm transfer information AT can be reliably transferred to the downstream transmission line even for an instantaneous alarm of one frame period or less.

In this embodiment, the transmission signal TS
Is generated in synchronization with the internal clock IC generated by the phase locked oscillator 15, so that even if the input of the reception signal RS is interrupted, the clock and the frame transmitted to the downstream transmission line are not interrupted. For this reason, the instantaneous interruption of the received signal RS can be transferred to the downstream transmission path as shown in FIG. Further, in the present embodiment, the frame synchronization circuit 13 and the code error detection circuit 14 are configured to operate in synchronization with the received transmission line clock PC, so that even if the phase-locked oscillator 15 fails, However, it is possible to detect an alarm for the received signal RS.

[0025]

As described above, according to the present invention, since the internal clock generated by the phase-locked oscillator is used as the transmission clock to the downstream transmission line, even if the input signal to the intermediate repeater is interrupted, the downstream is used. The transmission clock to the transmission line is always output, and an instantaneous transmission line alarm can be transferred to the intermediate relay device downstream without causing a failure to propagate to the intermediate relay device downstream. Further, in the present invention, since the operation is performed by the transmission line clock until immediately before the generation of the transmission frame and the insertion of the overhead, even if the phase-locked oscillator has failed, it is possible to detect the alarm for the received signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an intermediate relay device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a part of an alarm holding circuit used in the intermediate relay device shown in FIG. 1;

FIG. 3 is a time chart for explaining an operation of the intermediate relay device shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 11 input disconnection detection circuit 12 clock extraction circuit 13 frame synchronization circuit 14 code error detection circuit 15 phase locked oscillator (PLO) 16 buffer circuit 17 frame counter 18 alarm holding circuit 19 alarm transfer information generation circuit 20 overhead insertion circuit

Claims (2)

[Claims] 1. An intermediate repeater that receives a signal transmitted from an upstream transmission path as a reception signal and transmits a transmission signal to a downstream transmission path, wherein an input disconnection of the reception signal is detected, An input disconnection detection circuit that outputs an input disconnection detection signal when an input disconnection is detected, a clock extraction circuit that extracts a transmission line clock from the reception signal, and a frame synchronization of the reception signal in synchronization with the transmission line clock A frame synchronization circuit that outputs a signal after frame synchronization and outputs a frame loss signal when frame synchronization is lost, and detects a code error of the signal after frame synchronization, and outputs a signal after the frame synchronization. A code error detection circuit that outputs a code error detection signal when detecting a code error of the signal; and a phase synchronization circuit that generates an internal clock synchronized with the transmission line clock. An oscillator, writing the signal after the frame synchronization in synchronization with the transmission line clock, and reading out the signal written in synchronization with the internal clock as a read signal; A buffer circuit that switches from a transmission line clock to the internal clock; a frame counter that generates a transmission frame signal and an overhead insertion pulse in synchronization with the internal clock; and a transmission that responds to the transmission frame signal. An alarm holding circuit for holding the input disconnection detection signal for one frame of the frame signal, the frame out-of-synchronization signal, and the transmission path alarm of the code error detection signal, and outputting an alarm signal; , In response to the transmission frame signal, the identification signal of the relay relay device in the alarm signal An alarm transfer information generating circuit that generates the added alarm transfer information; and, in response to the overhead insertion pulse, inserts an overhead including the alarm transfer information into the read signal, and transmits the transmission signal to the downstream transmission path. And an overhead insertion circuit for transmitting. 2. An alarm transfer method in an intermediate repeater for receiving a signal transmitted from an upstream transmission path as a reception signal and transmitting a transmission signal to a downstream transmission path, wherein a transmission path clock is converted from the reception signal. Extracting, synchronizing with the transmission line clock, outputting a signal after frame synchronization by synchronizing the frame of the received signal, and outputting a frame out-of-frame signal when frame synchronization is lost, Detecting a code error of the signal after the frame synchronization, outputting a code error detection signal when detecting a code error of the signal after the frame synchronization, and generating an internal clock synchronized with the transmission line clock. And writing the signal after the frame synchronization in synchronization with the transmission line clock, and writing the signal in synchronization with the internal clock. Changing the transmission line clock to the internal clock for the signal after the frame synchronization by reading as a read signal; and transmitting a transmission frame signal and an overhead insertion pulse in synchronization with the internal clock. Generating, in response to the transmission frame signal, the input disconnection detection signal for one frame of the transmission frame signal, the frame out-of-synchronization signal, and holding each transmission path alarm of the code error detection signal, Outputting an alarm signal; synchronizing with the internal clock and generating alarm transfer information in which an identification ID of the relay relay device is added to the alarm signal in response to the transmission frame signal; and In response to the pulse for use, the readout signal includes an overhead containing the alarm transfer information. Inserted, an alarm transfer method intermediate relay apparatus characterized by including the step of transmitting said transmission signal to said downstream transmission path.