JPH1065313A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH1065313A JPH1065313A JP8229426A JP22942696A JPH1065313A JP H1065313 A JPH1065313 A JP H1065313A JP 8229426 A JP8229426 A JP 8229426A JP 22942696 A JP22942696 A JP 22942696A JP H1065313 A JPH1065313 A JP H1065313A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- groove
- insulating layer
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明はプリント配線板に
関し、より詳細には回路の実装密度をより高めることを
目的とした両面及び多層プリント配線板の創作に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly, to the creation of a double-sided or multilayer printed wiring board for the purpose of increasing the circuit mounting density.
【０００２】[0002]
【従来の技術】この発明に間接的に関連する従来技術と
しては、絶縁層の表裏又は層間の回路を接続するにあた
り、貫通穴の壁面に金属をめっきしたスルーホールが存
するが、本願発明者の知得する限りにおいてはこの発明
の直接的な従来技術は存しない。2. Description of the Related Art As a prior art which is indirectly related to the present invention, there is a through hole formed by plating a metal on a wall surface of a through hole when connecting a circuit between front and back surfaces of an insulating layer or between layers. As far as we know, there is no direct prior art of this invention.
【０００３】[0003]
【発明が解決しようとする課題】この発明の目的は両面
及び多層プリント配線板の回路の実装密度をより高める
点にあるが、その前提として従来技術における以下の具
体的な問題点が挙げられる。SUMMARY OF THE INVENTION An object of the present invention is to increase the mounting density of circuits on double-sided and multilayer printed wiring boards. The premise of this is the following specific problems in the prior art.
【０００４】図１６に示すように、例えばアンテナ回
路のように絶縁層１００の両面の回路１１１及び１１２
が同一の回路において、信号の位相差を減少させるため
に、両面の回路をスルーホール１１３で接続している
が、信号がスルーホールを経由する時点で若干の位相差
が発生し、回路に悪影響を与えていた。As shown in FIG. 16, circuits 111 and 112 on both sides of an insulating layer 100, such as an antenna circuit, are provided.
However, in the same circuit, the circuits on both sides are connected by through holes 113 in order to reduce the phase difference of the signal, but a slight phase difference occurs when the signal passes through the through hole, adversely affecting the circuit. Had been given.
【０００５】図１７に示すように、例えば信号回路１
２５において、クロックライン等へのノイズ混入防止及
び他へのノイズの影響防止のため、信号回路１２５の両
側に一対のダミー回路１２１Ａ、１２１Ｂを配してシー
ルドを行っているが、あくまでも平面方向へのシールド
効果しか得られない。又、Ｚ軸方向（絶縁層の厚み方
向）には配線板表面をグランドプレーンにする設計手法
か、導電性物質で表面を被膜する方法があるが、完全で
はなかった。[0005] As shown in FIG.
In FIG. 25, a pair of dummy circuits 121A and 121B are disposed on both sides of the signal circuit 125 to shield noise in order to prevent noise from entering a clock line or the like and to prevent influence of noise on others. Only the shielding effect of is obtained. Further, in the Z-axis direction (the thickness direction of the insulating layer), there is a design method of making the surface of the wiring board a ground plane, or a method of coating the surface with a conductive substance, but it is not perfect.
【０００６】図１８及び図１９に示すように、大電流
を必要とする回路１３１に関しては、通常の回路１３２
に比し回路の巾を太くするか（図１８の状態）、回路を
構成する銅箔を厚くして（図１９の状態）対応してい
る。しかしながら、前者は回路の巾が太くなる分の回路
の実装密度が低下し、後者はプリント配線板の製法上、
必要な箇所の銅箔のみを厚くすることは不可能なことよ
り、必要としない回路の銅箔も厚くなり、やはり回路の
実装密度が低下する問題を生じた。As shown in FIG. 18 and FIG. 19, a circuit 131 requiring a large current
In this case, the width of the circuit is made larger than that of FIG. 18 (the state of FIG. 18), or the copper foil constituting the circuit is made thicker (the state of FIG. 19). However, in the former, the mounting density of the circuit is reduced due to the increase in the width of the circuit.
Since it is impossible to increase the thickness of only the required portion of the copper foil, the thickness of the unnecessary portion of the copper foil of the circuit is also increased.
【０００７】図２０に示すように、熱発生のある回路
１４１及びその近辺の回路では放熱効果を高めるため
に、通常の回路１４２に比しやはり回路の巾を太くして
面積を増大させているが、効果が不十分の上、回路の実
装密度が低下する問題を生じた。As shown in FIG. 20, in the circuit 141 which generates heat and the circuits in the vicinity thereof, the width of the circuit is increased and the area is increased as compared with the ordinary circuit 142 in order to enhance the heat radiation effect. However, there has been a problem that the effect is insufficient and the mounting density of the circuit is reduced.
【０００８】[0008]
【課題を解決するための手段】この発明は以上の問題点
に鑑みて創作されたものであり、絶縁層に溝を設けると
共に、この溝の壁面に金属をめっきすることにより、回
路を形成することを特徴とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a groove formed in an insulating layer and a metal formed on a wall surface of the groove to form a circuit. It is characterized by the following.
【０００９】よって、この発明によれば溝の壁面に金属
をめっきすることにより、回路が形成されるので、プリ
ント配線板において従来絶縁層の表裏のみに存した回路
を、絶縁層の内部にも配することが可能となる作用を生
じることとなる。従来、スルーホールのように貫通穴の
壁面に金属をめっきして層間接続をする技術は存した
が、これはあくまでも絶縁層のＺ方向（厚み方向）をス
ポット的に回路が貫通するに過ぎず、この発明は絶縁層
の内部のＸＹ方向（平面方向）にも回路が連続的に貫通
する点において区別される。一方、この発明においては
溝を貫通溝とすることにより、スルーホールのように層
間接続を行う作用も生じるが、この場合には上記したよ
うに回路は絶縁層の内部のＸＹ方向（平面方向）にも延
びているのだから、結果的に回路は絶縁層の表裏を貫通
して形成され、内外層の回路が一体化することとなる。Therefore, according to the present invention, a circuit is formed by plating a metal on the wall surface of the groove, so that a circuit which has conventionally existed only on the front and back of the insulating layer in the printed wiring board can also be formed inside the insulating layer. The effect that can be arranged is produced. Conventionally, there has been a technique of plating a metal on a wall surface of a through-hole like a through-hole to perform interlayer connection. However, this is merely a case where a circuit penetrates the insulating layer in a spot direction in the Z direction (thickness direction). The present invention is distinguished in that the circuit continuously penetrates also in the XY directions (plane direction) inside the insulating layer. On the other hand, in the present invention, by forming the groove as a through groove, an effect of making an interlayer connection like a through hole also occurs. In this case, however, as described above, the circuit is formed in the XY directions (plane direction) inside the insulating layer. As a result, the circuit is formed penetrating the front and back of the insulating layer, and the circuits of the inner and outer layers are integrated.
【００１０】又、溝は、それをレーザー加工により施せ
ば、極めて微細な巾のものを実現することが可能とな
り、巾の細さによっては溝の壁面に金属をめっきするこ
とによりめっき層の厚みで溝が埋められ、めっき後は存
在しなくなる作用も生じる。[0010] Further, if the groove is formed by laser processing, it is possible to realize a groove having an extremely fine width. The groove is filled with the metal, and there is an effect that the groove does not exist after plating.
【００１１】[0011]
【発明の実施の形態】図９乃至１５は、この発明のプリ
ント配線板の製造方法の具体例を示す図である。尚、こ
の製造方法はあくまでも一例であり、アディティブ法、
ビルドアップ法等、スルーホールめっき配線板に関する
公知の製造方法の応用によりこの発明のプリント配線板
を製造できることはいうまでもない。9 to 15 are views showing a specific example of a method for manufacturing a printed wiring board according to the present invention. This manufacturing method is merely an example, and the additive method,
It goes without saying that the printed wiring board of the present invention can be manufactured by applying a known manufacturing method for a through-hole plated wiring board such as a build-up method.
【００１２】表裏に銅箔２Ａ、２Ｂを積層した絶縁層
（樹脂）１に、施すべき溝以外の部分を被膜するように
エッチングレジスト被膜３Ａ、３Ｂを施す（図９参
照）。Etching resist coatings 3A and 3B are applied to the insulating layer (resin) 1 in which the copper foils 2A and 2B are laminated on the front and back so as to cover portions other than the grooves to be applied (see FIG. 9).
【００１３】エッチングにより、施すべき溝に沿って
絶縁層１が露出するように銅箔２Ａ、２Ｂを除去する
（図１０参照）。The copper foils 2A and 2B are removed by etching so that the insulating layer 1 is exposed along the grooves to be formed (see FIG. 10).
【００１４】露出した絶縁層１に対し、レーザ加工に
より溝４を掘削する（図１１参照）。A groove 4 is excavated in the exposed insulating layer 1 by laser processing (see FIG. 11).
【００１５】溝４の壁面に無電解銅めっき５を施し、
上下の銅箔２Ａ、２Ｂと接続する（図１２参照）。Electroless copper plating 5 is applied to the wall surface of the groove 4,
It is connected to upper and lower copper foils 2A and 2B (see FIG. 12).
【００１６】上下の銅箔２Ａ、２Ｂの所定の回路Ｃを
被膜するように、エッチングレジスト被膜３Ａ、３Ｂを
施す（図１３参照）。Etching resist films 3A and 3B are applied so as to cover predetermined circuits C of the upper and lower copper foils 2A and 2B (see FIG. 13).
【００１７】エッチングにより、回路Ｃ以外の銅箔２
Ａ、２Ｂを除去する（図１４参照）。By etching, copper foil 2 other than circuit C
A and 2B are removed (see FIG. 14).
【００１８】上記工程を必要層数に応じ繰り返すと共
に、プリプレグ６を介して層間の接着を行う（図１５参
照）。The above steps are repeated according to the required number of layers, and at the same time, interlayer bonding is performed via the prepreg 6 (see FIG. 15).
【００１９】[0019]
【実施例】次に、この発明のプリント配線板の具体的実
施例を添付図面に基づいて説明する。図１及び２は、前
記した発明が解決しようとする課題の欄のの問題点を
解消するための実施例を示す図である。この実施例は、
例えばアンテナ回路のように絶縁層１の両面の回路１１
及び１２が同一の回路において、信号の位相差を減少さ
せるために層間の回路を接続するものであり、接続対象
の回路１１、１２に沿ってレーザ加工により絶縁層１に
貫通溝１０を掘削し、この貫通溝１０の壁面に金属１３
をめっきすることにより回路同士を一体に接続してい
る。尚、図１においては貫通溝１０はめっきした金属１
３により完全に埋められているように図示されている
が、これは前記したようにレーザー加工により極めて微
細な巾の溝としたことにより、溝の壁面にめっきにより
施した金属の厚みで溝が埋められたことによる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a specific embodiment of the printed wiring board of the present invention will be described with reference to the accompanying drawings. FIGS. 1 and 2 show an embodiment for solving the problems in the column of the problem to be solved by the invention. This example is
For example, a circuit 11 on both sides of the insulating layer 1 such as an antenna circuit
And 12 connect the circuits between layers in order to reduce the phase difference of signals in the same circuit, and excavate the through groove 10 in the insulating layer 1 by laser processing along the circuits 11 and 12 to be connected. The metal 13 is provided on the wall of the through groove 10.
The circuits are integrally connected by plating. In FIG. 1, the through groove 10 is formed of a plated metal 1.
Although it is illustrated as completely buried by 3, this is a groove having an extremely fine width formed by laser processing as described above, so that the groove is formed by the thickness of the metal plated on the wall surface of the groove. Due to being buried.
【００２０】図３及び４は、前記した発明が解決しよう
とする課題の欄のの問題点を解消するための実施例を
示す図である。この実施例においては、例えば信号回路
２５において、クロックライン等へのノイズ混入防止及
び他へのノイズの影響防止のためのダミー回路にこの発
明を実施している。図中符号２１Ａ、２１Ｂは信号回路
２５の両側に配されるダミー回路であり、ここまでは従
来技術と同様であるが、この実施例においては、更にこ
のダミー回路に沿ってレーザ加工により絶縁層１に一対
の貫通溝２０Ａ、２０Ｂを掘削すると共に、絶縁層１の
他面にはこの一対の貫通溝間を結ぶダミー回路２３を配
し、貫通溝２０Ａ、２０Ｂの壁面に金属をめっきするこ
とにより各ダミー回路を接続している。よって、この実
施例によればダミー回路は、恰も信号回路２５を囲むト
ンネル状に形成されることとなり、万全のシールド効果
が実現されることとなる。FIGS. 3 and 4 show an embodiment for solving the problems in the column of the problem to be solved by the invention. In this embodiment, for example, in the signal circuit 25, the present invention is applied to a dummy circuit for preventing noise from entering a clock line and the like and preventing the influence of noise on other components. In the figure, reference numerals 21A and 21B denote dummy circuits arranged on both sides of the signal circuit 25, which are the same as those in the prior art. However, in this embodiment, the insulating layers are further processed by laser processing along the dummy circuits. 1, a pair of through-grooves 20A, 20B are excavated, and a dummy circuit 23 connecting the pair of through-grooves is arranged on the other surface of the insulating layer 1, and metal is plated on the wall surfaces of the through-grooves 20A, 20B. Connect the respective dummy circuits. Therefore, according to this embodiment, the dummy circuit is formed in a tunnel shape surrounding the signal circuit 25, and a perfect shielding effect is realized.
【００２１】図５及び６は、前記した発明が解決しよう
とする課題の欄のの問題点を解消するための実施例を
示す図である。この実施例は、大電流を必要とする回路
３２の断面積を増大させるためのものであり、回路３２
に沿ってレーザ加工により絶縁層１に貫通溝３０を掘削
すると共に、絶縁層の他面にこの貫通溝３０に沿って回
路３３、３３を配し、貫通溝３０の壁面に金属３１をめ
っきすることにより回路同士を一体に接続して、結果的
に要求される回路の断面積を増大させている。FIGS. 5 and 6 show an embodiment for solving the problems in the column of the problem to be solved by the invention. This embodiment is for increasing the cross-sectional area of the circuit 32 requiring a large current.
In addition to excavating the through-groove 30 in the insulating layer 1 by laser processing along, the circuits 33 and 33 are arranged along the through-groove 30 on the other surface of the insulating layer, and the metal 31 is plated on the wall surface of the through-groove 30. As a result, the circuits are integrally connected, and as a result, the required cross-sectional area of the circuit is increased.
【００２２】図７及び８は、前記した発明が解決しよう
とする課題の欄のの問題点を解消するための実施例を
示す図である。この実施例は、熱発生のある回路４２の
放熱効果を高めるために、回路の面積を増大させるため
のものであり、回路４２に沿ってレーザ加工により絶縁
層１に溝４１Ａ、４１Ｂを掘削すると共に、この溝４１
Ａ、４１Ｂの壁面に金属４３Ａ、４３Ｂをめっきするこ
とにより、要求される回路の面積を貫通溝の壁面に振り
分け、結果的に要求される回路の面積を増大させてい
る。尚、この実施例において溝は２本図示したが、溝は
それ以上の本数でも、又１本であってもよいことは勿論
である。FIGS. 7 and 8 are views showing an embodiment for solving the problems in the column of the problem to be solved by the invention. This embodiment is for increasing the area of the circuit 42 in order to enhance the heat radiation effect of the circuit 42 that generates heat, and excavates the grooves 41A and 41B in the insulating layer 1 by laser processing along the circuit 42. Together with this groove 41
By plating metals 43A and 43B on the wall surfaces of A and 41B, the required circuit area is distributed to the wall surfaces of the through-grooves, and as a result, the required circuit area is increased. Although two grooves are shown in this embodiment, it goes without saying that the number of grooves may be more than one or one.
【００２３】[0023]
【発明の効果】以上の構成よりなるこの発明によれば、
従来、Ｚ方向（厚み方向）にスポット的に回路が貫通す
るに過ぎなかった絶縁層の内部を、回路を構築するため
の空間として活用できると共に、この回路を絶縁層の表
裏の回路と一体化することにより回路の充分な面積或い
は断面積を確保することができ、その結果、表裏に表れ
る回路の巾を狭くすることが可能となり、プリント配線
板の回路の実装密度の飛躍的な向上が図られる。According to the present invention having the above configuration,
Conventionally, the inside of the insulating layer, which merely penetrated the circuit in a spot direction in the Z direction (thickness direction), can be used as a space for constructing the circuit, and this circuit is integrated with the circuit on the front and back of the insulating layer. By doing so, it is possible to secure a sufficient area or cross-sectional area of the circuit, and as a result, it is possible to reduce the width of the circuit appearing on the front and back sides, thereby dramatically improving the mounting density of the circuit on the printed wiring board. Can be
【００２４】又、上記の効果は絶縁層に溝を設けると共
に、この溝の壁面に金属をめっきするという簡易な作業
により実現されるので、実装密度の高いプリント配線板
を低いコストで実現することが可能となる。Further, the above effect can be realized by a simple operation of providing a groove in the insulating layer and plating a metal on the wall surface of the groove, so that a printed wiring board having a high mounting density can be realized at low cost. Becomes possible.
【図１】この発明のプリント配線板の実施例の要部の一
部切り欠き斜視図。FIG. 1 is a partially cutaway perspective view of a main part of an embodiment of a printed wiring board of the present invention.
【図２】同上、溝の状態を示す要部の一部切り欠き斜視
図。FIG. 2 is a partially cutaway perspective view of a main part showing the state of the groove.
【図３】同上、異なる実施例の要部の一部切り欠き斜視
図。FIG. 3 is a partially cutaway perspective view of a main part of another embodiment.
【図４】同上、溝の状態を示す要部の一部切り欠き斜視
図。FIG. 4 is a partially cutaway perspective view of a main part showing a state of the groove.
【図５】同上、異なる実施例の要部の一部切り欠き斜視
図。FIG. 5 is a partially cutaway perspective view of a main part of another embodiment.
【図６】同上、溝の状態を示す要部の一部切り欠き斜視
図。FIG. 6 is a partially cutaway perspective view of a main part showing the state of the groove.
【図７】同上、異なる実施例の要部の一部切り欠き斜視
図。FIG. 7 is a partially cutaway perspective view of a main part of another embodiment.
【図８】同上、溝の状態を示す要部の一部切り欠き斜視
図。FIG. 8 is a partially cutaway perspective view of a main part showing the state of the groove.
【図９】この発明のプリント配線板の製造方法の一例の
工程を示す断面図。FIG. 9 is a sectional view showing a step of an example of the method of manufacturing a printed wiring board according to the present invention.
【図１０】この発明のプリント配線板の製造方法の一例
の工程を示す断面図。FIG. 10 is a sectional view showing a step of an example of the method for manufacturing a printed wiring board according to the present invention;
【図１１】この発明のプリント配線板の製造方法の一例
の工程を示す断面図。FIG. 11 is a sectional view showing a step of an example of the method of manufacturing a printed wiring board according to the present invention.
【図１２】この発明のプリント配線板の製造方法の一例
の工程を示す断面図。FIG. 12 is a sectional view showing a step of an example of the method of manufacturing a printed wiring board according to the present invention.
【図１３】この発明のプリント配線板の製造方法の一例
の工程を示す断面図。FIG. 13 is a sectional view showing a step of an example of the method for manufacturing a printed wiring board according to the present invention.
【図１４】この発明のプリント配線板の製造方法の一例
の工程を示す断面図。FIG. 14 is a sectional view showing a step of an example of the method for manufacturing a printed wiring board according to the present invention;
【図１５】この発明のプリント配線板の製造方法の一例
の工程を示す断面図。FIG. 15 is a sectional view showing a step of an example of the method for manufacturing a printed wiring board according to the present invention;
【図１６】従来技術のプリント配線板の要部の斜視図。FIG. 16 is a perspective view of a main part of a conventional printed wiring board.
【図１７】従来技術のプリント配線板の要部の斜視図。FIG. 17 is a perspective view of a main part of a conventional printed wiring board.
【図１８】従来技術のプリント配線板の要部の斜視図。FIG. 18 is a perspective view of a main part of a conventional printed wiring board.
【図１９】従来技術のプリント配線板の要部の斜視図。FIG. 19 is a perspective view of a main part of a conventional printed wiring board.
【図２０】従来技術のプリント配線板の要部の斜視図。FIG. 20 is a perspective view of a main part of a conventional printed wiring board.
１ 絶縁層 １０ 溝 １１ 回路 １２ 回路 １３ （めっきされた）金属 REFERENCE SIGNS LIST 1 insulating layer 10 groove 11 circuit 12 circuit 13 (plated) metal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 9/00 Ｈ０５Ｋ 9/00 Ｒ // Ｈ０５Ｋ 1/02 1/02 Ｐ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical display location H05K 9/00 H05K 9/00 R // H05K 1/02 1/02 P
Claims (8)
面に金属をめっきすることにより回路を形成することを
特徴とするプリント配線板。1. A printed wiring board, wherein a groove is formed in an insulating layer, and a circuit is formed by plating a metal on a wall surface of the groove.
リント配線板。2. The printed wiring board according to claim 1, wherein the groove penetrates the insulating layer.
プリント配線板。3. The printed wiring board according to claim 1, wherein the groove does not penetrate the insulating layer.
る請求項１から３の何れかに記載のプリント配線板。4. The printed wiring board according to claim 1, wherein the groove is provided in the insulating layer by laser processing.
象の回路に沿ってレーザ加工により掘削した貫通溝を絶
縁層に配し、この貫通溝の壁面に金属をめっきすること
により回路同士を一体に接続したことを特徴とするプリ
ント配線板。5. When connecting circuits between layers, a through-groove excavated by laser processing is arranged on an insulating layer along a circuit to be connected, and a metal is plated on a wall surface of the through-groove to integrate the circuits. A printed wiring board characterized by being connected to a printed circuit board.
ための一対のダミー回路を配し、このダミー回路に沿っ
てレーザ加工により掘削した一対の貫通溝を絶縁層に配
すると共に、絶縁層の他面にはこの一対の貫通溝間を結
ぶダミー回路を配し、貫通溝の壁面に金属をめっきする
ことにより各ダミー回路を接続して、シールド対象の回
路を囲むトンネル状のダミー回路を形成したことを特徴
とするプリント配線板。6. A pair of dummy circuits for shielding are arranged on both sides of a circuit to be shielded, and a pair of through grooves excavated by laser processing along the dummy circuit are arranged in the insulating layer. On the other surface, a dummy circuit connecting the pair of through grooves is arranged, and each dummy circuit is connected by plating metal on the wall surface of the through groove to form a tunnel-shaped dummy circuit surrounding the circuit to be shielded. A printed wiring board characterized by the following.
るにあたり、回路に沿ってレーザ加工により掘削した貫
通溝を絶縁層に配すると共に、絶縁層の他面にはこの貫
通溝に沿って回路を配し、この貫通溝の壁面に金属をめ
っきすることにより回路同士を一体に接続して、要求さ
れる回路の断面積を増大させたこと特徴とするプリント
配線板。7. In forming a circuit requiring a predetermined cross-sectional area, a through-groove excavated by laser processing along the circuit is provided on the insulating layer, and the other surface of the insulating layer is formed along the through-groove. A printed wiring board characterized by increasing the required cross-sectional area of a circuit by disposing the circuit and plating the metal on the wall surface of the through groove to connect the circuits integrally.
にあたり、回路に沿ってレーザ加工により掘削した溝を
絶縁層に配すると共に、この溝の壁面に金属をめっきす
ることにより、要求される回路の面積を貫通溝の壁面に
振り分けたことを特徴とするプリント配線板。8. In forming a circuit requiring a predetermined area, a groove excavated by laser processing along the circuit is arranged on an insulating layer, and a metal is plated on a wall surface of the groove. A printed wiring board characterized in that the area of the circuit is distributed to the wall surface of the through groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8229426A JPH1065313A (en) | 1996-08-13 | 1996-08-13 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8229426A JPH1065313A (en) | 1996-08-13 | 1996-08-13 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1065313A true JPH1065313A (en) | 1998-03-06 |
Family
ID=16892049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8229426A Pending JPH1065313A (en) | 1996-08-13 | 1996-08-13 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1065313A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004228113A (en) * | 2003-01-20 | 2004-08-12 | Rion Co Ltd | Insulating structure using printed board |
| JP2009277863A (en) * | 2008-05-14 | 2009-11-26 | Toyota Industries Corp | Method of manufacturing wiring substrate |
| WO2010023865A1 (en) * | 2008-08-29 | 2010-03-04 | 住友ベークライト株式会社 | Printed wiring board and method of manufacturing printed wiring board |
| JP2016127251A (en) * | 2014-12-26 | 2016-07-11 | 京セラ株式会社 | Printed-circuit board and method for manufacturing the same |
| JP2017162895A (en) * | 2016-03-08 | 2017-09-14 | 株式会社ジェイデバイス | Wiring structure, printed board, semiconductor device, and method of manufacturing wiring structure |
| CN111356283A (en) * | 2020-04-09 | 2020-06-30 | Oppo广东移动通信有限公司 | Circuit board and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62131593A (en) * | 1985-12-03 | 1987-06-13 | 株式会社東海理化電機製作所 | Formation of resin molded electric circuit |
| JPH0272692A (en) * | 1988-09-07 | 1990-03-12 | Hitachi Ltd | Wiring board and forming method thereof |
| JPH07240568A (en) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | Circuit board and its manufacture |
| JPH08111588A (en) * | 1994-10-12 | 1996-04-30 | Oki Electric Ind Co Ltd | Thin film multilayer board and manufacture thereof |
-
1996
- 1996-08-13 JP JP8229426A patent/JPH1065313A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62131593A (en) * | 1985-12-03 | 1987-06-13 | 株式会社東海理化電機製作所 | Formation of resin molded electric circuit |
| JPH0272692A (en) * | 1988-09-07 | 1990-03-12 | Hitachi Ltd | Wiring board and forming method thereof |
| JPH07240568A (en) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | Circuit board and its manufacture |
| JPH08111588A (en) * | 1994-10-12 | 1996-04-30 | Oki Electric Ind Co Ltd | Thin film multilayer board and manufacture thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004228113A (en) * | 2003-01-20 | 2004-08-12 | Rion Co Ltd | Insulating structure using printed board |
| JP2009277863A (en) * | 2008-05-14 | 2009-11-26 | Toyota Industries Corp | Method of manufacturing wiring substrate |
| WO2010023865A1 (en) * | 2008-08-29 | 2010-03-04 | 住友ベークライト株式会社 | Printed wiring board and method of manufacturing printed wiring board |
| JP2016127251A (en) * | 2014-12-26 | 2016-07-11 | 京セラ株式会社 | Printed-circuit board and method for manufacturing the same |
| JP2017162895A (en) * | 2016-03-08 | 2017-09-14 | 株式会社ジェイデバイス | Wiring structure, printed board, semiconductor device, and method of manufacturing wiring structure |
| CN107172828A (en) * | 2016-03-08 | 2017-09-15 | 株式会社吉帝伟士 | Wire structures, printed base plate, the manufacture method of semiconductor device and wire structures |
| CN111356283A (en) * | 2020-04-09 | 2020-06-30 | Oppo广东移动通信有限公司 | Circuit board and electronic equipment |
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