JPH1065107A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set the optimum resistance value for each wafer by a method, wherein a bias resistor with which the change of the saturated drain current of a J-FET is suppressed with respect to the change in the ambient temperature, and the optimum resistance value of the bias resistor is estimated in the manufacturing process of a chip. SOLUTION: A J-FET element and a polysilicon film resistance element are formed on a semiconductor substrate. The resistance value of a polysilicon film resistor 20a is controlled by the implanting amount of impurities into a polysilicon film. The punch-through voltage of a gate diffusion layer and a P<+> -type silicon substrate 1 is measured after the formation of a gate diffusion layer 10-1, a saturated drain current is estimated, and the implanting amount of impurities to the polysilicon film is controlled in accordance with the estimation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a junction type field effect transistor (hereinafter referred to as a "junction type field effect transistor").
J-FET) and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device having a J-FET and a method of manufacturing the same will be described in the order of steps (FIGS. 7 and 8).
A description will be given with reference to FIG.

First, as shown in FIG. 7A, a silicon oxide film 3 is formed by thermally oxidizing the surface of a semiconductor substrate obtained by epitaxially growing an N-type semiconductor layer 2 on a P ⁺ type silicon substrate 1 (FIG. 9). Step 100). FIG. 7 shows a known photolithography (hereinafter referred to as PR) technique.
As shown in FIG. 2B, an opening 4 is formed by etching the silicon oxide film 3 to form a P ⁺ -type element isolation region 5,
In a boron atmosphere, boron as an impurity is diffused until it reaches the P ⁺ type silicon substrate 1 sufficiently (step 10).
1).

Next, the entire surface of the wafer is thermally oxidized, as shown in FIG.
As shown in (c), the silicon oxide film 7 is grown,
Openings 8-1 and 8-2 are formed in the FET formation region and the check element formation region by the PR technique, respectively, and boron implanted layers 9-1 and 9-2 are formed by ion implantation (step 102) and diffused under high temperature. Then, as shown in FIG. 7D, P ⁺ type diffusion layers 10-1 and 10-2 are formed.
At this time, an oxide film 11 is formed in the opening.
03). Next, after thinning or removing the oxide film 11, FIG.
As shown in (a), P ⁺ to type diffusion layer 10 by pressing a needle-like electrode 12-1, the P ⁺ -type diffusion layer 10 negative voltage to the P ⁺ -type silicon substrate 1 to Ev Apply. Ev
Increases when the depletion layer extends from the P ⁺ -type diffusion layer 10-2 and reaches the P ⁺ -type silicon substrate. The voltage at this time (punch through voltage V _PT ) is measured (step 104).

[0005] This V _PT has a correlation with the saturated drain current I _DSS of the completed J-FET. FIG. 10 is a graph showing the relationship between V _PT and I _DSS obtained experimentally. I _DSS is predicted from this graph (step 105). When the predicted value of the I _DSS is larger than the design value, by adding the heat treatment is performed to push diffusion of P ⁺ -type diffusion layer 101, 102 (step 106,103). Step until the predicted value of I _DSS coincide with a tolerance from the design value 104,10
5, 106, 103 and 104 are repeated. Next, FIG.
As shown in (b), openings 13-1 and 13-2 are formed on both sides of the P ⁺ -type diffusion layer 10-1, phosphorus is implanted, and annealing is performed to form the N ^{+ -type} diffusion layers 14-1 and 14-. 2 is formed (step 107). Next, as shown in FIG.
A silicon nitride film 16 is formed, and contact holes 17-1 and 17-1 are formed.
17-2, and aluminum-based wirings 18-1, 18
-2 is formed, and the surface protective film 19 is formed (Step 1).
08).

[0006] I _DSS of J-FET is dependent on the gate voltage V _GS and the ambient temperature T _a, the temperature change of I _DSS is the gate bias voltage V _Q is present becomes 0 (for example, "NE
C Data Book ", December 1995, pp. 798-799). This V _Q differs for each J-FET. FIG. 11 shows the characteristics of the two J-FETs.

As shown in FIG. 12, by externally connecting a bias resistor R _S to the source terminal S of the J-FET 30, it is possible to compensate for the temperature change of I _DSS .

In a region where _IDS increases due to a change in ambient temperature when no bias resistor is provided, the bias resistor R _S
Upon insertion of the voltage drop across the bias resistor R _S is increased, the gate electrode when a constant gate voltage V _G for ground - acting in the direction in which the voltage between the source electrode reduces the I _DSS reduced. Conversely, in a region where the _IDS decreases due to a change in the ambient temperature, the voltage between the gate electrode and the source electrode decreases due to a decrease in the voltage drop of the bias resistor, and thus the _IDS increases. Therefore, if the bias resistance R _{S is set} to an appropriate value, I.sub.
_DSS can be stabilized. This optimum resistance value R _S
As shown in FIG. 11, is given by R _S = V _Q / I _DS by the drain current I _DS when the above-mentioned V _Q is given.

[0009]

As described above, J-
The temperature change of the saturation drain current I _DSS of the FET can be mitigated by inserting a bias resistor R _S into the source. However, it I _DSS and V _Q and the like are different for every single even cultivar (type name) and the same type of J-FET, and measuring these values for J-FET each R _S
Since it is practically impossible to find the optimal value of,
In reality, the user has to determine the bias resistance R _S based on a characteristic curve representative of the product type.
That is, it is difficult to sufficiently compensate for the temperature change of the saturation drain current _IDSS even if the bias resistor _RS is used.

An object of the present invention is to provide a semiconductor device having a J-FET in which a change in temperature of a saturation drain current _IDSS is compensated by incorporating a bias resistor, and a method of manufacturing the same.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A junction field-effect transistor formed on a semiconductor substrate; and a resistance element having one end connected to a source region of the junction field-effect transistor, wherein the resistance element is a saturated drain current of the junction field-effect transistor. This is a bias resistor for compensating for the temperature change.

In this case, the first conductivity type diffusion layer formed on the second conductivity type semiconductor layer of the semiconductor substrate obtained by depositing the second conductivity type semiconductor layer on the first conductivity type semiconductor substrate is used as a gate region, A junction field-effect transistor having a source electrode and a drain electrode in contact with the second conductivity type semiconductor layer with a region therebetween, and a film resistance selectively covering an insulating film covering the second conductivity type semiconductor layer And a resistance element having a body.

According to the method of manufacturing a semiconductor device of the present invention, a first conductive type semiconductor substrate is formed from a surface of the second conductive type semiconductor layer of a semiconductor substrate obtained by depositing a second conductive type semiconductor layer on a first conductive type semiconductor substrate. Forming an element isolation region reaching the gate electrode and defining a FET formation region and a check element formation region; and a gate region comprising a first conductivity type diffusion layer in a second conductivity type semiconductor layer of the FET formation region and the check element formation region. And applying a voltage to the first conductive type semiconductor substrate and a gate region of the check element formation region to measure a punch-through voltage at which a depletion layer extending from the gate region reaches the first conductive type semiconductor substrate. Forming a resistance element having a resistance value according to the punch-through voltage,
Connecting to the second conductivity type semiconductor layer in the formation region, wherein the resistance element has a channel between the gate region of the FET formation region and the first conductivity type semiconductor substrate, using the second conductivity type semiconductor layer portion as a channel. This is a bias resistor for compensating a temperature change of the saturation drain current of the field effect transistor.

In this case, a resistive element can be formed by depositing a polycrystalline silicon film covering the insulating film, doping impurities according to the punch-through voltage, and patterning.

Since the bias resistance is formed corresponding to the saturated drain current predicted by the punch-through voltage determined by the relative relationship between the thickness of the second conductivity type semiconductor layer and the first conductivity type diffusion layer, the bias resistance value is appropriate. It can be.

[0016]

FIG. 1A is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX of FIG. 1A. is there.

The semiconductor device of the present embodiment has a polysilicon film resistor 20a for covering the silicon oxide film 7 on the surface of the semiconductor substrate and an aluminum-based wiring 18 connected thereto.
-1A and a bonding pad 22-1.

A semiconductor substrate having a 3 μm-thick silicon epitaxial layer (N-type semiconductor layer 2) formed on a P ⁺ -type silicon substrate 1, and a P ⁺ -type element isolation region is provided on the surface of the N-type semiconductor layer 2. 5A is provided to reach the P ⁺ type silicon substrate 1. Island-shaped N-type silicon epitaxial layer 2 (FET formation region) surrounded by P ⁺ -type element isolation region 5
A source region (N ⁺ type diffusion layer 14-
1) and a drain region (N ⁺ -type diffusion layer 14-2) are provided in a rectangular shape, and a P ⁺ -type gate region (P ⁺ -type diffusion layer 10-1) having a width of 2 μm and a depth of 2 μm is formed therebetween. I have. The P ⁺ -type gate region (10-1) is connected at both ends to the P ⁺ -type element isolation region 5A, and is taken out from the back electrode 23 formed on the back surface of the P ⁺ -type silicon substrate 1.
A silicon oxide film 7 having a thickness of 1 μm is formed on a main surface of a semiconductor substrate, and a source region (14-1) and a drain region (1
4-2) Contact holes 17-1 and 17 respectively reaching
-2 silicon nitride film 1 with a thickness of 100 nm over the side surface
6 are formed. Aluminum-based wiring 18-1A (connected to source region 14-1) is formed on silicon nitride film 16. Similarly, an aluminum-based wiring 18-2 is formed on the silicon nitride film 16, and is ohmically connected to the drain bonding pad 22-2 and the drain region (14-2) via the contact hole 17-2.
A polysilicon film resistor 20a is provided on a region outside the island-shaped N-type silicon epitaxial layer 2 (FET formation region). The polysilicon film resistor 20a is formed of a 400-nm-thick polysilicon film in which the amount of implantation of phosphorus or boron is controlled in order to set an optimum resistance value.
2, 21-2, the source bonding pad 22-
1 and the source electrode (18-1A).

Next, the manufacturing method of this embodiment will be described.
The process will be described with reference to sectional views (FIGS. 3 and 4) and a flowchart (FIG. 2).

First, as shown in FIG. 3A, the surface of a semiconductor substrate obtained by epitaxially growing an N-type semiconductor layer 2 on a P ⁺ type silicon substrate 1 is thermally oxidized to form silicon oxide 3 (step in FIG. 2). 100). FIG. 3B shows a known photolithography (hereinafter referred to as PR) technique.
As shown in FIG. 5, the opening 4A is formed by etching the silicon oxide film 3 for forming the P ⁺ -type element isolation region 5A.
In a boron atmosphere, boron as an impurity is diffused until it reaches the P ⁺ type silicon substrate 1 sufficiently (step 10).
1). At this time, an oxide film 6A is formed in the opening 4A.

Next, the entire surface of the wafer is thermally oxidized, as shown in FIG.
As shown in (c), the silicon oxide film 7 is grown,
Openings 8-1 and 8-2 are formed in the FET formation region and the check element formation region by the PR technique, respectively, and boron implanted layers 9-1 and 9-2 are formed by ion implantation (step 102) and diffused under high temperature. Then, as shown in FIG. 3D, P ⁺ type diffusion layers 10-1 and 10-2 are formed.
At this time, an oxide film 11 is formed in the opening.
03). Next, after thinning or removing the oxide film 11, FIG.
(A), the by pressing an electrode 12-1 of the needle to the P ⁺ -type diffusion layer 10, the P ⁺ -type diffusion layer 10 P ⁺
A negative voltage Ev is applied to the mold silicon substrate 1. E
The current when v increases in the negative direction starts increasing when the depletion layer extends from the P ⁺ -type diffusion layer 12-2 and reaches the P ⁺ -type silicon substrate. The voltage at this time (punch through voltage V _PT ) is measured (step 104).

This V _PT has a correlation with the saturated drain current I _DSS of the completed J-FET. However, it is determined based on data of a sample in which a resistive element is not built in or a sample in which the resistive element is short-circuited with aluminum-based wiring. FIG. 10 is a graph showing the relationship between V _PT and I _DSS obtained experimentally. I _DSS is predicted from this graph (step 105). When the predicted value of the I _DSS is larger than the design value, by adding the heat treated P ⁺ -type diffusion layer 10-1 and 10
The indentation diffusion of -2 is performed (steps 106 and 103).
Predicted value of I _DSS repeats steps 104,105,106,103,104 until a matching tolerance and design values. Next, as shown in FIG. 4 (b), P ⁺ -type diffusion layer 10
-1, openings 13-1 and 13-2 are formed on both sides, phosphorus is implanted, and annealing is performed to form N ⁺ type diffusion layers 14-1 and 14-1.
4-2 is formed (step 107).

Next, the optimum value of the bias resistor R _S is obtained from the predicted value of I _DDS (step 200). FIG.
₄ shows the relationship between _DSS and optimal R _S. FIG. 11 shows the gate-source voltage V _{GS of a} J-FET without a built-in bias resistor.
FIG. 9 is a graph showing the results of measuring the relationship between and the saturated drain current I _DSS for two samples while changing the ambient temperature. Find a similar graph for some samples,
FIG. 5 shows the result of _obtaining the relationship between I _DSS and the optimum R _S value. 5 and 10, the optimum R _S value can be obtained from the punch-through voltage V _PT . For example, when the punch-through voltage V _PT is 5.0 V, the predicted value of I _DSS is 1 mA from FIG. When I _DSS is to produce a 1mA J-FET is by 5, so that to incorporate a bias resistor 0.30Keiomega (step 200).
If this bias resistor is formed of a polysilicon film, the resistance value of the polysilicon film changes depending on the impurity concentration.

By the way, after step 107, CVD
4C, a non-doped polysilicon film 20 having a thickness of 400 nm is deposited as shown in FIG.
02), thermal oxidation is performed to form a thin oxide film (not shown) (step 203). This is to protect the polysilicon film from damage during the next ion implantation.
Next, phosphorus or boron is ion-implanted (step 2).
04), the injection amount is 0.30 kΩ as described above.
(Step 201). Next, annealing is performed and patterning is performed in a rectangular shape to form a polysilicon film resistor 20a as shown in FIG. 4D (step 205), a silicon nitride film 16 is formed, and a contact hole 17- is formed. 1,17
-2, 20-1, 20-2, and Al-Si-Cu
A film is deposited and patterned to form an aluminum wiring 18-
1A, 18-2, bonding pads 22-2, 22-
Form 2

FIG. 6 shows a semiconductor device 30A of the present embodiment.
FIG. 4 is a circuit diagram of a source bias resistor R _SA of a J-FET.
Is connected and built-in. The source terminal S is connected to the bonding pad 22-1, and the drain terminal D and the gate terminal 9 are connected to the bonding pad 22-2 and the back electrode 23, respectively.

Since the bias resistance R _SA is optimized within the range of variation within a lot, the temperature change of the saturation drain current of each semiconductor device is small.

As described above, the most basic shape of the J-FET has been described for convenience of explanation. However, in practice, in order to increase the current, a plurality of gate regions are formed across the FET formation region. It goes without saying that finger-shaped source electrode wiring and drain electrode wiring are formed in parallel, and finger-shaped source electrode wiring and drain electrode wiring are provided on both sides of an arbitrary gate region such that one source region and one drain region are respectively addressed.

Although the case where the resistance value of the polysilicon film resistance element is determined by impurities has been described, the resistance value may be determined by the thickness and shape using a thin film resistance element such as Ni—Cr or CrSi _2. Good.

Further, the N-channel J-FET has been described, but a bias resistor can be built in the P-channel J-FET.

[0030]

The first effect is that a J-FET having a small change in the saturated drain current due to the ambient temperature can be realized effectively. The reason is that the bias resistance is built in series with the source, but the optimum resistance value for performing the temperature compensation can be determined for each wafer.

The second effect is that the set using the J-FET can be reduced in size.

The reason is that a temperature compensating resistor is built in, and it is not necessary to secure a region on the circuit board for externally attaching the resistor separately from the J-FET.

A third effect is that the cost and time for mounting components of a set using a J-FET are reduced.

The reason is that the temperature compensation resistor is a J-FET
This is because the number of components is reduced.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1A) showing a semiconductor device according to an embodiment of the present invention, and a sectional view taken along line XX of FIG. 1A (FIG. 1B).

FIG. 2 is a flowchart for explaining a manufacturing method according to an embodiment of the present invention.

FIGS. 3A to 3D are cross-sectional views in the order of steps, illustrating the manufacturing method according to the embodiment of the present invention; FIGS.

FIG. 4 is a cross-sectional view in the order of steps, which is separated from (a) to (d) following FIG. 3;

FIG. 5 is a graph showing a relationship between a saturation drain current I _DSS and an optimum R _S.

FIG. 6 is a circuit diagram of a semiconductor device according to one embodiment of the present invention.

7A to 7D are cross-sectional views in the order of steps for explaining the conventional technique.

FIG. 8 is a sectional view in the order of steps, which is shown separately in FIGS.

FIG. 9 is a flowchart for explaining a conventional technique.

FIG. 10 shows punch-through voltage V _PT and saturation drain current I
Graph showing the relationship with _DSS .

FIG. 11 is a graph showing the relationship between the gate voltage V _GS and the saturation drain current I _DSS and changing the ambient temperature.

FIG. 12 is a circuit diagram in which a bias resistor R _S is connected to the source of a J-FET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P ⁺ type silicon base 2 N type semiconductor layer 3 Silicon oxide film 4 Opening 5, 5A P ⁺ type element isolation region 6 Oxide film 7 Silicon oxide film 8-1, 8-2 Opening 9-1, 9-2 Boron implantation Layer 10-1, 10-2 P ⁺ type diffusion layer 11 Oxide film 12-1, 12-2 Needle electrode 13-1, 13-2 Opening 14-1, 14-2 N ⁺ type diffusion layer 15 Oxide film 16 Silicon nitride film 17-1, 17-2 Contact hole 18-1, 18-1A, 18-2 Aluminum-based wiring 19 Surface protection film 20 Polysilicon film 20a Polysilicon film resistor 21-1, 21-2 Contact hole 22 -1,22-2 bonding pad 23 backside electrode 30 resin-sealed J-FET 30A semiconductor device 100～108,200～205 step numbers R _S, R _SA bias resistor I _DS1, I _DS2 drain Current I _DSS, I _DSS1, I _DSS2 saturation drain current V _GS between the gate and the source voltage V _Q I temperature change _DSS becomes zero gate-source voltage

Claims (4)

[Claims] 1. A semiconductor device comprising: a junction field effect transistor formed on a semiconductor substrate; and a resistance element having one end connected to a source region of the junction field effect transistor, wherein the resistance element includes the junction field effect transistor. A semiconductor device comprising a bias resistor for compensating a temperature change of a saturation drain current of a transistor. 2. A semiconductor device comprising: a first conductivity type semiconductor substrate formed by depositing a second conductivity type semiconductor layer on a first conductivity type semiconductor substrate; and a first conductivity type diffusion layer formed on the second conductivity type semiconductor layer of the semiconductor substrate. A junction field effect transistor having a source electrode and a drain electrode respectively in contact with the second conductivity type semiconductor layer, and a film resistor selectively covering an insulating film covering the second conductivity type semiconductor layer The semiconductor device according to claim 1, further comprising: a resistance element having: 3. An element isolation region extending from a surface of the second conductive type semiconductor layer of the semiconductor substrate formed by depositing a second conductive type semiconductor layer on the first conductive type semiconductor substrate to reach the first conductive type semiconductor substrate. Forming a gate region made of a first conductivity type diffusion layer in a second conductivity type semiconductor layer of the FET formation region and the check element formation region, Measuring a punch-through voltage at which a depletion layer extending from the gate region reaches the first conductivity type semiconductor substrate by applying a voltage to the gate region of the first conductivity type semiconductor substrate and the check element formation region;
Forming a resistive element having a resistance value according to the punch-through voltage and connecting the resistive element to a second conductivity type semiconductor layer in the FET forming region, wherein the resistive element is connected to a gate region of the FET forming region and a second conductive type semiconductor layer. A method of manufacturing a semiconductor device, comprising: a bias resistance for compensating a temperature change of a saturation drain current of a junction field effect transistor having a channel of a second conductivity type semiconductor layer between semiconductor substrates of one conductivity type. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a polycrystalline silicon film covering the insulating film is deposited, doped with an impurity according to a punch-through voltage, and patterned to form a resistance element.