JPH1064923A - High frequency field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency field effect transistor with which the design of a resonance frequency is facilitated and a gain is improved by reducing a source inductance. SOLUTION: Concerning a field effect transistor, of which a source electrode 5 is grounded in the manner of DC by plating on the side face of a semi- insulated substrate 1, formed on the semi-insulated substrate 1 and connected to the source electrode 5 or the rear side of the semi-insulated substrate 1 by via hole structure, a via hole 9 is formed from the rear side of the semi- insulated substrate 1 to the rear side of the source electrode 5 from which an active layer 2 at a central part is removed, a metal layer 6 is embedded on the rear side of the semi-insulated substrate 1 including the via hole 9, and a desired capacitor 3 is formed between the metal layer 6 and the source electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor formed on a semi-insulating substrate, and more particularly to a high frequency field effect transistor having a direct via hole structure.

[0002]

2. Description of the Related Art Generally, in a field effect transistor, a gain is reduced by a source series inductance generated by a lead wire from a source electrode to a source pad or a wire on the front and back surfaces of an element in a via hole.

FIG. 8 is a diagram showing a first conventional example of a field effect transistor. FIG. 9 is a diagram showing an equivalent circuit of the field-effect transistor shown in FIG. 8, a semi-insulating layer 13 and an active layer (hereinafter, referred to as an FET active layer) 2 of a field-effect transistor are formed on a GaAs substrate 1, and after a gate electrode 7 is formed, an FET protective film is formed. 8 are formed. A via hole 9 is formed below the source electrode 5, and a back surface electrode 6 is formed on the entire back surface including the via hole 9. In FIG. 9, L1 represents the inductance of the via hole 9 portion.

As described above, by providing the via hole 9 immediately below the source electrode 5, a source series inductance generated by a wiring (not shown) is removed, and a decrease in gain is suppressed.

FIGS. 10 and 11 show a second conventional example of a field-effect transistor. FIG.
FIG. 12 is a diagram showing an equivalent circuit of the field-effect transistor shown in FIGS. 10 and 11. In FIG. 10, an FET active layer 2 is formed on a GaAs substrate 1, and a source ohmic 4 is formed on the FET active layer 2. A via hole 9 is formed below the source lead-out line 14 extending from above the source ohmic 4, and a back surface electrode 6 is formed on the entire back surface including the via hole 9. Also, in FIG.
A dielectric film 3 is formed below the substrate. In FIG.
L1 represents the inductance of the via hole 9 and L1
2 is an air bridge (not shown) or a source lead-out line 14
Represents the series inductance generated by
Represents a capacitance formed by the dielectric film 3, and C2 represents a parasitic capacitance generated by an air bridge (not shown) or the source lead-out wiring.

As described above, a capacitor (dielectric film 3) is provided at the via hole 9 to form a resonance circuit between the capacitor and the source series inductance, and the inductance near this resonance frequency is reduced to reduce the gain. Deterred.

[0007]

A problem in the first conventional example is that in the direct via hole technology in which a via hole is provided immediately below a source electrode, the inductance of the via hole portion is not completely removed, so that an electric field is not generated. This means that the gain of the effect transistor is reduced. The reason is that the via hole is formed immediately below the source electrode, so that the floating inductance due to the wiring can be removed, but the inductance generated by the wiring on the front and back surfaces of the element in the via hole cannot be removed. is there.

A problem in the second conventional example is that it is difficult to obtain a desired resonance frequency between the inductance and the capacitance by the technique of forming a via hole having a capacitor. The reason is that since a via hole having a MIM structure capacitor is formed at a position distant from the source electrode, the inductance generated by the source lead-out wiring, the inductance generated by the wiring on the front and back surfaces of the element in the via hole portion, and furthermore, This is because the values of a plurality of floating factors such as the inductance and capacitance of the source bus bar in the finger field effect transistor must be obtained, and it is difficult to simulate or measure them.

In view of the foregoing, it is an object of the present invention to provide a high-frequency field-effect transistor which facilitates designing of a resonance frequency and reduces a source inductance to improve a gain.

[0010]

The high-frequency field effect transistor of the present invention is formed on a semi-insulating substrate, and is connected to the source electrode and the back surface of the semi-insulating substrate by a via hole structure or the back surface of the semi-insulating substrate. A field effect transistor in which the source electrode is grounded in a DC manner by plating on the side surface of a conductive substrate, and a via hole is formed from the back surface of the semi-insulating substrate on the back side of the source electrode from which the active layer in the central portion has been removed. Then, a metal layer is buried on the back surface of the semi-insulating substrate including the via hole, and a desired capacitor is formed between the metal layer and the source electrode.

In the high frequency field effect transistor according to the present invention, a dielectric film is formed before forming the source electrode in a central portion from which the active layer is removed, and the semi-insulating substrate is formed when forming the via hole. The desired capacitor can be provided with the dielectric film having a desired thickness.

Further, in the high frequency field effect transistor according to the present invention, a semi-insulating layer is formed when crystal growth is performed on the semi-insulating substrate, and the semi-insulating substrate is formed when the via hole is formed. The desired capacitor can be provided with the desired thickness of the semi-insulating layer.

By doing so, it is possible to select an appropriate capacitance by designing the dielectric film, as compared with a conventional field effect transistor having a direct via hole structure, and to adjust the resonance frequency to a desired frequency band. Becomes possible.

The wiring is drawn out from the source electrode to
Compared to the conventional structure grounded by via holes with IM-structured capacitors, source inductance can be eliminated by integrating the source electrode and via hole, which leads from the source electrode to the source pad. Thus, the desired resonance frequency can be designed by setting the capacitance without considering the inductance and capacitance of the source bus bar.

In this manner, the inductance of the via hole can be reduced, and a decrease in gain can be suppressed.

[0016]

Embodiments of the present invention will be described with reference to the drawings.

[1] First Embodiment FIGS. 1A and 1B are diagrams showing a structure of a high-frequency field effect transistor according to a first embodiment of the present invention, FIG. 1A is a plan view, and FIG. Shows a cross-sectional view.

The high frequency field effect transistor shown in FIG. 1 penetrates the GaAs substrate 1 behind the center of the source electrode 5 where the source ohmic 4 is not formed and the FET protective film 8 and the FET active layer 2 are removed. Thus, a via hole 9 reaching the dielectric film 3 is formed. A capacitor is formed by the dielectric film 3 having an arbitrary thickness formed between the back electrode 6 and the source electrode 5 which are a metal layer embedded in the via hole 9.

Here, an example of a method of forming the source electrode portion according to the first embodiment of the present invention will be described. FIG. 2 is a diagram illustrating a step of forming a source electrode unit according to the first embodiment of the present invention.

In FIG. 2A, after securing the FET active layer 2 on the GaAs substrate 1 by ion implantation or epitaxial growth to form the gate 7, the FET protective film 8 is formed. In FIG. 2B, after a source ohmic 4 is formed using lift-off, a source electrode 5 is formed.
The FET active layer 2 and the FET protective film 8 in the central portion where the GaN layer is formed are removed by etching. In FIG. 2C, a dielectric film 3 is grown, a contact of a source ohmic 4 is opened, and a source electrode 5 is formed. In FIG. 2D, after a via hole 9 is formed from the back surface of the GaAs substrate 1 to the center of the source electrode 5, a back electrode 6 is formed.

[2] Second Embodiment FIG. 3 is a diagram showing a cross-sectional structure of a high-frequency field effect transistor according to a second embodiment of the present invention.

In the high-frequency field effect transistor shown in FIG. 3, a semi-insulating layer 13 is grown during crystal growth, and no source ohmic 4 is formed.
A via hole 9 is formed from the back surface of the GaAs substrate 1 so as to reach the semi-insulating layer 13 on the back side of the central portion of the source electrode 5 from which the ET active layer 2 has been removed. The semi-insulating layer 13 formed between the back electrode 6 and the source electrode 5 which is the formed metal layer serves as a dielectric film to form a capacitor having an MIM structure.

Here, an example of a method of forming a source electrode portion according to the second embodiment of the present invention will be described. FIG. 4 is a diagram illustrating a process of forming a source electrode unit according to the second embodiment of the present invention.

In FIG. 4A, a semi-insulating layer 13 is grown on a GaAs substrate 1 during crystal growth, and a gate 7 is formed by securing an FET active layer 2 by ion implantation or epitaxial growth. 8 is formed. In FIG. 4B, after the source ohmic 4 is formed by using lift-off, the FET active layer 2 and the FET protective film 8 in the central portion where the source electrode 5 is formed are removed by selective crystal etching, and the source electrode 4 is removed. 5 is formed. In FIG. 4C, a via hole 9 is formed from the back surface of the GaAs substrate 1 to the center of the source electrode 5 by selective crystal etching, and then a back electrode 6 is formed.

[3] Design of Dielectric Film FIG. 5 is a diagram showing an equivalent circuit of the field effect transistor according to the present invention, and shows an equivalent circuit of the field effect transistor shown in FIG. 1 or FIG. A method for designing a dielectric film will be described with reference to FIGS.

In FIG. 5, the bus shown in FIG. 1 or FIG.
The inductance at the back electrode 6 of the ear hole 9 is represented by L
1, and the dielectric film 3 shown in FIG.
The capacitance generated by forming the edge layer 13 is represented by C1.
And the use angular frequency is ω, the via hole 9
Is the effective inductance of L1 [1- ｛1 / (ω ^Two 
L1 · C1)｝]. Therefore, 0 ≦ 1 / (ω^Two 
L1 · C1) ≦ 1, that is, C1 ≧ 1 / (ω^Two ・ L1)
And this effective inductance is in the via hole 9
Has the effect of being smaller than the inductance L1 of the
You. In particular, C1 ≒ 1 / (ω^Two• In the vicinity of L1), this effect
Fruit is big. Therefore, the thickness of the dielectric film
Design to manifest.

By selecting an appropriate capacitance in this manner, the resonance frequency can be adjusted to a desired frequency band as compared with a conventional direct via hole structure field effect transistor. As a result, the inductance of the via hole 9 can be reduced, and a decrease in gain can be suppressed.

FIGS. 6 and 7 show a method of supplying a DC bias to a field effect transistor according to the present invention.

In the equivalent circuit shown in FIG. 5, at a frequency lower than the resonance frequency, the impedance of the via hole via the capacitor becomes very high. However, FIG.
Is grounded by a via hole 9 * in contact with the high inductance wiring 10 drawn from the source electrode 5 without using a capacitor. In FIG. 7, grounding is provided by side plating 12 which is connected to the high inductance wiring 10 and serves as a back electrode of the via hole 9. By doing so, the impedance can be sufficiently reduced on the low frequency side even if the inductance is large. However, when grounding, use via holes 9 * to prevent short circuits in the high frequency band.
Alternatively, it is necessary to provide the high inductance wiring 10 between the side plating 12 and the source electrode 5.

As described above, the source electrode 5 and the via hole 9
To remove the source inductance due to the lead-out wiring from the source electrode to the source pad, as compared with the conventional structure in which the wiring is drawn out from the source electrode and grounded by a via hole having a capacitor of the MIM structure. It is possible to design a desired resonance frequency by setting the capacitance without considering the inductance and capacitance of the source bus bar.

[0031]

The first effect is that the resonance circuit for reducing the source inductance can be easily designed, and the gain can be improved by reducing the source inductance. The reason is that by integrating the source electrode and the via hole, it is possible to remove the inductance due to the lead-out wiring from the source electrode to the source pad, and it is possible to remove the inductance and the capacitance due to the source bus bar. This is because the power inductance is limited to the via hole inductance.

The second effect is that the chip area can be reduced. The reason is that the source electrode and the via hole having the capacitor of the MIM structure can be integrated.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a high-frequency field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a process of forming a source electrode unit according to the first embodiment of the present invention;

FIG. 3 is a diagram showing a cross-sectional structure of a high-frequency field effect transistor according to a second embodiment of the present invention.

FIG. 4 is a view showing a process of forming a source electrode unit according to a second embodiment of the present invention;

FIG. 5 is a diagram showing an equivalent circuit of a field-effect transistor according to the present invention.

FIG. 6 is a diagram showing a method for supplying a DC bias to a field-effect transistor according to the present invention.

FIG. 7 is a diagram showing a DC bias supply method for a field effect transistor according to the present invention.

FIG. 8 is a diagram showing a field effect transistor in a first conventional example.

9 is a diagram showing an equivalent circuit of the field-effect transistor shown in FIG.

FIG. 10 is a diagram showing a field effect transistor in a second conventional example.

FIG. 11 is a diagram showing a field effect transistor in a second conventional example.

FIG. 12 is a diagram showing an equivalent circuit of the field-effect transistor shown in FIGS. 10 and 11;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 GaAs substrate 2 FET active layer 3 dielectric film 4 source ohmic 5 source electrode 6 back electrode 7 gate 8 FET protective film 9, 9 * via hole 10 high inductance wiring 12 side plating 13 semi-insulating layer 14 source lead wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/095

Claims (3)

[Claims] The source electrode is formed on a semi-insulating substrate and is DC grounded by a via-hole structure or by plating on the side surface of the semi-insulating substrate connected to the source electrode and the back surface of the semi-insulating substrate. In the field effect transistor, a via hole is formed from the back surface of the semi-insulating substrate on the back side of the source electrode from which the central active layer is removed, and the back surface of the semi-insulating substrate including the via hole is formed. A high frequency field effect transistor, wherein a desired capacitor is formed between the metal layer and the source electrode. 2. A dielectric film is formed before forming the source electrode at a central portion where the active layer is removed, and when forming the via hole, the dielectric film penetrates the semi-insulating substrate and reaches the dielectric film. The high-frequency field effect transistor according to claim 1, wherein the desired capacitor includes the dielectric film having a desired thickness. 3. A semi-insulating layer is formed when crystal growth is performed on the semi-insulating substrate, and reaches the semi-insulating layer through the semi-insulating substrate when forming the via hole. The high frequency field effect transistor according to claim 1, wherein the desired capacitor includes the semi-insulating layer having a desired thickness.