JPH03230579A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03230579A JPH03230579A JP2635390A JP2635390A JPH03230579A JP H03230579 A JPH03230579 A JP H03230579A JP 2635390 A JP2635390 A JP 2635390A JP 2635390 A JP2635390 A JP 2635390A JP H03230579 A JPH03230579 A JP H03230579A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- semiconductor substrate
- mask
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 abstract 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 241001663154 Electron Species 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に引き出し電
極の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an extraction electrode.
従来から高周波帯で用いられている半導体装置の断面図
を第2図に示す。半絶縁性基板1上に半導体層2を設け
た半導体基板の表面側に、イオン注入等を行なったのち
、ソース電極3、ゲート電極4およびドレイン電極5を
形成し、電界効果トランジスタ(FET)を作製する。FIG. 2 shows a cross-sectional view of a semiconductor device conventionally used in a high frequency band. After performing ion implantation, etc. on the front side of a semiconductor substrate in which a semiconductor layer 2 is provided on a semi-insulating substrate 1, a source electrode 3, a gate electrode 4, and a drain electrode 5 are formed, and a field effect transistor (FET) is formed. Create.
その後、半導体基板に貫通孔6を作製し、裏面の全面に
金属からなる裏面導電膜7を形成する。このバイア・ホ
ール技術により、寄生回路要素を極力低減させて接地で
き、このため高周波半導体デバイスにおいて広く用いら
れている。Thereafter, a through hole 6 is formed in the semiconductor substrate, and a back conductive film 7 made of metal is formed on the entire back surface. This via-hole technology allows grounding with a minimum of parasitic circuit elements, and is therefore widely used in high-frequency semiconductor devices.
バイア・ホールを形成する方法としては、ウェットエツ
チングを用いる方法とドライエツチングを用いる方法が
ある。前者の方法は、第3(a)図に示すように、基板
1の裏面にマスク8を形成し、その開口から半導体基板
をエツチングするものである。しかし、この方法による
と、サイドエツチングが大幅に入るため所望の開口の大
きさよりも大きくなり、表側の電極3のサイズよりもバ
イア・ホールがはみだして穴があいたり、電極3が陥没
したりする不良が発生して歩留りが低下する。また均一
性が悪く、バイア・ホールがあく部分と、あかない部分
が(j在したりする。後者の方法は、Nl 、AI な
どのメタルマスクを用いて、RI E (Reacti
ve Ion Etching)や、ECR(Elec
tron Cyclotron Re5onance)
エツチングなどの方法により基板をエツチングするもの
である。Methods for forming via holes include a method using wet etching and a method using dry etching. In the former method, as shown in FIG. 3(a), a mask 8 is formed on the back surface of the substrate 1, and the semiconductor substrate is etched through the opening thereof. However, according to this method, side etching is significantly involved, resulting in an opening larger than the desired size, and the via hole protrudes beyond the size of the electrode 3 on the front side, resulting in a hole or the electrode 3 sinking. Defects occur and the yield decreases. In addition, the uniformity is poor, and there are some areas where via holes are open and others where they are not.The latter method uses a metal mask of Nl, AI, etc.
ve Ion Etching) and ECR (Elec
tron Cyclotron Re5onance)
The substrate is etched using a method such as etching.
この時、適当なエツチング条件を選べば、垂直に近いエ
ツチングプロファイルが得られる(異方性エツチング)
。しかしながら、その後にメタルマスクを除去してから
表面側の電極3を接地するために、TI/Au等の金属
を裏面より蒸着して裏面導電膜7を形成すると、第3図
(b)に示す通り、バイア・ホールの側壁の金属付着が
不十分で、寄生回路要素を十分に低減できないという問
題があった。At this time, if appropriate etching conditions are selected, a nearly vertical etching profile can be obtained (anisotropic etching).
. However, after removing the metal mask, in order to ground the electrode 3 on the front side, metal such as TI/Au is deposited from the back side to form a back conductive film 7, as shown in FIG. 3(b). However, there was a problem in that the metal adhesion on the sidewalls of the via holes was insufficient, making it impossible to sufficiently reduce parasitic circuit elements.
そこで本発明は、上記従来技術の有していた問題点を解
決できる半導体装置の製造方法を提供することを目的と
する。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the problems of the above-mentioned prior art.
本発明に係る半導体装置の製造方法は、表面に電極が形
成された半導体基板を裏面から選択的にエツチングして
電極の裏面に達する貫通孔を形成し、半導体基板の裏面
側から導電材料を被着して当該半導体基板の裏面、貫通
孔の壁面および電極の裏面に導電膜を形成する半導体装
置の製造方法において、半導体基板の裏面に第1のマス
ク材と第2のマスク材を順次に被着して電極に対応する
位置に開口を有する第1および第2のマスクパターンを
形成する第1の工程と、第1のマスク材に対してエツチ
ング能を有するエッチャントを用いて、第1および第2
のマスクパターンの開口を介して半導体基板を異方性エ
ツチングし、貫通孔を形成する第2の工程と、第1およ
び第2のマスクパターンを除去して導電材料を被告する
第3の工程とを備えることを特徴とする。A method for manufacturing a semiconductor device according to the present invention includes selectively etching a semiconductor substrate having an electrode formed on the front surface from the back side to form a through hole reaching the back side of the electrode, and covering the semiconductor substrate with a conductive material from the back side. A method for manufacturing a semiconductor device in which a conductive film is formed on the back surface of the semiconductor substrate, the wall surface of the through hole, and the back surface of the electrode by sequentially covering the back surface of the semiconductor substrate with a first mask material and a second mask material. a first step of forming first and second mask patterns having openings at positions corresponding to the electrodes; and a step of forming first and second mask patterns having openings at positions corresponding to the electrodes; 2
a second step of anisotropically etching the semiconductor substrate through the openings in the mask pattern to form a through hole; and a third step of removing the conductive material by removing the first and second mask patterns. It is characterized by having the following.
本発明によれば、半導体基板が異方性エツチングされる
過程で基板側の第1のマスクパターンがサイドエツチン
グされるので、異方性エツチングが半導体基板の表面に
形成された電極に達するまでの間に、半導体基板のサイ
ドエツチングも進行し、従って基板の裏面側で広くなっ
た貫通孔が形成される。According to the present invention, the first mask pattern on the substrate side is side-etched during the anisotropic etching process of the semiconductor substrate, so that the anisotropic etching does not reach the electrodes formed on the surface of the semiconductor substrate. During this time, side etching of the semiconductor substrate also progresses, and therefore a through hole is formed which becomes wider on the back side of the substrate.
以下、添付図面を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第1図は実施例に係る半導体装置の製造方法を示す工程
別の素子断面図である。なお、第1図ではMESFET
のソース電極3の近傍のみを示し、他の部分は省略しで
ある。また、図の下側がMESFET等を形成する半導
体基板の表面側、上側が半導体基板の裏面側となってい
る。まず、半絶縁性Ga Asなどの基板1が用意され
、この表面にエピタキシャル成長法などでGa Asな
どの半導体層2が形成され、これらによって半導体基板
が構成される。そして、半導体基板の表面すなわち半導
体層2には、イオン注入やリフトオフ法などによりME
S F ETが形成される。第1図(a)はこの状態
を示している。FIG. 1 is a cross-sectional view of an element in each step showing a method of manufacturing a semiconductor device according to an embodiment. In addition, in Figure 1, MESFET
Only the vicinity of the source electrode 3 is shown, and other parts are omitted. Further, the lower side of the figure is the front side of the semiconductor substrate on which MESFETs and the like are formed, and the upper side is the back side of the semiconductor substrate. First, a substrate 1 made of semi-insulating GaAs or the like is prepared, and a semiconductor layer 2 made of GaAs or the like is formed on the surface thereof by epitaxial growth or the like, thereby forming a semiconductor substrate. Then, ME is applied to the surface of the semiconductor substrate, that is, the semiconductor layer 2, by ion implantation, lift-off method, etc.
A S FET is formed. FIG. 1(a) shows this state.
次に、半導体基板の裏面すなわち基板1上に第1、第2
のマスク材を順次に被着し、2重構造のマスクを形成す
る。すなわち、裏面全面にマグネトロンスパッタ、EC
RプラズマCVDなどにより、S iO2などからなる
絶縁膜11を被着し、その上にフォトレジスト膜21を
形成する(同図(b)図示)。しかる後、フォトリソグ
ラフィ技術によってフォトレジスト膜21をソース電極
6に対応する部分で選択的に残存させてバイアホールパ
ターンとし、その上にAr、N1等の金属膜12を蒸着
等で被着する(同図(C)図示)。Next, on the back side of the semiconductor substrate, that is, on the substrate 1,
Mask materials are sequentially applied to form a double-layered mask. In other words, magnetron sputtering and EC are applied to the entire back surface.
An insulating film 11 made of SiO2 or the like is deposited by R plasma CVD or the like, and a photoresist film 21 is formed thereon (as shown in FIG. 4B). Thereafter, the photoresist film 21 is selectively left in the portion corresponding to the source electrode 6 by photolithography to form a via hole pattern, and a metal film 12 of Ar, N1, etc. is deposited thereon by vapor deposition or the like. Figure (C) shown).
次に、バイアホールパターンとしてのフォトレジスト膜
21を除去すると、その上の金属膜12が除去され、第
2のマスクパターンが得られる。Next, when the photoresist film 21 serving as a via hole pattern is removed, the metal film 12 thereon is removed, and a second mask pattern is obtained.
しかる後、第2のマスクパターンである金属膜12をマ
スクとして絶縁膜11を選択的にCF4や塩素系ガスで
ドライエツチングすると、第2のマスクパターンに対応
した第1のマスクパターンが絶縁膜11により得られる
。このとき、第1のマスクパターンおよび第2のマスク
パターンの開口で露出した基板1の位置は、半導体層2
上のソース電極3の位置と対応している(同図(d)図
示)。Thereafter, when the insulating film 11 is selectively dry etched with CF4 or chlorine gas using the metal film 12 as the second mask pattern as a mask, the first mask pattern corresponding to the second mask pattern becomes the insulating film 11. It is obtained by At this time, the position of the substrate 1 exposed through the openings of the first mask pattern and the second mask pattern is the same as that of the semiconductor layer 2.
This corresponds to the position of the source electrode 3 above (as shown in FIG. 2(d)).
次に、CC92F2とArの混合ガスをエッチャントと
して基板1と半導体層2からなる半導体基板を異方性エ
ツチングすると、半導体基板1は深さ方向に除去されて
いく (同図(e)図示)。Next, when the semiconductor substrate consisting of the substrate 1 and the semiconductor layer 2 is anisotropically etched using a mixed gas of CC92F2 and Ar as an etchant, the semiconductor substrate 1 is removed in the depth direction (as shown in FIG. 3(e)).
ここで、上記エッチャントは半導体基板を構成するGa
Asに対してエツチング能を有するだけでなく、第1
のマスクパターンを構成する8102等の絶縁膜11に
もエツチング能を有しているので、半導体基板が除去さ
れる過程で第1のマスクパターンもサイドエツチングさ
れていく (同図(f)図示)。このため、基板1及び
半導体層2に貫通孔が形成されてソース電極3の裏面が
露出されたときには、貫通孔の側壁は一定の傾斜を有す
ることになる(同図(g)図示)。Here, the above etchant is Ga constituting the semiconductor substrate.
It not only has etching ability for As, but also has the first
Since the insulating film 11 such as 8102 that constitutes the mask pattern also has etching ability, the first mask pattern is also side-etched during the process of removing the semiconductor substrate (as shown in FIG. 3(f)). . Therefore, when a through hole is formed in the substrate 1 and the semiconductor layer 2 and the back surface of the source electrode 3 is exposed, the side wall of the through hole has a certain slope (as shown in FIG. 2(g)).
次に、フッ酸系エッチャントで絶縁膜11、金属膜12
の2重マスクを除去し、基板1の裏面側からTI/Au
を蒸着等で被着し、裏面導電膜7を形成する。このとき
、貫通孔は裏面側に広くなるように形成されているため
、裏面導電膜7は貫通孔の側壁でも一定の厚さを有する
ことになる(同図(h)図示)。従って、寄生回路要素
を十分に低減させながらソース電極3を良好に接地でき
る。Next, the insulating film 11 and the metal film 12 are etched using a hydrofluoric acid etchant.
TI/Au is removed from the back side of the substrate 1.
is deposited by vapor deposition or the like to form the back conductive film 7. At this time, since the through-hole is formed so as to become wider toward the back side, the back conductive film 7 has a constant thickness even on the side wall of the through-hole (as shown in FIG. 4(h)). Therefore, the source electrode 3 can be well grounded while sufficiently reducing parasitic circuit elements.
なお、上記実施例において、貫通孔側壁の傾斜の程度は
、次のような条件を適切に選ぶことにより、任意に設定
できる。まず、使用するエッチャントの異方性の程度に
より設定でき、例えば異方性を強くすれば傾斜は小さく
なる。次に、半導体基板に接する第1−のマスクパター
ンの材料および厚さにより、傾斜の程度を設定できる。In the above embodiments, the degree of inclination of the side wall of the through hole can be arbitrarily set by appropriately selecting the following conditions. First, it can be set depending on the degree of anisotropy of the etchant used; for example, the stronger the anisotropy, the smaller the slope. Next, the degree of inclination can be set depending on the material and thickness of the first mask pattern in contact with the semiconductor substrate.
すなわち、第1のマスクパターンが厚いときには傾斜は
大きくなり、第1のマスクパターンがエツチングされや
すい材料のときにも傾斜は大きくなると考えられる。従
って、上記の設定により貫通孔内壁の傾斜を所望の値と
し、裏面導電膜7としてこれに見合った材料および厚さ
を選ぶことで、裏面導電膜7と表面のソース電極3の良
好な接続が可能になる。That is, it is considered that the slope becomes large when the first mask pattern is thick, and also becomes large when the first mask pattern is made of a material that is easily etched. Therefore, by setting the slope of the inner wall of the through hole to a desired value through the above settings and selecting a suitable material and thickness for the back conductive film 7, a good connection between the back conductive film 7 and the source electrode 3 on the front surface can be achieved. It becomes possible.
以上、詳細に説明した通り本発明では、半導体基板か異
方性エツチングされる過程で、基板側の第1のマスクパ
ターンがサイドエンチングされるので、異方性エツチン
グが半導体基板の表面に形成された電極に達するまでの
間に、半導体基板のサイドエツチングも進行し、従って
基板の裏面側で広くなった貫通孔が形成される。このた
め、半導体基板の裏面から導電材料を被着することで、
表面の電極と裏面導電膜の良好な接続が可能になる。本
発明は寄生回路要素を十分に低減させて表面側の電極を
接地することが可能になるため、高周波半導体デバイス
の製造に適している。As described above in detail, in the present invention, the first mask pattern on the substrate side is side-etched during the process of anisotropically etching the semiconductor substrate, so that anisotropic etching is formed on the surface of the semiconductor substrate. Before reaching the etched electrode, side etching of the semiconductor substrate also progresses, and a through hole is formed that becomes wider on the back side of the substrate. Therefore, by depositing a conductive material from the back side of the semiconductor substrate,
Good connection between the electrode on the front surface and the conductive film on the back surface becomes possible. The present invention is suitable for manufacturing high-frequency semiconductor devices because it is possible to sufficiently reduce parasitic circuit elements and ground electrodes on the surface side.
第1図は本発明の実施例に係る半導体装置の製造方法の
工程図、第2図は高周波帯で用いられる半導体デバイス
の断面図、第3図は従来方法を示す断面図である。
1・・・半導体基板、2・・・半導体層、3・・・ソー
ス電極、7・・・裏面導電膜、11・・・絶縁膜(第1
のマスクパターン)、12・・・金属膜(第2のマスク
パターン)、21・・・フォトレジスト膜。FIG. 1 is a process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device used in a high frequency band, and FIG. 3 is a sectional view showing a conventional method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Semiconductor layer, 3... Source electrode, 7... Back conductive film, 11... Insulating film (first
mask pattern), 12... metal film (second mask pattern), 21... photoresist film.
Claims (1)
エッチングして前記電極の裏面に達する貫通孔を形成し
、前記半導体基板の裏面側から導電材料を被着して当該
半導体基板の裏面、貫通孔の壁面および前記電極の裏面
に導電膜を形成する半導体装置の製造方法において、 前記半導体基板の裏面に第1のマスク材と第2のマスク
材を順次に被着して前記電極に対応する位置に開口を有
する第1および第2のマスクパターンを形成する第1の
工程と、 前記第1のマスク材に対してエッチング能を有するエッ
チャントを用いて、前記第1および第2のマスクパター
ンの開口を介して前記半導体基板を異方性エッチングし
、前記貫通孔を形成する第2の工程と、 前記第1および第2のマスクパターンを除去して前記導
電材料を被着する第3の工程と を備えることを特徴とする半導体装置の製造方法。[Claims] A semiconductor substrate having an electrode formed on the front surface is selectively etched from the back side to form a through hole reaching the back side of the electrode, and a conductive material is applied from the back side of the semiconductor substrate. In the method for manufacturing a semiconductor device in which a conductive film is formed on the back surface of the semiconductor substrate, the wall surface of the through hole, and the back surface of the electrode, a first mask material and a second mask material are sequentially applied to the back surface of the semiconductor substrate. a first step of forming first and second mask patterns having openings at positions corresponding to the electrodes; and a first step of forming first and second mask patterns having openings at positions corresponding to the electrodes; and a second step of anisotropically etching the semiconductor substrate through an opening in a second mask pattern to form the through hole, and removing the first and second mask patterns to remove the conductive material. A method for manufacturing a semiconductor device, comprising: a third step of adhering the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2635390A JPH03230579A (en) | 1990-02-06 | 1990-02-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2635390A JPH03230579A (en) | 1990-02-06 | 1990-02-06 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03230579A true JPH03230579A (en) | 1991-10-14 |
Family
ID=12191108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2635390A Pending JPH03230579A (en) | 1990-02-06 | 1990-02-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03230579A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08160403A (en) * | 1994-12-07 | 1996-06-21 | Internatl Business Mach Corp <Ibm> | Liquid crystal displaydevice,preparation thereof and image forming method |
US8610284B2 (en) | 2008-11-10 | 2013-12-17 | Panasonic Corporation | Semiconductor device and electronic device |
CN105329840A (en) * | 2014-06-16 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Inclined hole etching method |
-
1990
- 1990-02-06 JP JP2635390A patent/JPH03230579A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08160403A (en) * | 1994-12-07 | 1996-06-21 | Internatl Business Mach Corp <Ibm> | Liquid crystal displaydevice,preparation thereof and image forming method |
US8610284B2 (en) | 2008-11-10 | 2013-12-17 | Panasonic Corporation | Semiconductor device and electronic device |
CN105329840A (en) * | 2014-06-16 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Inclined hole etching method |
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