JPH1063237A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer system capable of shortening the operation interruption time of a processor in transferring picture data to be generated by the operation of the processor to an external processing. SOLUTION: In a picture processing system 1, a processor 12 stores the picture data obtained from the result of an operation in a main storage device 13 and, at the same time, transmits the read instruction command of the picture data to an input-output channel 14 to set a flag of the operation flag 133 of the main storage device 13 in 'in operation' or ' completion of opertion'. Then, the main storage device 13 repeats a readout and a read-skip for every fixed data amount in order to neglect detail part of a picture based on readout addresses transmitted from the input-output channel 14 after the read instruction command had been received and the input-output channel 14 transfers the data read out from the main storage device 13 to a picture processor 16 being the external processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a supercomputer or the like used for scientific calculation, for example.
The present invention relates to a data transfer technique for efficiently transferring a large amount of image data generated by a processor in a short period of time to an external process while suppressing a decrease in computational performance of the processor.

[0002]

2. Description of the Related Art For example, in a supercomputer or the like capable of performing high-speed scientific and technological calculations in the scientific fields such as meteorology, molecular science, and nuclear fusion, a large amount of operation result data by a processor is generated in a short time. . Such operation result data must be efficiently transferred for external processing. Hereinafter, a conventional method for efficiently transferring the operation result data will be specifically described with reference to the image processing system shown in FIG. 5 as an example. The calculation result data in this case is image data.

Referring to FIG. 5, an image processing system 5
Is roughly divided into a computer system 51 that processes input data and outputs image data, and an image processing device 56 that converts image data output from the computer system 51 into a signal that can be displayed on a display or the like. I have.

In the computer system 51, a processor 52 for executing an arithmetic processing program on input data to generate image data, a main storage device 53 for storing the image data generated by the processor 52, and a main storage device 53 And an input / output channel 54 for transferring the image data stored in the image processing device to an image processing device 56 as an external processing device. Further, in the input / output channel 54, a memory access unit 541 that specifies a read address when reading image data to the main storage device 53 and performs read control, and temporarily stores the image data read from the main storage device 53. , A transfer control unit 542 for reading out image data stored in the data buffer 543, and a transfer control unit 54.
Image data read by the image processing device 56
And a data transfer unit 544 for transferring data to the system bus 54.
5 are connected.

The operation procedure of the image processing system 5 having the above configuration is as shown in FIG. That is, the processor 52 executes the image processing program to generate image data, and stores the image data in the main storage device 53 (step S60).
1). The processor 52 transmits an instruction command for instructing reading of the image data stored in the main storage device 53 to the input / output channel 54 (Step S60).
2). The memory access unit 541 of the input / output channel 54 that has received the image data read instruction command interprets the read instruction command and instructs the main storage device 53 on the read address and the read amount of the stored image data (step). S603). In accordance with this instruction, the main storage device 53 reads out the image data (step S
604). The data buffer 543 stores the image data read from the main storage device 53 (step S60).
5).

[0006] The data transfer unit 544 is connected to the image processing device 56.
When it is determined that data transfer is possible, the transfer control unit 542 is given permission to transfer image data (step S606). When the transfer permission is given, the transfer control unit 542 reads the image data from the data buffer 543, and reads the image data from the data buffer 543.
(Step S607). Image processing device 56
Receives the image data transmitted from the data transfer unit 544 (step S608), changes to a signal that can be displayed by a display or the like, and performs image display (step S6).
09).

[0007]

FIG. 7 is a time table showing an example of a processing state in the processor 52, the main storage device 53, and the input / output channel 54 of the image processing system 5.

Referring to FIG. 7, after a processor 52 executes arithmetic processing to generate image data, a main storage 5
3 stores the image data generated by the processor 52 in the main storage device 53. During this time, the main storage device 53 is being accessed by the processor 52. On the other hand, while the processor 52 suspends the operation (during the WAIT state),
The main storage device 53 is in an access state of the input / output channel 54, and the input / output channel 54 reads out image data stored in the main storage device 53.

However, as is clear from the time table, in the image processing system 5 having the above configuration, the amount of transfer data increases as the amount of image data, which is the operation result of the processor, increases. The access of the input / output channel 52 and the input / output channel 54 conflicts. That is, there has been a problem that the WAIT state of the processor 52 frequently occurs, and the arithmetic processing of the processor 52 is hindered. Therefore, an object of the present invention is to provide a data transfer method capable of shortening the operation interruption time that hinders the operation processing of the processor even when the amount of transfer data increases as the result of the operation by the processor increases. It is in.

[0010]

According to the present invention, there is provided a data transfer system for storing image data generated by an operation of a processor, and storing the generated image data in the memory. And a memory control unit for alternately reading the image data, and a unit for transferring the read image data to an external process. Each time the memory control unit stores the image data generated by the processor in the memory, The flag information indicating whether the processor at that time is in the middle of the operation or the end of the operation is held, and when the stored image data is read, the flag information when the image data is stored in the memory is being calculated. In the case of indicating that a part of the image data is read, for example, a part corresponding to details of the image is skipped.

When reading out the image data stored in the memory, the memory control means stores the image data if the flag information at the time of storing the image data indicates that the calculation is being performed. It is preferable that reading and skipping are alternately repeated by a fixed amount of data corresponding to one detail of an image from the head address of the area, and transfer of the skipped portion is omitted.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. Here, an embodiment will be described in which the present invention is applied to an image processing system capable of performing arithmetic processing on input data and displaying image data obtained by processing.

FIG. 1 is a block diagram of an image processing system according to an embodiment of the present invention. The image processing system 1 includes a computer system 11 that outputs image data obtained by performing arithmetic processing on input data;
And an image processing device 16 that converts the image data output from the device into a signal that can be displayed on a display or the like.

The computer system 11 includes a processor 12 for executing an arithmetic processing program on input data to generate image data, a main storage device 13 for storing the image data generated by the processor 12, and a main storage device. 13
Image data stored in the image processing device 16
And an input / output channel 14 for transferring to

The main storage device 13 controls a memory section 131 for storing image data generated by the processor 12 and controls writing and reading to and from the memory section 131 in accordance with address designation for reading and writing from the processor 12 and the input / output channel 14. An address setting unit 132 to perform;
When the processor 12 stores the image data, the processor 12 stores an operation flag 133 that stores flag information indicating either “under operation” or “operation end”.
They are connected to each other by.

In the input / output channel 14, the processor 12
Memory access unit 1 that performs read control by designating a read address to main storage device 13 in accordance with an instruction from
41, a data buffer 142 for temporarily storing image data read from the main storage device 13 by the memory access unit 141 to synchronize transfer with the image processing device 16;
A transfer control unit 143 that controls the transfer of image data from the data buffer 142 to the image processing device 16 is connected to each other by a system bus 134. In addition,
The address setting unit 132 determines the address of the read from the memory access unit 141 and
, A read address is designated every time image data is read, and the designated address differs depending on whether the flag of the operation flag 133 indicates “operation in progress” or “operation end”.

When a read address is specified from the input / output channel 14, the address setting unit 132 accesses the operation flag 133. At this time, the operation flag 13
When the flag of No. 3 indicates “in operation”,
The address setting unit 132 corresponds to one line when an image is displayed on the memory unit 131 (for example, 1280 bytes = 1K
b) Each time, reading and skipping are performed alternately,
When there is one line of image data to be read, an address is specified. Here, the discrete addresses are separated by the displacement of the address where the area for one row to be thinned out exists. When the flag of the operation flag 133 indicates “operation end”, a continuous address without skip is specified.

Referring to FIG. 2, the skipping process will be described in detail. FIG. 2 shows an area in the memory unit 131 where image data from the processor 12 is stored. Now, assuming that n is a natural number, data 1280 ×
(2n−2) +1 to 1280 × (2n−1) is the area of the image data to be read, while data 1280 × (2n
-1) to 1280 × 2n are areas of image data which are not read from the memory unit 131 as a result of being skipped.
When the flag of the operation flag 133 indicates “under operation”, the address setting unit 132
The address designation of 0 × (2n−2) +1 to 1280 × (2n−1) is performed for the memory unit 131.

FIG. 3 is an explanatory diagram of a data transfer processing procedure in the image processing system 1 having the above configuration. Hereinafter, FIG.
The processing procedure of the data transfer will be described with reference to FIG. First,
The processor 12 generates image data by an operation based on the image processing program, and stores the image data in the main storage device 13 by designating a storage address (step S30).
1). When the processor 12 is executing an operation (step S302: Yes), the operation flag 133
Is set to "under calculation" (step S30).
3). After executing step S303, or when the operation of the processor 12 ends (step S302: N
o), the processor 12 transmits an instruction command for reading image data from the main storage device 13 to the memory access unit 141 of the input / output channel 14, and the memory access unit 141 receives the command (step S304).

The memory access unit 141 that has received the read instruction command from the processor 12 interprets the read instruction command and instructs the main storage device 13 to read image data (step S305).

Address setting section 132 of main storage device 13
Checks the flag of the operation flag 133. Then, when the flag of the calculation flag 133 indicates that the processor 12 is “calculating” (step S306:
Yes), the address setting unit 132 instructs the memory unit 131 of discrete addresses for reading out image data based on a preset displacement of the address of one line of image data to be skipped (step S307).
On the other hand, when the flag of the operation flag 133 indicates that the processor 12 is not performing the operation (operation is completed) (step S306: No), the address setting unit 1
32 instructs the memory unit 131 of a continuous address as a read address (step S308).

The memory unit 131 includes an address setting unit 132
The image data is read out from the address specified in the step (1) and transmitted to the input / output channel 14 (step S30).
9). The input / output channel 14 receives the image data transmitted from the main storage device 13 and transfers the received image data to the data buffer 14.
2 (step S310).

The transfer control unit 143 monitors the interface with the image processing device 16 to synchronize the transfer operation,
When it is determined that the data transfer is possible, the image data is transferred from the data buffer 142 to the image processing device 16 (step S311). The image processing device 16 receives the image data transferred from the input / output channel 14 (step S312), converts the received image data into a signal that can be displayed on a display or the like, and displays an image (step S313). The above is the procedure of the transfer processing of the image data generated as a result of the operation of the processor 12.

FIG. 4 shows the image processing system 1 described above.
Is a time table showing the processing states of the processor 12, the main storage device 13, and the input / output channel 14 of FIG. Referring to FIG. 4, after the processor 12 executes the arithmetic processing to generate the image data, the main storage device 13 stores the image data generated by the processor 12 in the memory unit 131. During this time, the main storage device 13 is being accessed by the processor 12. On the other hand, while the processor 12 suspends the operation (during the WAIT state), the main storage device 13 is in an access state by the input / output channel 14, and the input / output channel 14 is the image data stored in the main storage device 53. Are alternately read and skipped every fixed amount, here, every 1280 bytes corresponding to one line of the image.
If the operation of the processor 12 has been completed, the stored image data is read from the main storage device 53 without skipping.

As described above, according to the image processing system 1 according to the present embodiment, even if the processor 12 interrupts the operation during the execution of the operation by the processor 12, the input / output channel 14 Since the transfer is performed by skipping the stored image data, the interruption time of the operation of the processor 12 can be reduced as compared with the case where the reading is performed from the continuous address without skipping.

[0026]

As is apparent from the above description, according to the data transfer method of the present invention, when the processor suspends the operation and stores the image data as the operation result in the memory, the data is stored in the memory. Since a part of the image data is skipped and the transfer of the skipped part is omitted, there is a specific effect that the operation interruption time of the processor can be reduced.

[Brief description of the drawings]

FIG. 1 is a functional block configuration diagram of an image processing system according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a specific example of a skipping process according to the embodiment;

FIG. 3 is an explanatory diagram of a processing procedure according to the embodiment.

FIG. 4 is a view showing a time table of a transfer process according to the embodiment;

FIG. 5 is a block diagram of a conventional image processing system.

FIG. 6 is an explanatory diagram of a processing procedure in a conventional image processing system.

FIG. 7 is a diagram showing a time table of a transfer process in a conventional image processing system.

[Explanation of symbols]

 1, 5 Image processing system 11, 51 Computer system 12, 52 Processor 13, 53 Main storage device 14, 54 Input / output channel 15, 55, 134, 144, 545 System bus 16, 56 Image processing device 131 Memory section 132 Address setting Unit 133 Operation flag 141, 541 Memory access unit 142, 543 Data buffer 143, 542 Transfer control unit 544 Data transfer unit

Claims (2)

[Claims] A memory for storing image data generated by an operation of a processor; a memory control means for alternately storing and reading the generated image data in the memory; Means for transferring the generated image data to the memory each time the memory control means stores flag information indicating whether the processor at the time is performing the calculation or ending the calculation. In addition, when reading out the stored image data, if the flag information when the image data is stored in the memory indicates that the calculation is being performed, the image data is partially skipped. Data transfer method. 2. The image processing apparatus according to claim 1, wherein when the flag information at the time when the image data is stored indicates that the image data is being calculated, a predetermined amount of image data is read from a head address of an area where the image data is stored. 2. The data transfer method according to claim 1, wherein the reading and the skipping are alternately repeated.