JPH1056092A - Semiconductor case - Google Patents
Semiconductor caseInfo
- Publication number
- JPH1056092A JPH1056092A JP8211071A JP21107196A JPH1056092A JP H1056092 A JPH1056092 A JP H1056092A JP 8211071 A JP8211071 A JP 8211071A JP 21107196 A JP21107196 A JP 21107196A JP H1056092 A JPH1056092 A JP H1056092A
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- Prior art keywords
- pedestal
- semiconductor
- substrate
- thermal expansion
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体容器に係り、
特に高周波数帯高出力トランジスタ用半導体容器に関す
る。TECHNICAL FIELD The present invention relates to a semiconductor container,
In particular, it relates to a semiconductor container for a high-frequency band high-output transistor.
【０００２】[0002]
【従来の技術】従来の半導体容器は、半導体チップ、イ
ンピーダンス整合回路基板、チップコンデンサといった
半導体回路をマウントする台座部と、ヒートシンクを考
慮した放熱板と、半導体回路を囲む側壁部で構成されて
いる。すなわち、図３（Ａ）に示した従来の半導体容器
では、台座部と放熱板とが銅（Ｃｕ）により一体形成で
形成されて放熱板兼台座３を構成しており、この放熱板
兼台座３上にセラミック材又はＣｕ材の側壁部６が接着
され、また放熱板兼台座３上に例えばＧａＡｓからなる
半導体チップ１、セラミック等からなるインピーダンス
整合回路基板２等がマウントされている。2. Description of the Related Art A conventional semiconductor container includes a pedestal for mounting a semiconductor circuit such as a semiconductor chip, an impedance matching circuit board, and a chip capacitor, a heat sink in consideration of a heat sink, and a side wall surrounding the semiconductor circuit. . That is, in the conventional semiconductor container shown in FIG. 3A, the pedestal portion and the radiator plate are integrally formed of copper (Cu) to constitute the radiator plate / pedestal 3. A ceramic or Cu side wall 6 is adhered on the substrate 3, and a semiconductor chip 1 made of, for example, GaAs, an impedance matching circuit board 2 made of ceramic or the like are mounted on the radiator plate 3.
【０００３】図３（Ｂ）は従来の半導体容器の他の例の
断面図を示す。この半導体容器は、放熱板と台座が別々
に構成されている。Ｃｕ材により構成された放熱板４の
上に設けられた台座５はマウントする材料の熱膨張率に
近いと材料で形成され、銅−タングステン焼結体（Ｃｕ
Ｗ）等で構成されており、その上に半導体チップ１、イ
ンピーダンス整合回路基板２等がマウントされている。FIG. 3B is a sectional view of another example of a conventional semiconductor container. In this semiconductor container, a radiator plate and a pedestal are separately configured. The pedestal 5 provided on the heat radiating plate 4 made of Cu material is formed of a material having a coefficient of thermal expansion close to that of the mounting material, and is made of a copper-tungsten sintered body (Cu
W) and the like, on which the semiconductor chip 1, the impedance matching circuit board 2 and the like are mounted.
【０００４】[0004]
【発明が解決しようとする課題】しかるに、上記の図３
（Ａ）に死した半導体容器では、半導体チップ１、イン
ピーダンス整合回路基板２等を金・錫共晶ろう等のソル
ダによりマウントする際に生ずる熱応力、あるいはマウ
ント後に熱ショック試験等を行った際の熱応力により、
半導体チップ１、インピーダンス整合回路基板２等にク
ラックが入るという問題がある。However, FIG.
In the semiconductor container that died in (A), the thermal stress generated when the semiconductor chip 1, the impedance matching circuit board 2 and the like were mounted by a solder such as gold / tin eutectic solder, or when a thermal shock test or the like was performed after mounting. Due to the thermal stress of
There is a problem that cracks occur in the semiconductor chip 1, the impedance matching circuit board 2, and the like.
【０００５】その理由は、放熱板兼台座３として用いら
れるＣｕ材の熱膨張率は約１７．０×１０-6℃-1であ
り、半導体チップ１の材料であるガリウム−砒素（Ｇａ
Ａｓ）の熱膨張率６．０×１０-6℃-1やインピーダンス
整合回路基板２の材料であるセラミック材の熱膨張率
６．７×１０-6℃-1に比べて２〜３倍程度大きいためで
ある。[0005] The reason is that the Cu material used as the radiator plate / pedestal 3 has a coefficient of thermal expansion of about 17.0 × 10 −6 ° C. −1 , and the material of the semiconductor chip 1 is gallium-arsenic (Ga).
As), the thermal expansion coefficient is about 6.0 × 10 −6 ° C. −1 or about 2 to 3 times that of the ceramic material 6.7 × 10 −6 ° C. −1 which is the material of the impedance matching circuit board 2. Because it is big.
【０００６】また、図３（Ｂ）に示した従来の半導体容
器では、上記のクラックの問題は生じないものの、放熱
板４の裏面に大きな反りを生ずる。このため、放熱板４
の裏面からの熱放散性に問題がある。その理由は、台座
５の材料であるＣｕＷ材の熱膨張率は６．０×１０-6℃
-1であり、熱膨張率が約１７．０×１０-6℃-1であるＣ
ｕ材からなる放熱板４との貼り合わせの際にそれらの熱
膨張率の差により反りを生じるためである。実験の結
果、約１０ｍｍ角、厚さ２ｍｍの銅板と、同じく約１０
ｍｍ角、厚さ０．５ｍｍのＣｕＷ板を貼り合わせた場合
には最大約６０μｍの反りを生じた。Further, in the conventional semiconductor container shown in FIG. 3B, the above-described problem of the crack does not occur, but the back surface of the heat sink 4 is greatly warped. Therefore, the heat sink 4
There is a problem in heat dissipation from the back surface of the glass. The reason is that the thermal expansion coefficient of the CuW material as the material of the pedestal 5 is 6.0 × 10 -6 ° C.
-1 and a coefficient of thermal expansion of about 17.0 × 10 −6 ° C. −1
This is because warpage occurs due to a difference in the coefficient of thermal expansion between the heat radiating plate 4 and the heat radiating plate 4 made of a u material. As a result of the experiment, a copper plate of about 10 mm square and 2 mm thick and about 10 mm
When a CuW plate having a square shape of 0.5 mm and a thickness of 0.5 mm was bonded, a maximum warpage of about 60 μm occurred.
【０００７】更に、図３（Ｂ）に示した従来の半導体容
器では、ワイヤボンディングの自動化が困難である。そ
の理由は、半導体チップ１の表面に有するボンディング
パッドと、インピーダンス整合回路基板２等の表面のボ
ンディングパッドとの間に、４００μｍ以上の段差が生
じるため、ボンディングワイヤをボンディング自動機で
行う際に、機械の制限でボンディングできない場合が生
じるからである。Further, in the conventional semiconductor container shown in FIG. 3B, it is difficult to automate wire bonding. The reason is that a step of 400 μm or more occurs between the bonding pad on the surface of the semiconductor chip 1 and the bonding pad on the surface of the impedance matching circuit board 2 or the like. This is because bonding may not be possible due to mechanical limitations.
【０００８】本発明は以上の点に鑑みなされたもので、
熱ストレスに対する信頼度が高く、しかも生産性の高い
半導体容器を提供することを目的とする。[0008] The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor container having high reliability against thermal stress and high productivity.
【０００９】[0009]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は放熱板上に台座を介して半導体回路を構成
する回路部品及び基板をマウントすると共に、半導体回
路を囲む側壁部を放熱板上に設けた構成の半導体容器に
おいて、台座を、回路部品及び基板のうち熱膨張率の異
なる回路部品及び基板毎に専用に設け、かつ、マウント
する回路部品又は基板の熱膨張率と近似した熱膨張率の
材料で構成したものである。In order to achieve the above object, the present invention mounts circuit components and a substrate constituting a semiconductor circuit on a radiator plate via a pedestal, and radiates a side wall surrounding the semiconductor circuit. In a semiconductor container having a configuration provided on a board, a pedestal is provided exclusively for each of circuit components and substrates having different coefficients of thermal expansion among circuit components and substrates, and approximates the coefficient of thermal expansion of the mounted circuit component or substrate. It is made of a material having a coefficient of thermal expansion.
【００１０】この発明では、台座にマウントする際にソ
ルダにより生じる熱応力、あるいはマウント後の熱ショ
ック試験等の熱環境試験による熱応力に対し、台座とそ
の上にマウントされる回路部品又は基板との熱膨張率の
差が小さいため、熱ストレスが単一材料で形成された単
一の台座よりも小さくできる。According to the present invention, the pedestal and a circuit component or board mounted thereon are protected against thermal stress generated by solder when mounting the pedestal or thermal stress caused by a thermal environment test such as a thermal shock test after mounting. Since the difference in the coefficient of thermal expansion between the pedestals is small, the thermal stress can be made smaller than that of a single pedestal formed of a single material.
【００１１】また、本発明における熱膨張率の異なる回
路部品及び基板毎に専用に設けられた台座は、それぞれ
マウントされる回路部品又は基板の寸法と同一の寸法で
形成されるため、各専用台座と放熱板との貼り合わせ面
積を減少できる。In the present invention, the pedestals provided exclusively for the circuit components and substrates having different coefficients of thermal expansion are formed in the same dimensions as the dimensions of the circuit components or the substrates to be mounted. And the heat radiation plate can reduce the bonding area.
【００１２】また、本発明における熱膨張率の異なる回
路部品及び基板毎に専用に設けられた台座は、マウント
する回路部品が有するボンディングパッド面とマウント
する基板が有するボンディングパッド面とが互いに同一
平面上に位置するように、熱膨張率の異なる回路部品及
び基板の各厚さに対応して厚さが設定されて形成されて
いることを特徴とする。Further, in the present invention, the pedestal provided exclusively for the circuit component having a different coefficient of thermal expansion and the substrate has a bonding pad surface of the circuit component to be mounted and a bonding pad surface of the substrate to be mounted on the same plane. As described above, the thickness is set so as to correspond to each thickness of the circuit component and the substrate having different coefficients of thermal expansion.
【００１３】また、本発明では、専用台座をマウントす
る回路部品又は基板の材料の熱膨張率を考慮した材料で
個々に選択でき、また、マウントする回路部品又は基板
の寸法変更に合わせて台座の寸法変更ができる。Further, according to the present invention, the dedicated pedestal can be individually selected from materials in consideration of the coefficient of thermal expansion of the material of the circuit component or the substrate on which the pedestal is mounted. Dimensions can be changed.
【００１４】また、本発明における放熱板は、半導体チ
ップがマウントされる第１の台座が設けられる部分が、
インピーダンス整合回路基板がマウントされる第２の台
座が設けられる部分に対して第２の台座の厚さよりも高
い断面凸形状であることを特徴とする。これにより、第
２の台座を放熱板に設ける際に放熱板の凸部の側面を位
置決めに利用できる。Further, in the heat radiation plate according to the present invention, the portion where the first pedestal on which the semiconductor chip is mounted is provided,
It is characterized in that it has a convex cross section higher than the thickness of the second pedestal with respect to the portion where the second pedestal on which the impedance matching circuit board is mounted is provided. Accordingly, when the second pedestal is provided on the heat sink, the side surface of the convex portion of the heat sink can be used for positioning.
【００１５】[0015]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００１６】図１は本発明になる半導体容器の第１の実
施の形態の断面図を示す。同図中、図３（Ｂ）と同一構
成部分には同一符号を付してある。図１に示すように、
この半導体容器は、Ｃｕ材による放熱板４の上にチップ
台座７と基板台座８とを設け、チップ台座７の上に表面
にボンディングパッドを有する半導体チップ１をマウン
トし、基板台座８の上に表面にボンディングパッドやス
トリップラインで構成される電気回路配線を有するイン
ピーダンス整合回路基板２等をマウントする構成とされ
ている。また、チップ台座７及び基板台座８及びそれら
の上にマウントされた半導体回路の周囲に側壁部６が設
けられている。これらの半導体チップ１及びインピーダ
ンス整合回路基板２等からなる半導体回路は、高周波数
帯用の高出力トランジスタを構成している。FIG. 1 is a sectional view of a first embodiment of a semiconductor container according to the present invention. In the figure, the same components as those in FIG. 3 (B) are denoted by the same reference numerals. As shown in FIG.
In this semiconductor container, a chip pedestal 7 and a substrate pedestal 8 are provided on a radiator plate 4 made of a Cu material, and the semiconductor chip 1 having a bonding pad on the surface is mounted on the chip pedestal 7. The configuration is such that the impedance matching circuit board 2 having an electric circuit wiring composed of bonding pads and strip lines on its surface is mounted. A side wall 6 is provided around the chip pedestal 7 and the substrate pedestal 8 and the semiconductor circuit mounted thereon. A semiconductor circuit including the semiconductor chip 1 and the impedance matching circuit board 2 constitutes a high-output transistor for a high frequency band.
【００１７】ここで、上記のチップ台座７はＧａＡｓ材
による半導体チップ１とほぼ同等の熱膨張率を持つ材
料、例えばＣｕＷ材により構成されている。また、基板
台座８は、セラミック材によるインピーダンス整合回路
基板２とほぼ同等の熱膨張率を持つ、例えばＭｏ材、Ｃ
ｕＷ材等により構成されている。なお、熱膨張率は、Ｃ
ｕが約１７．０×１０-6℃-1、ＣｕＷが約６．０×１０
-6℃-1、Ｍｏが約５．１×１０-6℃-1、ＧａＡｓが約
６．０×１０-6℃-1、セラミック（Ａｉ2Ｏ3）で約６．
７×１０-6℃-1である。The chip pedestal 7 is made of a material having a thermal expansion coefficient substantially equal to that of the semiconductor chip 1 made of GaAs, for example, CuW. The substrate pedestal 8 has a thermal expansion coefficient substantially equal to that of the impedance matching circuit substrate 2 made of a ceramic material.
It is made of uW material or the like. The coefficient of thermal expansion is C
u is about 17.0 × 10 −6 ° C. −1 , and CuW is about 6.0 × 10 -6
-6 ° C. -1, Mo is about 5.1 × 10 -6 ℃ -1, GaAs is about 6.0 × 10 -6 ℃ -1, about ceramic (Ai 2 O 3) 6.
7.times.10.sup.-6.degree. C.- 1 .
【００１８】例えば、ＣｕＷ材で形成されたチップ台座
７にＧａＡｓ材の半導体チップ１をマウントし、Ｍｏ材
で形成された基板台座８にセラミック材のインピーダン
ス整合回路基板２をマウントした場合、Ｃｕ単一材質で
形成された台座にマウントした場合に比べて、互いの熱
膨張率の差が小さいため、熱ストレスによって生じる半
導体チップ１やインピーダンス整合回路基板２等のクラ
ックの発生を低減でき、よって容器の信頼度を向上でき
ると共に、製造工程における歩留りが向上し、生産性が
向上する。これは容器が大きく、チップ台座７、基板台
座８と半導体チップ１、インピーダンス整合回路基板２
との接触面積が大きい場合に特に有効である。For example, when a semiconductor chip 1 made of a GaAs material is mounted on a chip pedestal 7 made of a CuW material and an impedance matching circuit board 2 made of a ceramic material is mounted on a substrate pedestal 8 made of a Mo material, Since the difference in the coefficient of thermal expansion between them is smaller than when mounted on a pedestal made of one material, the occurrence of cracks in the semiconductor chip 1 and the impedance matching circuit board 2 caused by thermal stress can be reduced. Can be improved, the yield in the manufacturing process can be improved, and the productivity can be improved. This is a large container, chip pedestal 7, substrate pedestal 8 and semiconductor chip 1, impedance matching circuit board 2
This is particularly effective when the contact area with the substrate is large.
【００１９】また、この際、半導体チップ１及びインピ
ーダンス整合回路基板２等の寸法に合わせて、チップ台
座７及び基板台座８個々の寸法を決定し、できるだけ放
熱板４との貼り合わせ面積を減少させることで、放熱板
４とチップ台座７及び基板台座８との熱膨張率の差によ
って生じる反りが低減でき、よって、熱環境に対し安定
な高周波数体用高出力トランジスタの容器が得られる。
これは容器が大きく、チップ台座７、基板台座８と半導
体チップ１、インピーダンス整合回路基板２との接触面
積が小さい場合に特に有効である。At this time, the dimensions of each of the chip pedestal 7 and the substrate pedestal 8 are determined in accordance with the dimensions of the semiconductor chip 1 and the impedance matching circuit board 2 and the like, and the bonding area with the heat sink 4 is reduced as much as possible. As a result, the warpage caused by the difference in the coefficient of thermal expansion between the radiator plate 4 and the chip pedestal 7 and the substrate pedestal 8 can be reduced, so that a high-frequency transistor high-power transistor container that is stable in a thermal environment can be obtained.
This is particularly effective when the container is large and the contact area between the chip pedestal 7 and the substrate pedestal 8 and the semiconductor chip 1 and the impedance matching circuit board 2 is small.
【００２０】また、チップ台座７及び基板台座８の各厚
さを、それらの上にマウントされる半導体チップ１、イ
ンピーダンス整合回路基板２等の有するボンディングパ
ッド面が同一平面となるように、個々に形成すること
で、ワイヤボンディングを容易、かつ、確実に行える。
これはボンディング作業を自動機にて行う際、機械のボ
ンディングパッド面の段差によるボンディング能力の限
界を補償し、特に有効であり、このことにより、組立歩
留りが向上するために生産性が向上する。The thickness of the chip pedestal 7 and the thickness of the substrate pedestal 8 are individually adjusted so that the bonding pad surfaces of the semiconductor chip 1, the impedance matching circuit board 2 and the like mounted thereon are coplanar. By forming them, wire bonding can be performed easily and reliably.
This is particularly effective when the bonding operation is performed by an automatic machine, by compensating for the limit of the bonding ability due to the step of the bonding pad surface of the machine, thereby improving the assembly yield and improving the productivity.
【００２１】また、チップ台座７と基板台座８の材料を
個々に選択することにより、例えばチップ台座７は半導
体チップ１のクラックを防止するＣｕＷ材で、基板台座
８はインピーダンス整合回路基板２のクラックを防止す
るＭｏ材とすることにより、加工が困難なＣｕＷ材のみ
の台座を用いる場合に比べて安価に構成でき、生産性を
向上できる。By individually selecting the materials of the chip pedestal 7 and the substrate pedestal 8, for example, the chip pedestal 7 is a CuW material for preventing cracking of the semiconductor chip 1, and the substrate pedestal 8 is formed of a crack of the impedance matching circuit board 2. By using a Mo material that prevents the occurrence of the above problem, it is possible to configure at a lower cost and improve productivity as compared with a case where a pedestal made of only a CuW material, which is difficult to process, is used.
【００２２】更に、半導体チップ１及びインピーダンス
整合回路基板２等に対して専用のチップ台座７、基板台
座８を側壁部６を有する放熱板４に被着しているため、
例えば周波数の異なる製品展開等の際の半導体チップ
１、インピーダンス整合回路基板２等の設計寸法の変更
に合わせてチップ台座７、基板台座８の寸法を個々に変
更することで同一放熱板を使用でき、よってこれまでの
製品毎に異なる容器を使用していた場合に比べて安価に
容器を製造、入手でき、生産性が向上する。Further, since the chip pedestal 7 and the substrate pedestal 8 dedicated to the semiconductor chip 1 and the impedance matching circuit board 2 are attached to the heat radiating plate 4 having the side wall 6,
For example, the same heat sink can be used by individually changing the dimensions of the chip pedestal 7 and the substrate pedestal 8 in accordance with a change in the design dimensions of the semiconductor chip 1, the impedance matching circuit board 2 and the like when developing products having different frequencies. Therefore, compared to the case where a different container is used for each product, the container can be manufactured and obtained at lower cost, and the productivity is improved.
【００２３】次に、本発明の第２の実施の形態について
説明する。図２は本発明になる半導体容器の第１の実施
の形態の断面図を示す。同図中、図１と同一構成部分に
は同一符号を付し、その説明を省略する。図２に示すよ
うに、この容器は、チップ台座７が設けられる部分が、
基板台座８が設けられる部分に対して基板台座８の厚さ
よりも高い断面凸形状の放熱板９を有する点に特徴があ
る。Next, a second embodiment of the present invention will be described. FIG. 2 shows a sectional view of a first embodiment of the semiconductor container according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 2, this container has a portion where the chip pedestal 7 is provided,
It is characterized in that a heat radiating plate 9 having a convex cross section higher than the thickness of the substrate pedestal 8 is provided at a portion where the substrate pedestal 8 is provided.
【００２４】この実施の形態によれば、第１の実施の形
態と同様のチップ台座７及び基板台座８を有するため
に、第１の実施の形態と同様の効果を有すると共に、更
に基板台座８を放熱板９に接着するときに、放熱板９の
凸部の側壁を利用して位置決めできるため、位置精度良
く接着できるという効果も有する。According to this embodiment, since the same chip pedestal 7 and substrate pedestal 8 as in the first embodiment are provided, the same effects as in the first embodiment are obtained, and further, the substrate pedestal 8 is provided. Can be positioned using the side wall of the convex portion of the heat radiating plate 9 when bonding the heat radiating plate 9 to the heat radiating plate 9.
【００２５】[0025]
【発明の効果】以上説明したように、本発明によれば、
放熱板上の台座を、台座にマウントされる回路部品又は
基板との熱膨張率を考慮してマウントされる回路部品又
は基板個々に、すなわち専用に設けるようにしたため、
以下の数々の特長を有する。As described above, according to the present invention,
Because the pedestal on the heat sink is provided individually for the circuit component or board mounted in consideration of the coefficient of thermal expansion with the circuit component or board mounted on the pedestal, that is, for exclusive use,
It has the following features.
【００２６】（１）台座とマウントされる回路部品又は
基板との熱膨張率の差が小さく、熱ストレスが単一材料
で形成された単一の台座よりも小さくできるため、熱環
境下での回路部品、基板等のクラックの発生を低減でき
ることから、製造工程における歩留りの向上により生産
性を向上でき、しかも上記のクラックの発生の低減と共
に放熱板裏面に反りも低減できるため、熱環境に対し高
信頼度の半導体容器が得られる。(1) The difference in the coefficient of thermal expansion between the pedestal and the mounted circuit component or substrate is small, and the thermal stress can be made smaller than that of a single pedestal formed of a single material. Since the occurrence of cracks in circuit components, substrates, etc. can be reduced, productivity can be improved by improving the yield in the manufacturing process, and in addition to the above-mentioned reduction in occurrence of cracks, warpage on the back side of the radiator plate can be reduced. A highly reliable semiconductor container can be obtained.
【００２７】（２）熱膨張率の異なる回路部品及び基板
毎に専用に設けられた台座は、それぞれマウントされる
回路部品又は基板の寸法と同一の寸法で形成されること
で、各専用台座と放熱板との貼り合わせ面積を減少する
ようにしたため、熱膨張率の差によって生じる放熱板裏
面の反りを殆ど生じないようにでき、より一層熱環境に
対し高信頼度の半導体容器が得られる。(2) The pedestals provided exclusively for the circuit components and the substrates having different coefficients of thermal expansion are formed in the same dimensions as the dimensions of the circuit components or the substrates to be mounted, respectively. Since the bonding area with the heat radiating plate is reduced, the back surface of the heat radiating plate, which is caused by the difference in the coefficient of thermal expansion, can be hardly warped, so that a semiconductor container having higher reliability in a thermal environment can be obtained.
【００２８】（３）熱膨張率の異なる回路部品及び基板
毎に専用に設けられた台座の厚さの設定により、マウン
トする回路部品が有するボンディングパッド面とマウン
トする基板が有するボンディングパッド面とが互いに同
一平面上に位置するようにされるため、ボンディング自
動機によるボンディング作業が容易に、かつ、確実にで
き、ボンディング自動化及び組立歩留りの向上により生
産性が向上する。(3) By setting the thickness of the pedestal provided exclusively for each circuit component having a different coefficient of thermal expansion and each substrate, the bonding pad surface of the circuit component to be mounted and the bonding pad surface of the substrate to be mounted are changed. Since they are located on the same plane, the bonding operation by the automatic bonding machine can be performed easily and reliably, and the productivity is improved by the automatic bonding and the improvement of the assembly yield.
【００２９】（４）専用台座をマウントする回路部品又
は基板の材料の熱膨張率を考慮した材料で個々に選択で
きるため、加工が困難な材料を用いずに台座を形成で
き、安価に構成できると共に生産性を向上することがで
きる。(4) Since it is possible to individually select a circuit component for mounting the dedicated pedestal or a material in consideration of the coefficient of thermal expansion of the material of the substrate, the pedestal can be formed without using a material which is difficult to process, and the cost can be reduced. At the same time, productivity can be improved.
【００３０】（５）台座が個々に形成されているため、
使用周波数の異なる製品展開等の際のマウントする回路
部品又は基板の寸法変更に合わせて台座の寸法変更がで
き、同一の放熱板を使用でき、製品毎に異なる容器を製
造・使用するよりも、同一容器の大量製造・使用ができ
ることから安価に容器を製造・入手でき、生産性を向上
できる。(5) Since the pedestals are individually formed,
The dimensions of the pedestal can be changed according to the dimensions of the circuit components or boards to be mounted when developing products with different operating frequencies, etc., the same radiator plate can be used, and rather than manufacturing and using different containers for each product, Since the same container can be mass-produced and used, containers can be manufactured and obtained at low cost, and productivity can be improved.
【００３１】（６）放熱板の半導体チップがマウントさ
れる第１の台座が設けられる部分が、インピーダンス整
合回路基板がマウントされる第２の台座が設けられる部
分に対して第２の台座の厚さよりも高い断面凸形状とす
ることにより、第２の台座を放熱板に設ける際に放熱板
の凸部の側面を位置決めに利用できるため、位置精度良
く第２の台座を放熱板上に固定でき、生産性を向上でき
る。(6) The portion of the heat sink on which the first pedestal on which the semiconductor chip is mounted is provided is thicker than the portion on which the second pedestal on which the impedance matching circuit board is mounted is provided. When the second base is provided on the heat sink, the side surface of the protrusion of the heat sink can be used for positioning when the second base is provided on the heat sink, so that the second base can be fixed on the heat sink with high positional accuracy. , Productivity can be improved.
【図１】本発明の第１の実施の形態の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of the present invention.
【図２】本発明の第２の実施の形態の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図３】従来の各例の断面図である。FIG. 3 is a cross-sectional view of each conventional example.
１ 半導体チップ ２ インピーダンス整合回路基板 ４ 放熱板 ６ 側壁部 ７ チップ台座 ８ 基板台座 ９ 放熱板 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Impedance matching circuit board 4 Heat sink 6 Side wall part 7 Chip base 8 Board base 9 Heat sink
Claims (5)
成する回路部品及び基板をマウントすると共に、前記半
導体回路を囲む側壁部を前記放熱板上に設けた構成の半
導体容器において、 前記台座を、前記回路部品及び基板のうち熱膨張率の異
なる回路部品及び基板毎に専用に設け、かつ、マウント
する回路部品又は基板の熱膨張率と近似した熱膨張率の
材料で構成したことを特徴とする半導体容器。1. A semiconductor container having a circuit board and a circuit component constituting a semiconductor circuit mounted on a radiator plate via a pedestal, and a side wall surrounding the semiconductor circuit provided on the radiator plate. Is provided exclusively for each circuit component and substrate having a different coefficient of thermal expansion among the circuit components and the substrate, and is made of a material having a coefficient of thermal expansion similar to that of the mounted circuit component or substrate. Semiconductor container.
毎に専用に設けられた台座は、マウントする回路部品が
有するボンディングパッド面とマウントする基板が有す
るボンディングパッド面とが互いに同一平面上に位置す
るように、前記熱膨張率の異なる回路部品及び基板の各
厚さに対応して厚さが設定されて形成されていることを
特徴とする請求項１記載の半導体容器。2. A pedestal provided exclusively for each of the circuit components having different coefficients of thermal expansion and the substrate, wherein the bonding pad surface of the mounted circuit component and the bonding pad surface of the mounted substrate are on the same plane. 2. The semiconductor container according to claim 1, wherein the semiconductor container is formed so as to have a thickness corresponding to each thickness of the circuit component and the substrate having different coefficients of thermal expansion.
毎に専用に設けられた台座は、それぞれマウントされる
回路部品又は基板の寸法と同一の寸法で形成されている
ことを特徴とする請求項１記載の半導体容器。3. The circuit component having a different coefficient of thermal expansion and a pedestal provided exclusively for each substrate are formed to have the same dimensions as the dimensions of the mounted circuit component or substrate. Item 7. A semiconductor container according to Item 1.
は、少なくとも半導体チップとインピーダンス整合回路
基板であることを特徴とする請求項１乃至３のうちいず
れか一項記載の半導体容器。4. The semiconductor container according to claim 1, wherein the circuit components and the substrates having different coefficients of thermal expansion are at least a semiconductor chip and an impedance matching circuit substrate.
ントされる第１の台座が設けられる部分が、前記インピ
ーダンス整合回路基板がマウントされる第２の台座が設
けられる部分に対して該第２の台座の厚さよりも高い断
面凸形状であることを特徴とする請求項４記載の半導体
容器。5. The radiator plate according to claim 1, wherein a portion on which the first pedestal on which the semiconductor chip is mounted is provided, and a portion on which the second pedestal on which the impedance matching circuit board is mounted is provided on the second side. 5. The semiconductor container according to claim 4, wherein the cross section is higher than the thickness of the pedestal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21107196A JP2833592B2 (en) | 1996-08-09 | 1996-08-09 | Semiconductor container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21107196A JP2833592B2 (en) | 1996-08-09 | 1996-08-09 | Semiconductor container |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1056092A true JPH1056092A (en) | 1998-02-24 |
| JP2833592B2 JP2833592B2 (en) | 1998-12-09 |
Family
ID=16599933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21107196A Expired - Fee Related JP2833592B2 (en) | 1996-08-09 | 1996-08-09 | Semiconductor container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2833592B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008192655A (en) * | 2007-01-31 | 2008-08-21 | Kyocera Corp | Multiple wiring base mount, wiring base mount and electronic device, and method for dividing multiple wiring base mount |
| JP2010027953A (en) * | 2008-07-23 | 2010-02-04 | Mitsubishi Electric Corp | Semiconductor device |
| JP2016208766A (en) * | 2015-04-27 | 2016-12-08 | 株式会社デンソー | Controller-integrated dynamo-electric machine |
| JP2021019149A (en) * | 2019-07-23 | 2021-02-15 | 三菱電機株式会社 | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH053265A (en) * | 1990-10-26 | 1993-01-08 | Sumitomo Electric Ind Ltd | Complex heatsing for semiconductor loading and its manufacture |
| JPH05206306A (en) * | 1992-01-29 | 1993-08-13 | Nec Corp | High-power transistor vessel for high-frequency band |
-
1996
- 1996-08-09 JP JP21107196A patent/JP2833592B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH053265A (en) * | 1990-10-26 | 1993-01-08 | Sumitomo Electric Ind Ltd | Complex heatsing for semiconductor loading and its manufacture |
| JPH05206306A (en) * | 1992-01-29 | 1993-08-13 | Nec Corp | High-power transistor vessel for high-frequency band |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008192655A (en) * | 2007-01-31 | 2008-08-21 | Kyocera Corp | Multiple wiring base mount, wiring base mount and electronic device, and method for dividing multiple wiring base mount |
| JP2010027953A (en) * | 2008-07-23 | 2010-02-04 | Mitsubishi Electric Corp | Semiconductor device |
| JP2016208766A (en) * | 2015-04-27 | 2016-12-08 | 株式会社デンソー | Controller-integrated dynamo-electric machine |
| JP2021019149A (en) * | 2019-07-23 | 2021-02-15 | 三菱電機株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2833592B2 (en) | 1998-12-09 |
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