JPH1056068A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve wiring efficiency, by wiring the clock main line in the wiring layer, which is electrically insulated from a signal wiring layer, on a clock pin for applying a clock signal, and electrically connecting the clock pin and the clock main line. SOLUTION: In a semiconductor integrated circuit device 1, the clock signal from the outside is applied on a clock input pin 3 of the semiconductor integrated circuit device 1, amplified in a clock driver 4, applied on a clock pin 6 arranged on a signal wiring layer through a through hole, which is provided on each cell 2 on a clock main line 5 arranged on a special clock wiring layer, and inputted into the gate electrode of the cell 2 requiring the distribution of the clock from the gate connecting through hole. Since the clock main line 5 is wired on the special clock wiring layer, the wiring efficiency does not become worse by the obstruction of the clock main line 5 on the other wiring, and the wiring to a spot directly above each cell 2 becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having cells that require clock distribution.

[0002]

2. Description of the Related Art FIG. 4 is a schematic plan view showing a conventional semiconductor integrated circuit device having cells requiring clock distribution. In the figure, 1 is a semiconductor integrated circuit device, 2 is a cell requiring clock distribution, 3 is a clock input pin to which an external clock signal is applied, and 4 is a clock signal for an internal cell 2 for an external clock signal. A clock driver for transmitting the clock signal from the clock driver 3 to each part of the semiconductor integrated circuit device 1; a clock pin 6 to which a clock signal for each cell 2 is applied; This is a branch wiring to each clock pin 6.

A conventional semiconductor integrated circuit device is configured as described above. A clock signal from the outside is applied to a clock input pin 3 of the semiconductor integrated circuit device 1 and is amplified by a clock driver 3 to form a clock main line 5. And branch wiring 7
Is applied to the clock pin 6 of each cell 2 requiring clock distribution.

[0004]

In the semiconductor integrated circuit device as described above, the clock trunk line 5 is formed on the same wiring layer as the clock pin 6 of each cell 2 and other signal wirings, as is generally done in the prior art. When formed, the clock main line 5 hinders signal wiring and wiring efficiency is reduced, and it is necessary to connect the clock main line 5 to each clock pin 6 via the branch wiring 7. There is a problem that the skew value increases depending on the wiring length.

In order to prevent this, for example, Japanese Patent Application Laid-Open
As disclosed in -273203 and JP-A-5-267625, it has been proposed to wire a clock main line to a layer different from the signal wiring layer and close to the semiconductor circuit layer. However, the clock trunk 5 is connected to each cell 2
In this case, it is necessary to provide the branch wiring 7 and the skew value increases accordingly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. It is possible to improve the wiring efficiency without hindering other signal wirings, and it is not necessary to provide branch wirings, and the skew is reduced. It is an object of the present invention to obtain a semiconductor integrated circuit device in which clock trunk lines are wired so as to lower the value.

[0007]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having cells that require clock distribution, wherein a dedicated wiring electrically insulated from a general signal wiring layer is provided. A clock trunk in a layer is wired on a clock pin for applying a clock signal of a cell requiring the clock distribution, and these clock pins and the clock trunk are electrically connected via through holes.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 3 show an embodiment of the present invention. FIG. 1 is a schematic plan view, FIG. 2 is a partially enlarged plan view of a portion A of FIG. 1A, and FIG. 3 is a partially enlarged view taken along line BB of FIG. It is sectional drawing. In the figure, 1 is a semiconductor integrated circuit device, 2 is a cell requiring clock distribution, 3 is a clock input pin, 4
Is a clock driver, 5 is a clock main line, and 6 is a clock pin. The above is almost the same as the conventional example of FIG.

Reference numeral 8 denotes a semiconductor circuit layer on which a semiconductor integrated circuit in the semiconductor integrated circuit device 1 is formed, 9 denotes a gate electrode of each cell 2, 10 denotes an insulating layer formed on the semiconductor circuit layer 8, 1
Reference numeral 1 denotes a through hole for gate connection formed by filling a hole provided in the insulating layer 10 with a conductor, and reference numeral 12 denotes a clock pin arranged to be electrically connected to the through hole 11 for gate connection. Reference numeral 6 denotes a signal wiring layer on which other signal lines (not shown) are also wired. 1
Reference numeral 3 denotes an insulating layer formed on the signal wiring layer 12, and reference numeral 14 denotes a clock pin connection formed by filling a hole provided in the insulating layer 13 with a conductor and arranged to be connected to the clock pin 6. Reference numeral 15 denotes a dedicated clock wiring layer wired so as to electrically connect the clock trunk line 5 to the clock pin connection through hole.

The semiconductor integrated circuit device 1 of this embodiment is configured as described above. An external clock signal is applied to the clock input pin 3 of the semiconductor integrated circuit device 1, amplified by the clock driver 3, and used for exclusive use. Is applied to the clock pin 6 wired to the signal wiring layer 12 through a through hole 14 provided in the insulating layer 13 immediately above each cell 2 of the clock trunk line 5 wired to the clock wiring layer 15 for gate connection. Is input from the through hole 11 to the gate electrode 9 of the cell 2 requiring clock distribution.

As described above, since the clock main line 5 is wired on the dedicated clock wiring layer 15, the clock main line 5
Does not hinder other signal lines, and wiring efficiency does not deteriorate. In addition, wiring can be performed immediately above each cell 2. Therefore, the clock pins 6 can be directly connected to the clock pins 6 through the through holes 14, and a branch line from the clock main line 5 to each clock pin 6 is not required, and an increase in clock skew value due to the branch lines can be prevented.

In the semiconductor integrated circuit device configured as described above, by using a PLL (Phase-Locked Loop) as the clock driver 3 for driving the clock main line 5, the skew value can be further suppressed. In addition, the wiring efficiency can be further improved by wiring the power / GND main line to a dedicated wiring layer different from the signal wiring layer 12 and the clock wiring layer 15.

[0013]

As described above, according to the present invention, in a semiconductor integrated circuit device having a cell requiring clock distribution, a clock trunk line in a dedicated wiring layer electrically insulated from a general signal wiring layer is provided. In addition, wiring is performed on clock pins for applying a clock signal of a cell requiring the clock distribution, and these clock pins and the clock main line are electrically connected through through holes, so that wiring efficiency can be improved. In addition, there is an effect that a semiconductor integrated circuit device which does not consider the increase in the skew value due to the branch wiring can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an embodiment of the present invention.

FIG. 2 is a partially enlarged plan view of a part A in FIG. 1;

FIG. 3 is a partially enlarged sectional view taken along line BB of FIG. 2;

FIG. 4 is a schematic plan view showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 is a semiconductor integrated circuit device, 2 cells, 3 clock input pins, 4 clock drivers, 5 clock trunk lines, 6
Clock pin, 12 signal wiring layer, 13 insulating layer, 14
Through hole, 15 clock wiring layer.

Claims (1)

[Claims] In a semiconductor integrated circuit device having a cell requiring clock distribution, a clock trunk in a dedicated wiring layer electrically insulated from a general signal wiring layer is replaced with a cell requiring clock distribution. A semiconductor integrated circuit device, which is wired on clock pins for applying a clock signal, and the clock pins and the clock main line are electrically connected through through holes.