JP3893328B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP3893328B2
JP3893328B2 JP2002206887A JP2002206887A JP3893328B2 JP 3893328 B2 JP3893328 B2 JP 3893328B2 JP 2002206887 A JP2002206887 A JP 2002206887A JP 2002206887 A JP2002206887 A JP 2002206887A JP 3893328 B2 JP3893328 B2 JP 3893328B2
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power semiconductor
semiconductor device
area
emitter electrode
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JP2004055589A (en
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康雄 田中
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Description

【０００１】
【発明の属する技術分野】
本発明は、産業用インバータ等に採用される電力用半導体装置に関する。
【０００２】
【従来の技術】
図４に、従来の電力用半導体装置の一例を示す。この電力用半導体装置５０では、矩形状のセラミック絶縁基板５５の主表面上に、基板５５の長手方向に沿って、エミッタ電極５６，コレクタ電極５７及びゲート電極５８が順に形成され、コレクタ電極５７の形成領域上に、電力用半導体チップ５１が搭載されている。電力用半導体チップ５１上には、エミッタ電極部５６が略全域に形成され、このエミッタ電極部５６は、ゲート電極５８側からエミッタ電極５６側へ平行して複数本延びる線状のゲート電極部５３Ａによりその大部分の領域で区画化され、全体として略櫛状をなしている。図４に示す例では、ゲート電極部５３Ａによってエミッタ電極部５２の大部分の領域が５等分され、エミッタ電極部５２は、５本の歯をもつ櫛状をなしている。
【０００３】
エミッタ電極部５２の各区画領域５２ａは、エミッタ電極５６とそれぞれアルミワイヤ５４を介して接続される。他方、ゲート電極５８側では、線状のゲート電極部５３Ｂとともに、エミッタ電極部５２の中央の区画領域５２ａに形成されたゲート電極部５３Ａが、アルミワイヤ５９を介して、エミッタ電極５６と接続される。
【０００４】
以上の構成を備えた電力用半導体装置５０の動作について説明する。例えば電力用半導体チップ５１に接続されるゲート電極５６とエミッタ電極５８との間に、所定の外部回路を用いて＋１５Ｖの電圧を印加した場合、主電流が、コレクタ電極５７から電力用半導体チップ５１のエミッタ電極部５２を通過し、アルミワイヤ４を介してエミッタ電極５８へ流れる。また、一方、ゲート電極５６とエミッタ電極５８との間に、−１５Ｖの電圧を印加した場合には、主電流が遮断される。このようにして、外部回路からのゲート〜エミッタ間の電圧の制御によりスイッチング動作が実行可能である。
【０００５】
【発明が解決しようとする課題】
ところで、前述した従来の電力用半導体装置５０では、電力用半導体チップ５１上のゲート電極部５３Ａにより、エミッタ電極部５２が大部分の領域で複数の区画領域５２ａをなすように区画されているため、区画領域５２ａ間の電気抵抗やインダクタンスが大きく、電流が通過している状態で、それら区画領域５２ａ間の電流均一性が悪くなり、実質的な発熱源に偏りを生じたり、スイッチング時の過渡的アンバランスが大きくなり、スイッチング時の損失アンバランスにより破壊耐量の低下を起こしたりする等の問題があった。
【０００６】
本発明は、上記技術的課題に鑑みてなされたもので、搭載される電力用半導体チップの構造を変更させることなく、十分な実質的熱抵抗の低下や破壊耐量の向上を図る電力用半導体装置を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本願の第１の発明は、所定の基板の主表面上にエミッタ電極，コレクタ電極及びゲート電極が形成され、該コレクタ電極の形成領域上に、電力用半導体チップが搭載された電力用半導体装置において、電力用半導体チップ上の略全域にエミッタ電極部が形成され、該エミッタ電極部が、その一端側から平行して複数本延びる線状のゲート電極部によりその大部分の領域で区画され、全体として略櫛状をなしており、上記ゲート電極部により区画化されてなるエミッタ電極部の区画領域同士を電気的に接続する区画領域中継用ワイヤが設けられていることを特徴としたものである。
【０００８】
また、本願の第２の発明は、上記区画領域中継用ワイヤの各区画領域での接合点が、各区画領域の延びる方向において前後交互に配置されていることを特徴としたものである。
【０００９】
更に、本願の第３の発明は、上記区画領域中継用ワイヤとして、上記区画領域のうちの最も外側の区画領域と中央又はその近傍の区画領域とを優先して電気的に接続するワイヤと、残りの区画領域同士を電気的に接続するワイヤが設けられていることを特徴としたものである。
【００１０】
【発明の実施の形態】
以下、本発明の実施の形態について、添付図面を参照しながら説明する。
実施の形態１．
図１は、本発明の実施の形態１に係る電力用半導体装置を示す平面図である。この電力用半導体装置１０では、矩形状のセラミック絶縁基板５の主表面上に、基板５の長手方向に沿って、エミッタ電極６，コレクタ電極７及びゲート電極８が順に形成され、コレクタ電極７の形成領域上に、電力用半導体チップ１が搭載されている。電力用半導体チップ１上には、エミッタ電極部６が略全域に形成され、このエミッタ電極部６は、ゲート電極８側からエミッタ電極６側へ平行して複数本延びる線状のゲート電極部３Ａによりその大部分の領域で区画され、全体として略櫛状をなしている。図１に示す例では、ゲート電極部３Ａによってエミッタ電極部２の大部分の領域が５等分され、エミッタ電極部２は、全体として５本の歯をもつ櫛状をなしている。
【００１１】
エミッタ電極部２の各区画領域２ａは、エミッタ電極６とそれぞれアルミワイヤ４を介して接続される。他方、ゲート電極８側では、線状のゲート電極部３Ｂとともに、エミッタ電極部２の中央の区画領域２ａに形成されたゲート電極部３Ａが、アルミワイヤ９を介して、エミッタ電極６と接続される。アルミワイヤ４又は９は、超音波接合等により各区画領域２ａや電極６又は８に対してボンディングされてもよい。
【００１２】
この実施の形態１では、更に、ゲート電極部３Ａにより区画化されたエミッタ電極部２の区画領域２ａを、基板５の幅方向に沿って電気的に接続する１本のアルミ製のワイヤ（以下、区画領域中継用ワイヤという）１５が設けられている。この区画領域中継用ワイヤ１５は、その両端部でそれぞれ最も外側の区画領域２ａに接合され、その途中部において、内側の各区画領域２ａに接合され、これにより、全ての区画領域２ａを電気的に接続している。各区画領域２ａでの接合点は、ほぼ一直線上に配置されている。なお、区画領域中継用ワイヤ１５としては、アルミ製のものに限定されることはなく、適切であれば他の金属製のワイヤを用いてもよい。
【００１３】
以上の構成を備えた電力用半導体装置１０によれば、大掛かりなチップ構造の変更を実施することなく、区画領域中継用ワイヤ１５により区画領域２ａ間を電気接続することで、電力用半導体チップ１内の電流分布を改善することができ、これにより、実効通電面積が増大し、発熱面積を増大させることが可能である。その結果、実質熱抵抗の低減及び破壊耐量の向上を実現することができる。
【００１４】
実施の形態２．
図２は、本発明の実施の形態２に係る電力用半導体装置を示す平面図である。この電力用半導体装置２０は、上記実施の形態１における場合とほぼ同じ構成を有しているもので、この実施の形態２では、各区画領域２ａ間を電気接続するための区画領域中継用ワイヤ２５が、各区画領域２ａでの接合点が一直線上に配置されるように設けられていない。ここでは、図２に示すように、区画領域中継用ワイヤ２５が、各区画領域２ａでの接合点が各区画領域２ａの延びる方向において前後交互に配置されるように接続されている。
【００１５】
かかる構成を備えた電力用半導体装置２０では、上記実施の形態１において各区画領域２ａでの接合点が一直線上に配置される場合と比較して、区画領域中継用ワイヤ２５を太く設定することが可能となる。これにより、電力用半導体チップ１内の電流分布を一層良好に改善することができ、実質熱抵抗の低減及び破壊耐量の向上を実現することができる。また、かかる区画領域中継用ワイヤ２５は、チップサイズが小さい場合においても、装置の組立性を損なうことなく適用可能である。
【００１６】
実施の形態３．
図３は、本発明の実施の形態３に係る電力用半導体装置を示す平面図である。この電力用半導体装置３０は、上記実施の形態１及び２における場合とほぼ同様の構成を有しているもので、この実施の形態３では、区画領域２ａ間を電気接続するための区画領域中継用ワイヤとして、上記実施の形態１及び２における場合のように全ての区画領域２ａ間を１本で電気接続するワイヤ１５又は２５でなく、複数（ここでは２本）の区画領域中継用ワイヤ３５Ａ及び３５Ｂを用いる。
【００１７】
区画領域中継用ワイヤ３５Ａは、その両端部で、最も外側の区画領域２ａに接合されるとともに、その途中部で、中央の区画領域２ａに接合されている。他方、区画領域中継用ワイヤ３５Ｂは、その両端部で、最も外側の区画領域２ａより内側のまた中央の区画領域２ａより外側の区画領域２ａ（図３に示す例では中央の区画領域２ａの両隣の区画領域２ａ）に接合されている。
【００１８】
このように、区画領域中継用ワイヤ３５Ａを用いて、最も外側の区画領域２ａと中央の区画領域２ａとを優先して電気的に接続することにより、区画領域中継用ワイヤがない条件下で、内側の区画領域２ａに比べて区画化が良好でないすなわち電流均一性を確保し得ない外側の区画領域２ａを優先して補うことができる。また、残りの区画領域２ａ同士を別の区画領域中継用ワイヤ３５Ｂを用いて接続することにより、電気抵抗について各区画領域２ａ間の差を小さくすることができ、この作用により、更なる効果の増大が得られる。
【００１９】
なお、本発明は、例示された実施の形態に限定されるものでなく、本発明の要旨を逸脱しない範囲において、種々の改良及び設計上の変更が可能であることは言うまでもない。
【００２０】
【発明の効果】
本願の請求項１の発明によれば、所定の基板の主表面上にエミッタ電極，コレクタ電極及びゲート電極が形成され、該コレクタ電極の形成領域上に、電力用半導体チップが搭載された電力用半導体装置において、電力用半導体チップ上の略全域にエミッタ電極部が形成され、該エミッタ電極部が、その一端側から平行して複数本延びる線状のゲート電極部によりその大部分の領域で区画され、全体として略櫛状をなしており、上記ゲート電極部により区画化されてなるエミッタ電極部の区画領域同士を電気的に接続する区画領域中継用ワイヤが電気的に低いインピーダンスとインダクタンスが得られるように設けられているので、安定して電力用半導体チップ内の電流分担を改善することができ，低熱抵抗及び高破壊耐量を実現することができる。
【００２１】
また、本願の請求項２の発明によれば、上記区画領域中継用ワイヤの各区画領域での接合点が、各区画領域の延びる方向において前後交互に配置されているので、各区画領域での接合点が一直線上に配置される場合と比較して、区画領域中継用ワイヤを太く設定することが可能であり、電力用半導体チップ内の電流分布を一層良好に改善することができる。
【００２２】
更に、本願の請求項３の発明によれば、上記区画領域中継用ワイヤとして、上記区画領域のうちの最も外側の区画領域と中央又はその近傍の区画領域とを優先して電気的に接続するワイヤと、残りの区画領域同士を電気的に接続するワイヤが設けられているので、区画領域中継用ワイヤがない条件下で、内側の区画領域に比べて区画化が良好でないすなわち電流均一性を確保し得ない外側の区画領域を優先して補うことができ、また、残りの区画領域同士を別の区画領域中継用ワイヤを用いて接続することにより、電気抵抗について各区画領域間の差を小さくすることができ、電力用半導体チップ内の電流分布を一層良好に改善することができる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１に係る電力用半導体装置を示す平面図である。
【図２】 本発明の実施の形態２に係る電力用半導体装置を示す平面図である。
【図３】 本発明の実施の形態３に係る電力用半導体装置を示す平面図である。
【図４】 従来の電力用半導体装置を示す平面図である。
【符号の説明】
１ 電力用半導体チップ，２ 半導体チップ上のエミッタ電極部，２ａ 区画領域，３Ａ，３Ｂ 半導体チップ上のゲート電極部，４ エミッタ電極−電極部間接続用ワイヤ，５ 絶縁基板，６ 絶縁基板上のエミッタ電極，７ 絶縁基板上のコレクタ電極，８ 絶縁基板上のゲート電極，９ ゲート電極−電極部間接続用ワイヤ，１０ 電力用半導体装置，１５，２５，３５Ａ，３５Ｂ 区画領域中継用ワイヤ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device employed in an industrial inverter or the like.
[0002]
[Prior art]
FIG. 4 shows an example of a conventional power semiconductor device. In this power semiconductor device 50, an emitter electrode 56, a collector electrode 57, and a gate electrode 58 are sequentially formed on the main surface of a rectangular ceramic insulating substrate 55 along the longitudinal direction of the substrate 55. A power semiconductor chip 51 is mounted on the formation region. On the power semiconductor chip 51, an emitter electrode portion 56 is formed in substantially the entire region, and the emitter electrode portion 56 is a plurality of linear gate electrode portions 53A extending in parallel from the gate electrode 58 side to the emitter electrode 56 side. Therefore, it is partitioned in most of the region, and has a substantially comb shape as a whole. In the example shown in FIG. 4, most of the region of the emitter electrode portion 52 is equally divided into five by the gate electrode portion 53 </ b> A, and the emitter electrode portion 52 has a comb shape having five teeth.
[0003]
Each partition region 52 a of the emitter electrode portion 52 is connected to the emitter electrode 56 via an aluminum wire 54. On the other hand, on the gate electrode 58 side, together with the linear gate electrode portion 53B, the gate electrode portion 53A formed in the central partition region 52a of the emitter electrode portion 52 is connected to the emitter electrode 56 via the aluminum wire 59. The
[0004]
The operation of the power semiconductor device 50 having the above configuration will be described. For example, when a voltage of +15 V is applied between the gate electrode 56 and the emitter electrode 58 connected to the power semiconductor chip 51 using a predetermined external circuit, the main current is supplied from the collector electrode 57 to the power semiconductor chip 51. And flows to the emitter electrode 58 through the aluminum wire 4. On the other hand, when a voltage of −15 V is applied between the gate electrode 56 and the emitter electrode 58, the main current is cut off. In this way, the switching operation can be performed by controlling the voltage between the gate and the emitter from the external circuit.
[0005]
[Problems to be solved by the invention]
By the way, in the conventional power semiconductor device 50 described above, the emitter electrode portion 52 is partitioned by the gate electrode portion 53A on the power semiconductor chip 51 so as to form a plurality of partition regions 52a in most regions. In the state where the electrical resistance and inductance between the partition regions 52a are large and current is passing, the current uniformity between the partition regions 52a is deteriorated, the bias of the substantial heat source is generated, or the transient during switching There is a problem that the dynamic unbalance becomes large and the breakdown tolerance is lowered due to the loss unbalance at the time of switching.
[0006]
The present invention has been made in view of the above technical problem, and a power semiconductor device capable of sufficiently reducing a substantial thermal resistance and improving a breakdown resistance without changing a structure of a power semiconductor chip to be mounted. The purpose is to provide.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a power semiconductor device in which an emitter electrode, a collector electrode, and a gate electrode are formed on a main surface of a predetermined substrate, and a power semiconductor chip is mounted on a region where the collector electrode is formed. The emitter electrode portion is formed over substantially the entire area of the power semiconductor chip, and the emitter electrode portion is partitioned in the most area by a plurality of linear gate electrode portions extending in parallel from one end side thereof. Is formed in a substantially comb shape, and is provided with a partition region relay wire that electrically connects the partition regions of the emitter electrode portion partitioned by the gate electrode portion. .
[0008]
In addition, the second invention of the present application is characterized in that the junction points in each partitioned area of the partitioned area relay wire are alternately arranged in the front-rear direction in the extending direction of each partitioned area.
[0009]
Furthermore, the third invention of the present application, as the partition area relay wire, a wire that preferentially electrically connects the outermost partition area of the partition area and the partition area in the center or the vicinity thereof, A wire for electrically connecting the remaining partition regions is provided.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a plan view showing a power semiconductor device according to Embodiment 1 of the present invention. In this power semiconductor device 10, an emitter electrode 6, a collector electrode 7, and a gate electrode 8 are formed in this order along the longitudinal direction of the substrate 5 on the main surface of the rectangular ceramic insulating substrate 5. A power semiconductor chip 1 is mounted on the formation region. On the power semiconductor chip 1, an emitter electrode portion 6 is formed in substantially the entire region, and the emitter electrode portion 6 is a plurality of linear gate electrode portions 3A extending in parallel from the gate electrode 8 side to the emitter electrode 6 side. Is partitioned in most of the region, and has a substantially comb shape as a whole. In the example shown in FIG. 1, the gate electrode portion 3A divides most of the emitter electrode portion 2 into five equal parts, and the emitter electrode portion 2 has a comb shape having five teeth as a whole.
[0011]
Each partition region 2 a of the emitter electrode portion 2 is connected to the emitter electrode 6 via an aluminum wire 4. On the other hand, on the gate electrode 8 side, the gate electrode portion 3A formed in the central partition region 2a of the emitter electrode portion 2 is connected to the emitter electrode 6 through the aluminum wire 9 together with the linear gate electrode portion 3B. The The aluminum wire 4 or 9 may be bonded to each partition region 2a or the electrode 6 or 8 by ultrasonic bonding or the like.
[0012]
In the first embodiment, furthermore, a single aluminum wire (hereinafter referred to as “wire”) that electrically connects the partition region 2a of the emitter electrode portion 2 partitioned by the gate electrode portion 3A along the width direction of the substrate 5. (Referred to as a segmented area relay wire) 15. This partition area relay wire 15 is joined to the outermost partition area 2a at both ends thereof, and is joined to the inner partition areas 2a in the middle, thereby electrically connecting all the partition areas 2a. Connected to. Junction points in each partition region 2a are arranged substantially on a straight line. The partition region relay wire 15 is not limited to aluminum, and other metal wires may be used as appropriate.
[0013]
According to the power semiconductor device 10 having the above configuration, the power semiconductor chip 1 can be obtained by electrically connecting the partition regions 2a with the partition region relay wires 15 without changing the chip structure greatly. Current distribution can be improved, whereby the effective energization area can be increased and the heat generation area can be increased. As a result, it is possible to reduce the substantial thermal resistance and improve the breakdown resistance.
[0014]
Embodiment 2. FIG.
FIG. 2 is a plan view showing a power semiconductor device according to the second embodiment of the present invention. The power semiconductor device 20 has substantially the same configuration as that in the first embodiment. In the second embodiment, a partition area relay wire for electrically connecting the partition areas 2a. 25 is not provided so that the junction points in each partition region 2a are arranged on a straight line. Here, as shown in FIG. 2, the partition area relay wires 25 are connected so that the junction points in each partition area 2a are alternately arranged in the front-rear direction in the extending direction of each partition area 2a.
[0015]
In the power semiconductor device 20 having such a configuration, the partition area relay wire 25 is set to be thicker than in the case where the junction points in the partition areas 2a are arranged in a straight line in the first embodiment. Is possible. As a result, the current distribution in the power semiconductor chip 1 can be further improved, and the real thermal resistance can be reduced and the breakdown tolerance can be improved. In addition, the partitioned region relay wire 25 can be applied without impairing the assembly of the apparatus even when the chip size is small.
[0016]
Embodiment 3 FIG.
FIG. 3 is a plan view showing a power semiconductor device according to the third embodiment of the present invention. The power semiconductor device 30 has substantially the same configuration as in the first and second embodiments. In the third embodiment, the partitioned area relay for electrically connecting the partitioned areas 2a. As a wire for use, not a single wire 15 or 25 for electrically connecting all the divided areas 2a as in the first and second embodiments, but a plurality (two in this case) of divided area relay wires 35A. And 35B.
[0017]
The partition area relay wire 35A is joined to the outermost partition area 2a at both ends thereof, and is joined to the center partition area 2a in the middle thereof. On the other hand, the partition area relay wire 35B has a partition area 2a inside the outermost partition area 2a and outside the center partition area 2a at both ends thereof (in the example shown in FIG. 3, adjacent to the center partition area 2a). To the partition region 2a).
[0018]
In this way, by using the partition area relay wire 35A to electrically connect the outermost partition area 2a and the central partition area 2a with priority, under the condition that there is no partition area relay wire, Comparing to the inner partition area 2a, the outer partition area 2a, which is not good in partitioning, that is, cannot secure current uniformity, can be preferentially supplemented. Further, by connecting the remaining partition areas 2a to each other using another partition area relay wire 35B, the difference between the partition areas 2a in terms of electrical resistance can be reduced. An increase is obtained.
[0019]
Note that the present invention is not limited to the illustrated embodiments, and it goes without saying that various improvements and design changes are possible without departing from the scope of the present invention.
[0020]
【The invention's effect】
According to the invention of claim 1 of the present application, an emitter electrode, a collector electrode, and a gate electrode are formed on a main surface of a predetermined substrate, and a power semiconductor chip is mounted on the collector electrode forming region. In a semiconductor device, an emitter electrode portion is formed in substantially the entire region on a power semiconductor chip, and the emitter electrode portion is partitioned in a large area by a plurality of linear gate electrode portions extending in parallel from one end side thereof. As a whole, it has a substantially comb shape, and the partitioned region relay wire that electrically connects the partitioned regions of the emitter electrode portion partitioned by the gate electrode portion has an electrically low impedance and inductance. Therefore, current sharing in the power semiconductor chip can be improved stably, and low thermal resistance and high breakdown resistance can be realized. That.
[0021]
Further, according to the invention of claim 2 of the present application, since the junction points in each partition region of the partition region relay wire are alternately arranged in the front and rear in the extending direction of each partition region, Compared to the case where the junction points are arranged in a straight line, the partition region relay wire can be set thicker, and the current distribution in the power semiconductor chip can be further improved.
[0022]
Furthermore, according to the invention of claim 3 of the present application, as the partition area relay wire, the outermost partition area of the partition areas is electrically connected with priority in the center or in the vicinity thereof. Since the wire and the wire that electrically connects the remaining partition areas are provided, the partitioning is not as good as the inner partition area under the condition that there is no partition area relay wire. It is possible to preferentially compensate for the outside partition areas that cannot be secured, and by connecting the remaining partition areas using another partition area relay wire, the difference between the partition areas in terms of electrical resistance can be reduced. The current distribution in the power semiconductor chip can be further improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a power semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a power semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a plan view showing a power semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a plan view showing a conventional power semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Power semiconductor chip, 2 Emitter electrode part on semiconductor chip, 2a Partition area, 3A, 3B Gate electrode part on semiconductor chip, 4 Emitter electrode-electrode part connection wire, 5 Insulating substrate, 6 On insulating substrate Emitter electrode, 7 Collector electrode on insulating substrate, 8 Gate electrode on insulating substrate, 9 Gate electrode-electrode connecting wire, 10 Power semiconductor device, 15, 25, 35A, 35B Partition region relay wire.

Claims (3)

所定の基板の主表面上にエミッタ電極，コレクタ電極及びゲート電極が形成され、該コレクタ電極の形成領域上に、電力用半導体チップが搭載された電力用半導体装置において、
電力用半導体チップ上の略全域にエミッタ電極部が形成され、該エミッタ電極部が、その一端側から平行して複数本延びる線状のゲート電極部によりその大部分の領域で区画され、全体として略櫛状をなしており、
上記ゲート電極部により区画化されてなるエミッタ電極部の区画領域同士を電気的に接続する区画領域中継用ワイヤが設けられていることを特徴とする電力用半導体装置。In a power semiconductor device in which an emitter electrode, a collector electrode, and a gate electrode are formed on a main surface of a predetermined substrate, and a power semiconductor chip is mounted on a region where the collector electrode is formed,
An emitter electrode portion is formed in substantially the entire area of the power semiconductor chip, and the emitter electrode portion is partitioned in the most area by a plurality of linear gate electrode portions extending in parallel from one end side thereof, and as a whole It ’s almost comb-shaped,
A power semiconductor device, comprising: a partition region relay wire that electrically connects the partition regions of the emitter electrode section partitioned by the gate electrode portion. 上記区画領域中継用ワイヤの各区画領域での接合点が、各区画領域の延びる方向において前後交互に配置されていることを特徴とする請求項１記載の電力用半導体装置。The power semiconductor device according to claim 1, wherein junction points in each partition region of the partition region relay wires are alternately arranged in the front-rear direction in a direction in which each partition region extends. 上記区画領域中継用ワイヤとして、上記区画領域のうちの最も外側の区画領域と中央又はその近傍の区画領域とを優先して電気的に接続するワイヤと、残りの区画領域同士を電気的に接続するワイヤが設けられていることを特徴とする請求項１記載の電力用半導体装置。As the partition area relay wire, a wire that electrically connects the outermost partition area of the partition areas and the partition area in the center or its vicinity with priority, and the remaining partition areas are electrically connected to each other. The power semiconductor device according to claim 1, further comprising a wire for performing power supply.
JP2002206887A 2002-07-16 2002-07-16 Power semiconductor device Expired - Fee Related JP3893328B2 (en)

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