JP2006165151A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP2006165151A
JP2006165151A JP2004352401A JP2004352401A JP2006165151A JP 2006165151 A JP2006165151 A JP 2006165151A JP 2004352401 A JP2004352401 A JP 2004352401A JP 2004352401 A JP2004352401 A JP 2004352401A JP 2006165151 A JP2006165151 A JP 2006165151A
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Japan
Prior art keywords
power
wire
semiconductor device
main
electrode
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Granted
Application number
JP2004352401A
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Japanese (ja)
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JP4471823B2 (en
Inventor
Masao Kikuchi
正雄 菊池
Koichi Tsurusako
浩一 鶴迫
Kunihiro Yoshihara
邦裕 吉原
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2004352401A priority Critical patent/JP4471823B2/en
Publication of JP2006165151A publication Critical patent/JP2006165151A/en
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Publication of JP4471823B2 publication Critical patent/JP4471823B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To improve the lifetime for the heat cycle fatigue in switching operation by making current density per unit wire small, and by lowering the temperature rise in the bonding part of the main current wire. <P>SOLUTION: Apart from the wire group of main current wires 10 with a bonding part 22a for the main current wires, a bonding wire 17a with single bonding parts 21a and 21b is formed on the anode electrode 14 of a diode 2 for electric power and on an emitter electrode 13 for transistor 1 for electric power. In addition, a bonding wire 17b with single bonding parts 21c and 21d is formed on near one end side of a second main terminal 6 and on the other end side of the anode electrode 14 of the diode 2 for electric power (on the electrode surface in the vicinity of the opposite end side of the emitter electrode 13). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、大電流を制御するための電力半導体装置に関する。   The present invention relates to a power semiconductor device for controlling a large current.

図６は、従来の電力半導体装置の内部構造を透視した俯瞰図である。電力半導体装置は、一般的に、２種類の素子を、即ち、電力用トランジスタ１及び電力用ダイオード２を使用する。図６に於いて、第１主端子５は電力半導体装置に流れ込む電流のための入力端子であり、第２主端子６は本装置から負荷へ電流を出力する出力端子であり、信号端子７は例えばゲート電圧入力端子やエミッタセンス端子より成る。各素子１，２は、基板３の金属パターン４上に搭載されており、基板３はベース板８に固着されてケース９内に収納された上で、上面より蓋を被せて保護される。ここで、図７は、電力用トランジスタ１、電力用ダイオード２及びこれらの素子の電気的な接続構成を示す平面図である。   FIG. 6 is a bird's-eye view of the internal structure of a conventional power semiconductor device. A power semiconductor device generally uses two types of elements, that is, a power transistor 1 and a power diode 2. In FIG. 6, a first main terminal 5 is an input terminal for current flowing into the power semiconductor device, a second main terminal 6 is an output terminal for outputting current from the device to a load, and a signal terminal 7 is For example, it consists of a gate voltage input terminal and an emitter sense terminal. The elements 1 and 2 are mounted on the metal pattern 4 of the substrate 3. The substrate 3 is secured to the base plate 8 and accommodated in the case 9, and then protected by a cover from the upper surface. Here, FIG. 7 is a plan view showing a power transistor 1, a power diode 2, and an electrical connection configuration of these elements.

電力半導体装置は、所定のゲート電圧が印加された場合には、コレクタ領域とエミッタ領域とにチャネルが形成され、コレクタ電極に流入する電流がエミッタ電極から流出する電力スイッチとして働く。ゲート電圧の印加時間や電圧レベルを変えることによって、エミッタ電極から負荷側へ流出する出力を制御する。   In the power semiconductor device, when a predetermined gate voltage is applied, a channel is formed in the collector region and the emitter region, and the power semiconductor device functions as a power switch in which a current flowing into the collector electrode flows out from the emitter electrode. The output flowing from the emitter electrode to the load side is controlled by changing the application time and voltage level of the gate voltage.

他方、ゲート電圧を印加しないスイッチオフの場合には、負荷のインダクタンスに蓄えられた電流エネルギーが電力半導体装置側に還流する。この際、電力用ダイオード２が順方向となる様に回路構成されており、電力用ダイオード２に還流電流が流れる。   On the other hand, when the switch is turned off without applying the gate voltage, the current energy stored in the inductance of the load returns to the power semiconductor device side. At this time, the circuit is configured so that the power diode 2 is in the forward direction, and a return current flows through the power diode 2.

この様な電力半導体装置は、電力用トランジスタ１のコレクタ電極（第１主電極に相当）及び電力用ダイオード２のカソード電極（両者共に対応素子１，２の裏面であり、その符号は省略）並びに第１主端子５の組合わせと、エミッタ電極１３及びアノード電極１４並びに第２主端子６の組合わせとから構成され、前者の組合わせ（コレクタ電極―カソード電極―第１主端子５）は、基板３の金属パターン４及びボンディングワイヤ１１を介して、電気的に接続される。コレクタ電極及びカソード電極は、これらの素子１，２を搭載する基板３上の金属パターン４の上に搭載され、金属パターン４と半田付けされる。これによって、双方の電極同士が電気的に接続される。従来例では、第１主端子５と金属パターン４との間はボンディングワイヤ１１によって互いに接続されているが、これに代えて、半田付け等の方法が用いられることもある。他方、電力用トランジスタ１のエミッタ電極１３、電力用ダイオード２のアノード電極１４及び第２主端子６は、ボンディングワイヤ１０によって接続されており、しかも、ボンディングワイヤ１０は、アノード電極１４上のボンディングワイヤ１０のボンド部（ステッチボンド部）２２ａで切断されること無く、連続的に第２主端子６あるいはエミッタ電極１３に向かって繋がれている。そして、ボンディングワイヤ１０は、電力半導体装置の主電流を輸送する電流路を形成しており、以下、ボンディングワイヤ１０を「主電流ワイヤ」と称する。又、この様に、接合後に切断せずに連続的にボンディングする方法を「ステッチボンド」と称する。ステッチボンドのボンディングワイヤ１０には、アルミニウムワイヤが一般的に良く用いられるが、数十〜数百アンペア以上の主電流を流す電力半導体装置では、従来例の様に、複数本の主電流ワイヤ１０をボンディングすることによって、アルミニウムワイヤが溶断しない様に、電流容量が確保されている。   Such a power semiconductor device includes a collector electrode (corresponding to a first main electrode) of the power transistor 1 and a cathode electrode of the power diode 2 (both are the back surfaces of the corresponding elements 1 and 2, and the reference numerals are omitted) and The combination of the first main terminal 5 and the combination of the emitter electrode 13 and the anode electrode 14 and the second main terminal 6, the former combination (collector electrode-cathode electrode-first main terminal 5), Electrical connection is established via the metal pattern 4 of the substrate 3 and the bonding wire 11. The collector electrode and the cathode electrode are mounted on the metal pattern 4 on the substrate 3 on which these elements 1 and 2 are mounted, and are soldered to the metal pattern 4. Thereby, both electrodes are electrically connected. In the conventional example, the first main terminal 5 and the metal pattern 4 are connected to each other by the bonding wire 11, but instead of this, a method such as soldering may be used. On the other hand, the emitter electrode 13 of the power transistor 1, the anode electrode 14 of the power diode 2, and the second main terminal 6 are connected by a bonding wire 10, and the bonding wire 10 is a bonding wire on the anode electrode 14. It is continuously connected toward the second main terminal 6 or the emitter electrode 13 without being cut by 10 bond portions (stitch bond portions) 22a. The bonding wire 10 forms a current path for transporting the main current of the power semiconductor device. Hereinafter, the bonding wire 10 is referred to as a “main current wire”. In addition, a method of bonding continuously without cutting after joining is referred to as “stitch bonding”. Aluminum wires are generally used as the stitch bond bonding wires 10. However, in a power semiconductor device that allows a main current of several tens to several hundred amperes or more, a plurality of main current wires 10 are used as in the conventional example. By bonding, a current capacity is secured so that the aluminum wire does not melt.

上記従来例の電力半導体装置では、エミッタ電極１３、アノード電極１４及び第２主端子６をステッチボンドすることによって直接連接しているために、基板上に中間電極を設けることが不要となり、ステッチボンドの技術は電力半導体装置全体の小型化に寄与し得る。   In the above-described conventional power semiconductor device, the emitter electrode 13, the anode electrode 14 and the second main terminal 6 are directly connected by stitch bonding, so that it is not necessary to provide an intermediate electrode on the substrate. This technique can contribute to miniaturization of the entire power semiconductor device.

特開２０００−３５３７７８号公報（図１）JP 2000-353778 A (FIG. 1)

以上の様に構成された従来の電力半導体装置においては、主電流が電力用トランジスタあるいは電力用ダイオードを流れる際に各素子の電圧降下によって発熱し、素子表面の温度が上昇する。この際、素子表面のボンド部には、アルミニウムから成るボンディングワイヤとシリコンから成る素子間の物性上のミスマッチによる熱応力が発生し、スイッチング数の増加によって熱サイクル疲労が進行し、究極的にはボンド部が破壊されてパワーサイクル寿命に至る。このため、所望の電流容量を流すために必要な複数の主電流ワイヤが、局部的な素子表面温度の上昇を避ける様に、素子上を分散配置されており、これによって電流容量の平準化を図っている。   In the conventional power semiconductor device configured as described above, when the main current flows through the power transistor or the power diode, heat is generated by the voltage drop of each element, and the temperature of the element surface rises. At this time, thermal stress occurs due to physical mismatch between the bonding wire made of aluminum and the element made of silicon at the bond portion on the surface of the element, and thermal cycle fatigue progresses due to an increase in the number of switching, ultimately. The bond part is destroyed and the power cycle life is reached. For this reason, a plurality of main current wires necessary for flowing a desired current capacity are distributed over the elements so as to avoid a local increase in the element surface temperature, thereby leveling the current capacity. I am trying.

しかしながら、エミッタ電極とアノード電極間にステッチボンドによって連接された主電流ワイヤのボンド部に関しては、これらのボンド部をステッチボンドされた主電流ワイヤの長手方向に並べて接合部を形成することは、隣接ワイヤとの干渉を避けて安定的に形成する観点から見た場合、不可能であると言え、結局、ボンド部２２ａを、図６及び図７に示す様に、電力用ダイオード２の幅方向（紙面の上から下への縦方向に相当）に沿って一列に配置せざるを得ず、実質的にはステッチボンド部を対角線上に沿って配置することが寸法上の限界であった。このため、デバイスの主電流が大きくなると、主電流ワイヤの本数が増大し、その分だけ電力用ダイオード２の幅方向に一列に並んだステッチボンド部２２ａの配置数が増加するので、電力用ダイオード２の素子サイズがより縦長型となり、素子サイズをより一層大きくする必要性が生じていた。このことは、１個のシリコンウエハから採取し得る電力用ダイオード２の素子数の減少をもたらし、その分だけ、本装置のコストアップをもたらしている。逆に、ステッチボンド部２２ａの配置数を少なくすると、その分だけ素子サイズが幅方向に関してより短くなるけれども、主電流ワイヤのボンド部に於ける発熱量が増大し、熱サイクル疲労に対する寿命の低下と言う問題点が深刻化する。   However, for the main current wire bonds connected by stitch bonds between the emitter electrode and the anode electrode, it is adjoining to form these joints by arranging these bonds in the longitudinal direction of the stitch bonded main current wires. From the viewpoint of stable formation while avoiding interference with the wire, it can be said that this is impossible. Eventually, the bond portion 22a is formed in the width direction of the power diode 2 (see FIG. 6 and FIG. 7). In other words, it is necessary to arrange them in a line along the vertical direction from the top to the bottom of the paper. For this reason, when the main current of the device increases, the number of main current wires increases and the number of stitch bond portions 22a arranged in a line in the width direction of the power diode 2 increases accordingly. The element size of 2 has become a vertically long type, and the necessity of further increasing the element size has arisen. This leads to a decrease in the number of elements of the power diode 2 that can be taken from one silicon wafer, and this increases the cost of the apparatus. Conversely, if the number of stitch bond portions 22a is reduced, the element size becomes shorter in the width direction, but the amount of heat generated at the bond portion of the main current wire increases, and the life against thermal cycle fatigue is reduced. The problem becomes more serious.

本発明は斯かる閉塞状態を打開すべくなされたものであり、その目的とするところは、電力用ダイオードの幅方向の素子サイズの減少化（横断面形状がより正方形に近づく様にすること）を図りつつも、主電流ワイヤのボンド部の温度上昇を低減化して熱サイクル疲労に対する寿命の向上化を図る点にある。   The present invention has been made to overcome such a closed state, and its object is to reduce the element size in the width direction of the power diode (make the cross-sectional shape closer to a square). However, the temperature rise at the bond portion of the main current wire is reduced to improve the life against thermal cycle fatigue.

この発明の主題に係る電力半導体装置は、電力用スイッチング半導体素子及び電力用ダイオードを搭載した基板と第１及び第２主端子とを有し、前記電力用スイッチング半導体素子の第１主電極と前記電力用ダイオードのカソード電極と前記第１主端子とを前記基板上の金属パターンによって電気的に接続し、前記電力用スイッチング半導体素子の第２主電極と前記電力用ダイオードのアノード電極と前記第２主端子とを連続的にワイヤボンドして前記アノード電極上に主電流ワイヤのボンド部を形成することによって電気的に接続してなる電力半導体装置であって、前記電力用スイッチング半導体素子の前記第２主電極及び前記電力用ダイオードの前記アノード電極の両方にシングルボンド部を有するボンディングワイヤを形成したことを特徴とする。   A power semiconductor device according to a subject of the present invention includes a substrate on which a power switching semiconductor element and a power diode are mounted, first and second main terminals, the first main electrode of the power switching semiconductor element, and the The cathode electrode of the power diode and the first main terminal are electrically connected by a metal pattern on the substrate, the second main electrode of the power switching semiconductor element, the anode electrode of the power diode, and the second A power semiconductor device that is electrically connected by wire bonding to a main terminal continuously to form a bond portion of a main current wire on the anode electrode, the power switching semiconductor element of the power switching semiconductor element (2) A bonding wire having a single bond portion is formed on both the main electrode and the anode electrode of the power diode. And butterflies.

以下、この発明の主題の様々な具体化を、添付図面を基に、その効果・利点と共に、詳述する。   Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

本発明の主題によれば、シングルボンドの追加に伴い、電力用トランジスタと電力用ダイオードとを接続する、主電流が流れるべきワイヤの数を増加させることが出来るので、単位ワイヤ当たりの電流密度が小さくなり、主電流ワイヤのボンド部の温度上昇を低減化することが出来、スイッチング動作時に於ける熱サイクル疲労に対する寿命の向上化を図ることが出来る。特に、シングルボンド部が電力用ダイオードの幅方向に略直角な方向（主電流ワイヤの長手方向に相当）に沿ってステッチボンド部の横側に設けられる場合には、電力用ダイオードの素子の横断面形状を縦長の長方形状からより正方形に近い形状（縦方向の長さと横方向の長さとがより均衡化する形状）に変更することが出来、素子サイズの小型化、従って、装置の低コスト化を併せて実現することも可能となる。   According to the subject of the present invention, with the addition of a single bond, it is possible to increase the number of wires through which the main current flows, connecting the power transistor and the power diode, so that the current density per unit wire is increased. As a result, the temperature rise at the bond portion of the main current wire can be reduced, and the life against thermal cycle fatigue during the switching operation can be improved. In particular, when the single bond portion is provided on the lateral side of the stitch bond portion along the direction substantially perpendicular to the width direction of the power diode (corresponding to the longitudinal direction of the main current wire), the element of the power diode is crossed. The surface shape can be changed from a vertically long rectangular shape to a shape closer to a square (a shape in which the length in the vertical direction and the length in the horizontal direction are more balanced), the element size is reduced, and the cost of the device is reduced. It is also possible to realize this.

（実施の形態１）
本実施の形態の特徴点は、ステッチボンドのボンディングワイヤに加えて、シングルボンドのボンディングワイヤを追加することにある。これにより、本実施の形態は、電力半導体装置内部に於けるワイヤボンド配線のスペース効率を向上させて、ワイヤ及びチップ上の温度上昇を抑制してパワーサイクル寿命の向上化を図るものである。尚、本実施の形態では、当該ワイヤの両端にシングルボンド部を有するボンディングワイヤを、「シングルボンド」とも称する。以下、図面に基づき、本実施の形態に係る電力半導体装置の好適な一例を詳述する。 (Embodiment 1)
The feature of this embodiment is that a single bond bonding wire is added in addition to the stitch bond bonding wire. As a result, this embodiment improves the space efficiency of the wire bond wiring inside the power semiconductor device and suppresses the temperature rise on the wire and the chip, thereby improving the power cycle life. In the present embodiment, a bonding wire having single bond portions at both ends of the wire is also referred to as “single bond”. Hereinafter, a suitable example of the power semiconductor device according to the present embodiment will be described in detail with reference to the drawings.

図１は、本実施の形態に係る電力半導体装置の内部構造を示す俯瞰図であり、既述した図６に対応する図面である。又、図２は、電力用トランジスタ１、電力用ダイオード２及びこれらの素子の電気的な接続構成を示す平面図であり（Ａ−Ａ線に関する縦断面図も付記されている）、既述した図７に対応する図面である。ここで、図１及び図２中、図６及び図７と同一の参照符号は同一の構成要素を示しており、図６及び図７に関して述べた従来技術に於ける記載をこれらの参照符号で示される各構成要素に関して援用することとして、記載の簡略化を図るものとする。   FIG. 1 is an overhead view showing the internal structure of the power semiconductor device according to the present embodiment, and corresponds to FIG. 6 described above. FIG. 2 is a plan view showing a power transistor 1, a power diode 2, and an electrical connection configuration of these elements (a longitudinal sectional view with respect to the line AA is also attached). It is drawing corresponding to FIG. Here, in FIG. 1 and FIG. 2, the same reference numerals as those in FIG. 6 and FIG. 7 indicate the same components, and the description in the prior art described with reference to FIG. 6 and FIG. The description is intended to be simplified as it is incorporated with respect to each component shown.

本実施の形態では、図２に明示する通り、ステッチボンド部２２ａを有する主電流ワイヤ１０のワイヤ群とは別に、ワイヤの両端であって、電力用トランジスタ１のエミッタ電極（第２主電極に相当）１３上と電力用ダイオード２のアノード電極１４上とに、（ステッチボンド部では無い）シングルボンド部２１ａ，２１ｂを有するボンディングワイヤ（第１シングルボンド）１７ａが、形成されている。加えて、電力用ダイオード２のアノード電極１４の他端側上（エミッタ電極１３とは反対側の端近傍の電極表面上）と第２主端子６の一端側寄り部分上とに同様のシングルボンド部２１ｃ，２１ｄを有するボンディングワイヤ（第２シングルボンド）１７ｂが、形成されている。尚、ボンド部２２ａを有する主電流ワイヤ１０に関しては、少なくとも、通電中のワイヤの溶断が発生しないために必要な数量分が形成される。但し、本実施の形態では、アノード電極１４上にシングルボンド部２１ｂ，２１ｃが形成されている分だけ、ボンド部２２ａの数量は図７の場合と比較して減少する。   In the present embodiment, as clearly shown in FIG. 2, apart from the wire group of the main current wire 10 having the stitch bond portion 22a, both ends of the wire and the emitter electrode of the power transistor 1 (the second main electrode) Equivalent) A bonding wire (first single bond) 17 a having single bond portions 21 a and 21 b (not stitch bond portions) is formed on 13 and the anode electrode 14 of the power diode 2. In addition, the same single bond is formed on the other end side of the anode electrode 14 of the power diode 2 (on the electrode surface near the end opposite to the emitter electrode 13) and on the portion near the one end side of the second main terminal 6. A bonding wire (second single bond) 17b having portions 21c and 21d is formed. In addition, regarding the main current wire 10 having the bond portion 22a, at least the necessary number of wires are formed in order to prevent melting of the wire being energized. However, in the present embodiment, the number of bond portions 22a is reduced by the amount of the single bond portions 21b and 21c formed on the anode electrode 14 as compared with the case of FIG.

この様に構成された電力半導体装置においては、アノード電極１４上のステッチボンド部２２ａの両側に、エミッタ電極１３とのシングルボンド部２１ｂ及び第２主端子６とのシングルボンド部２１ｃが形成されているため、電力用ダイオード２の幅方向（図２の紙面の上から下へ向かう縦方向に相当）を大きくすることなく、ワイヤ数を増加させることが出来る。従って、電力用ダイオード２のチップの縦横寸法比を従来例よりも１：１に近づけることが可能となり、コスト低減化にも寄与し得る。この場合、シングルボンドのボンディングワイヤ１７ａ，１７ｂを流れる電流は、電力用ダイオード２のアノード電極１４を構成する厚さ数μｍのアルミニウム膜を経由するが、ボンディングワイヤ１７ａ，１７ｂは、電力用トランジスタ１のエミッタ電極１３から第２主端子６にまで至る主電流ワイヤ１０とは別個の経路を成すため、微少ながらも、主電流の一部が分配される。そのため、主電流ワイヤ１０の電流が減少し、全体的に見ると、主電流ワイヤ１０のボンド部２２ａの発熱を減少させることが出来る。   In the power semiconductor device configured as described above, a single bond portion 21 b with the emitter electrode 13 and a single bond portion 21 c with the second main terminal 6 are formed on both sides of the stitch bond portion 22 a on the anode electrode 14. Therefore, the number of wires can be increased without increasing the width direction of the power diode 2 (corresponding to the vertical direction from the top to the bottom of FIG. 2). Therefore, the vertical / horizontal dimension ratio of the chip of the power diode 2 can be made closer to 1: 1 than in the conventional example, which can contribute to cost reduction. In this case, the current flowing through the single bond bonding wires 17a and 17b passes through the aluminum film having a thickness of several μm constituting the anode electrode 14 of the power diode 2, but the bonding wires 17a and 17b are connected to the power transistor 1. Since a path separate from the main current wire 10 extending from the emitter electrode 13 to the second main terminal 6 is formed, a part of the main current is distributed although it is minute. Therefore, the current of the main current wire 10 is reduced, and the heat generation of the bond portion 22a of the main current wire 10 can be reduced as a whole.

又、図３は、本実施の形態の変形例に係る電力半導体装置に於ける、電力用トランジスタ１、電力用ダイオード２及びこれらの素子の電気的な接続構成を示す平面図である。図３の変形例は、電力用トランジスタ１のエミッタ電極１３と電力用ダイオード２のアノード電極１４の両方に、シングルボンド部２１ａ，２１ｂを有するボンディングワイヤ１７ａのみを形成した例に該当する。換言すれば、本変形例の構造は、図１及び図２に於ける構造からシングルボンドのボンディングワイヤ１７ｂを無くした構造に相当している。電力半導体装置に於いては、一般的にスイッチオン時の電力用トランジスタを通電する場合の電力損失が大きいため、図３の様に、電力用トランジスタ１と電力用ダイオード２間のシングルボンドのみの増加だけでも、既述した効果は得られる。   FIG. 3 is a plan view showing a power transistor 1, a power diode 2, and an electrical connection configuration of these elements in a power semiconductor device according to a modification of the present embodiment. The modification of FIG. 3 corresponds to an example in which only the bonding wire 17a having single bond portions 21a and 21b is formed on both the emitter electrode 13 of the power transistor 1 and the anode electrode 14 of the power diode 2. In other words, the structure of this modification corresponds to a structure in which the single bond bonding wire 17b is eliminated from the structure shown in FIGS. In a power semiconductor device, since a power loss is generally large when a power transistor is energized when the switch is turned on, only a single bond between the power transistor 1 and the power diode 2 is used as shown in FIG. The effect described above can be obtained only by the increase.

この場合、図１及び図２で記載した例と比較すると、単位ワイヤ当たりに流れる電流量は増加するが、ワイヤボンディングの数が少なくて済むため、ワイヤボンド起因不良の発生を軽減することが出来ると言う利点がある。   In this case, compared with the example described in FIG. 1 and FIG. 2, the amount of current flowing per unit wire increases, but the number of wire bondings can be reduced, so that the occurrence of defects caused by wire bonding can be reduced. There is an advantage to say.

（実施の形態２）
図４は、本実施の形態に係る電力半導体装置に於ける、電力用トランジスタ１、電力用ダイオード２及びこれらの素子の電気的な接続構成を示す平面図である。本実施の形態の特徴点は、実施の形態１で述べたエミッタ電極１３とのシングルボンド部２１ｂ及び第２主端子６とのシングルボンド部２１ｃが、共にアノード電極１４上の主電流ワイヤ用ボンド部２２ａの両側に常に形成されているのでは無くて、隣り合う主電流ワイヤ用ボンド部２２ａの間のスペースであって且つ任意の位置に形成されている点にある。 (Embodiment 2)
FIG. 4 is a plan view showing a power transistor 1, a power diode 2, and an electrical connection configuration of these elements in the power semiconductor device according to the present embodiment. The feature of this embodiment is that both the single bond portion 21b with the emitter electrode 13 and the single bond portion 21c with the second main terminal 6 described in the first embodiment are bonded to the main current wire on the anode electrode 14. It is not always formed on both sides of the portion 22a, but is a space between adjacent main current wire bond portions 22a and formed at an arbitrary position.

本実施の形態では、電力用ダイオード２のアノード電極１４上には、ボンド位置がダイオード２の幅方向（紙面の縦方向に相当）に複数列配置されているが、図４の例では、ボンド位置がアノード電極１４上を平行に二列に並列した場合を取り扱っている。即ち、幅方向に延在した各ボンド位置において、（１）エミッタ電極１３からアノード電極１４を経て第２主端子６に至る主電流ワイヤ１０のボンド部２２ａと、（２）エミッタ電極１３とアノード電極１４との間に形成されたシングルボンド１７ａのシングルボンド部２１ｂ又はアノード電極１４と第２主端子６との間に形成されたシングルボンド１７ｂのシングルボンド部２１ｃとが、任意の位置に形成されている。主電流ワイヤのボンド部２２ａの複数列は、隣接ワイヤ１０と干渉しない程度に、主電流ワイヤ１０の長手方向に沿って配設されており、各列において、各ボンド部２２ａは幅方向に所定の間隔を有して並んでいる。そして、各列において、シングルボンド部２１ｂ，２１ｃは、アノード電極１４上のボンド部２２ａが形成されている場所以外の任意の位置に形成されている。図４の例では、シングルボンド部２１ｂ，２１ｃは、主電流ワイヤのボンド部２２ａ間であって且つ主電流ワイヤのボンド部２２ａに近接した位置に形成されている。   In the present embodiment, a plurality of bond positions are arranged on the anode electrode 14 of the power diode 2 in the width direction of the diode 2 (corresponding to the vertical direction of the paper surface). In the example of FIG. The case where the positions are arranged in parallel in two rows on the anode electrode 14 is handled. That is, at each bond position extending in the width direction, (1) the bond portion 22a of the main current wire 10 extending from the emitter electrode 13 through the anode electrode 14 to the second main terminal 6, and (2) the emitter electrode 13 and the anode A single bond portion 21b of the single bond 17a formed between the electrode 14 and a single bond portion 21c of the single bond 17b formed between the anode electrode 14 and the second main terminal 6 is formed at an arbitrary position. Has been. The plurality of rows of bond portions 22a of the main current wires are arranged along the longitudinal direction of the main current wires 10 so as not to interfere with the adjacent wires 10, and in each row, each bond portion 22a is predetermined in the width direction. Are lined up with an interval of. In each row, the single bond portions 21b and 21c are formed at arbitrary positions other than the place where the bond portion 22a on the anode electrode 14 is formed. In the example of FIG. 4, the single bond portions 21 b and 21 c are formed between the main current wire bond portions 22 a and close to the main current wire bond portions 22 a.

この様な２列配置構成に修正することによって、実施の形態１と比較して、幅方向に直角な方向（図４の紙面の横方向：長手方向）に沿ってシングルボンド部と主電流ワイヤのボンド部とを配置する際のボンド配列数が少なくなる。図４の例では、ボンド部２２ａの配列に許容される電力用ダイオード２の幅内に収まる様にシングルボンド部２１ｂ，２１ｃを配列し、長手方向に関しては最低限の配列数（２列）とすることでダイオードチップの長さを小さくしている。   By modifying to such a two-row arrangement configuration, compared to the first embodiment, the single bond portion and the main current wire are along a direction perpendicular to the width direction (horizontal direction of the paper surface of FIG. 4: longitudinal direction). The number of bond arrangements when arranging the bond portions is reduced. In the example of FIG. 4, the single bond portions 21 b and 21 c are arranged so as to be within the width of the power diode 2 allowed for the arrangement of the bond portions 22 a, and the minimum number of arrangements (two rows) in the longitudinal direction. By doing so, the length of the diode chip is reduced.

本実施の形態でも、電力用トランジスタ１又は電力用ダイオード２とのシングルボンド数分の増加に伴い、単位ワイヤ当たりの電流を軽減して、パワーサイクル寿命を向上させることが出来る。   Also in the present embodiment, as the number of single bonds with the power transistor 1 or the power diode 2 increases, the current per unit wire can be reduced and the power cycle life can be improved.

尚、電力用ダイオード２のアノード電極１４上に３列以上のボンド部配列を設ける場合には、電力用ダイオード２のチップサイズの点と総合して最適化を図る必要性がある。   In the case where three or more rows of bond portion arrays are provided on the anode electrode 14 of the power diode 2, it is necessary to perform optimization in view of the chip size of the power diode 2.

又、本実施の形態の変形例を、図５に示す。図５の構造の特徴点は、図４の２列に配列されたボンド位置における実施の形態２に対して、２つのシングルボンド部２１ｂ，２１ｃと２つの主電流ワイヤのボンド部２２ａとを一組として当該組を交互に幅方向に配置して成るボンド配置例とした点にある。ここで、この様なボンド配置例を「オフセット配置」と定義することにする。   A modification of the present embodiment is shown in FIG. The feature of the structure in FIG. 5 is that two single bond portions 21b and 21c and two main current wire bond portions 22a are combined with each other in the second embodiment at the bond positions arranged in two rows in FIG. It is the point made into the example of a bond arrangement | positioning formed by arrange | positioning the said group alternately in the width direction as a group. Here, such an example of bond arrangement is defined as “offset arrangement”.

この様なオフセット配置を有する本変形例の電力半導体装置では、シングルボンド部２１ｂ，２１ｃ同士が近接配置されているために、アノード電極膜に形成される通電路の電気抵抗を小さくすることが出来るので、シングルボンド１７ａ，１７ｂへの電流の分配を増大させることが出来、主電流ワイヤ１０の電流密度をより一層低減化することが出来る。   In the power semiconductor device of this modification having such an offset arrangement, since the single bond portions 21b and 21c are arranged close to each other, the electric resistance of the current path formed in the anode electrode film can be reduced. Therefore, the current distribution to the single bonds 17a and 17b can be increased, and the current density of the main current wire 10 can be further reduced.

（付記）
以上、本発明の実施の形態を詳細に開示し記述したが、以上の記述は本発明の適用可能な局面を例示したものであって、本発明はこれに限定されるものではない。即ち、記述した局面に対する様々な修正や変形例を、この発明の範囲から逸脱することの無い範囲内で考えることが可能である。例えば、本発明を、ＩＧＢＴのみならず、ＭＯＳＦＥＴやＧＴＯ等、その他の電力用スイッチング半導体素子を用いた実施の形態に対しても適用可能である。 (Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention. For example, the present invention can be applied not only to an IGBT but also to an embodiment using other power switching semiconductor elements such as MOSFET and GTO.

実施の形態１に係る電力半導体装置の内部構造を示す俯瞰図である。1 is an overhead view showing an internal structure of a power semiconductor device according to a first embodiment. 実施の形態１に於ける、電力用トランジスタ、電力用ダイオード及びこれらの素子の電気的な接続構成を示す平面図である。FIG. 3 is a plan view showing a power transistor, a power diode, and an electrical connection configuration of these elements in the first embodiment. 実施の形態１の変形例に於ける、電力用トランジスタ、電力用ダイオード及びこれらの素子の電気的な接続構成を示す平面図である。FIG. 5 is a plan view showing a power transistor, a power diode, and an electrical connection configuration of these elements in a modification of the first embodiment. 実施の形態２に於ける、電力用トランジスタ、電力用ダイオード及びこれらの素子の電気的な接続構成を示す平面図である。FIG. 6 is a plan view showing a power transistor, a power diode, and an electrical connection configuration of these elements in the second embodiment. 実施の形態２の変形例に於ける、電力用トランジスタ、電力用ダイオード及びこれらの素子の電気的な接続構成を示す平面図である。FIG. 10 is a plan view showing a power transistor, a power diode, and an electrical connection configuration of these elements in a modification of the second embodiment. 従来例に係る電力半導体装置の内部構造を示す俯瞰図である。It is an overhead view which shows the internal structure of the power semiconductor device which concerns on a prior art example. 従来例に於ける、電力用トランジスタ、電力用ダイオード及びこれらの素子の電気的な接続構成を示す平面図である。It is a top view which shows the electric connection structure of the power transistor, power diode, and these elements in a prior art example.

符号の説明Explanation of symbols

１ 電力用トランジスタ、２ 電力用ダイオード、３ 基板、４ 金属パターン、５ 第１主端子、６ 第２主端子、７ 信号端子、８ ベース板、９ ケース、１０ 主電流ワイヤ、１３ エミッタ電極、１４ アノード電極、１７ａ，１７ｂ シングルボンド、２１ａ，２１ｂ，２１ｃ，２１ｄ シングルボンド部、２２ａ 主電流ワイヤのボンド部。
DESCRIPTION OF SYMBOLS 1 Power transistor, 2 Power diode, 3 Substrate, 4 Metal pattern, 5 1st main terminal, 6 2nd main terminal, 7 Signal terminal, 8 Base board, 9 Case, 10 Main current wire, 13 Emitter electrode, 14 Anode electrode, 17a, 17b Single bond, 21a, 21b, 21c, 21d Single bond part, 22a Bond part of main current wire.

Claims (4)

電力用スイッチング半導体素子及び電力用ダイオードを搭載した基板と第１及び第２主端子とを有し、前記電力用スイッチング半導体素子の第１主電極と前記電力用ダイオードのカソード電極と前記第１主端子とを前記基板上の金属パターンによって電気的に接続し、前記電力用スイッチング半導体素子の第２主電極と前記電力用ダイオードのアノード電極と前記第２主端子とを連続的にワイヤボンドして前記アノード電極上に主電流ワイヤのボンド部を形成することによって電気的に接続してなる電力半導体装置において、
前記電力用スイッチング半導体素子の前記第２主電極及び前記電力用ダイオードの前記アノード電極の両方にシングルボンド部を有するボンディングワイヤを形成したことを特徴とする、
電力半導体装置。 A power switching semiconductor element and a substrate on which the power diode is mounted, and first and second main terminals, the first main electrode of the power switching semiconductor element, the cathode electrode of the power diode, and the first main terminal. Terminals are electrically connected by a metal pattern on the substrate, and the second main electrode of the power switching semiconductor element, the anode electrode of the power diode, and the second main terminal are continuously wire-bonded. In the power semiconductor device that is electrically connected by forming a bond portion of the main current wire on the anode electrode,
A bonding wire having a single bond portion is formed on both the second main electrode of the power switching semiconductor element and the anode electrode of the power diode.
Power semiconductor device. 請求項１記載の電力半導体装置であって、
前記アノード電極及び前記第２主端子の両方にシングルボンド部を有する別のボンディングワイヤを前記アノード電極と前記第２主端子間にも形成したことを特徴とする、
電力半導体装置。 The power semiconductor device according to claim 1,
Another bonding wire having a single bond portion on both the anode electrode and the second main terminal is also formed between the anode electrode and the second main terminal.
Power semiconductor device. 請求項２記載の電力半導体装置であって、
前記主電流ワイヤのボンド部と、前記ボンディングワイヤ及び前記別のボンディングワイヤの各々の前記アノード電極上の前記シングルボンド部とが、それぞれ、前記アノード電極上に少なくとも２列に並列して配置されたボンド位置の任意の位置に形成されたことを特徴とする、
電力半導体装置。 The power semiconductor device according to claim 2,
The bond portion of the main current wire and the single bond portion on the anode electrode of each of the bonding wire and the another bonding wire are arranged in parallel in at least two rows on the anode electrode. It is formed at any position of the bond position,
Power semiconductor device. 請求項３記載の電力半導体装置であって、
前記ボンド位置は２列に並列して配置されており、前記ボンディングワイヤ及び前記別のボンディングワイヤの各々の前記アノード電極上の前記シングルボンド部と前記ボンド部とが前記ボンド位置に於いてオフセット配置されていることを特徴とする、
電力半導体装置。
The power semiconductor device according to claim 3,
The bond positions are arranged in parallel in two rows, and the single bond part and the bond part on the anode electrode of each of the bonding wire and the another bonding wire are offset at the bond position. It is characterized by being
Power semiconductor device.
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